dc/dcn31/dcn31_resource.h

0001 /*
0002  * Copyright 2020 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef _DCN31_RESOURCE_H_
0027 #define _DCN31_RESOURCE_H_
0028
0029 #include "core_types.h"
0030
0031 #define TO_DCN31_RES_POOL(pool)\
0032     container_of(pool, struct dcn31_resource_pool, base)
0033
0034 extern struct _vcs_dpi_ip_params_st dcn3_1_ip;
0035
0036 struct dcn31_resource_pool {
0037     struct resource_pool base;
0038 };
0039
0040 bool dcn31_validate_bandwidth(struct dc *dc,
0041         struct dc_state *context,
0042         bool fast_validate);
0043 void dcn31_calculate_wm_and_dlg(
0044         struct dc *dc, struct dc_state *context,
0045         display_e2e_pipe_params_st *pipes,
0046         int pipe_cnt,
0047         int vlevel);
0048 int dcn31_populate_dml_pipes_from_context(
0049     struct dc *dc, struct dc_state *context,
0050     display_e2e_pipe_params_st *pipes,
0051     bool fast_validate);
0052 void
0053 dcn31_populate_dml_writeback_from_context(struct dc *dc,
0054                       struct resource_context *res_ctx,
0055                       display_e2e_pipe_params_st *pipes);
0056 void
0057 dcn31_set_mcif_arb_params(struct dc *dc,
0058               struct dc_state *context,
0059               display_e2e_pipe_params_st *pipes,
0060               int pipe_cnt);
0061
0062 struct resource_pool *dcn31_create_resource_pool(
0063         const struct dc_init_data *init_data,
0064         struct dc *dc);
0065
0066 /*temp: B0 specific before switch to dcn313 headers*/
0067 #ifndef regPHYPLLF_PIXCLK_RESYNC_CNTL
0068 #define regPHYPLLF_PIXCLK_RESYNC_CNTL 0x007e
0069 #define regPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX 1
0070 #define regPHYPLLG_PIXCLK_RESYNC_CNTL 0x005f
0071 #define regPHYPLLG_PIXCLK_RESYNC_CNTL_BASE_IDX 1
0072
0073 //PHYPLLF_PIXCLK_RESYNC_CNTL
0074 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
0075 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1
0076 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
0077 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE__SHIFT 0x8
0078 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
0079 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
0080 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L
0081 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
0082 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE_MASK 0x00000100L
0083 #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
0084
0085 //PHYPLLG_PIXCLK_RESYNC_CNTL
0086 #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
0087 #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1
0088 #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
0089 #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_ENABLE__SHIFT 0x8
0090 #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
0091 #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
0092 #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L
0093 #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
0094 #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_ENABLE_MASK 0x00000100L
0095 #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
0096 #endif
0097 #endif /* _DCN31_RESOURCE_H_ */