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0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 
0026 
0027 #include "dm_services.h"
0028 #include "dc.h"
0029 
0030 #include "dcn31/dcn31_init.h"
0031 
0032 #include "resource.h"
0033 #include "include/irq_service_interface.h"
0034 #include "dcn31_resource.h"
0035 
0036 #include "dcn20/dcn20_resource.h"
0037 #include "dcn30/dcn30_resource.h"
0038 
0039 #include "dml/dcn30/dcn30_fpu.h"
0040 
0041 #include "dcn10/dcn10_ipp.h"
0042 #include "dcn30/dcn30_hubbub.h"
0043 #include "dcn31/dcn31_hubbub.h"
0044 #include "dcn30/dcn30_mpc.h"
0045 #include "dcn31/dcn31_hubp.h"
0046 #include "irq/dcn31/irq_service_dcn31.h"
0047 #include "dcn30/dcn30_dpp.h"
0048 #include "dcn31/dcn31_optc.h"
0049 #include "dcn20/dcn20_hwseq.h"
0050 #include "dcn30/dcn30_hwseq.h"
0051 #include "dce110/dce110_hw_sequencer.h"
0052 #include "dcn30/dcn30_opp.h"
0053 #include "dcn20/dcn20_dsc.h"
0054 #include "dcn30/dcn30_vpg.h"
0055 #include "dcn30/dcn30_afmt.h"
0056 #include "dcn30/dcn30_dio_stream_encoder.h"
0057 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
0058 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
0059 #include "dcn31/dcn31_apg.h"
0060 #include "dcn31/dcn31_dio_link_encoder.h"
0061 #include "dcn31/dcn31_vpg.h"
0062 #include "dcn31/dcn31_afmt.h"
0063 #include "dce/dce_clock_source.h"
0064 #include "dce/dce_audio.h"
0065 #include "dce/dce_hwseq.h"
0066 #include "clk_mgr.h"
0067 #include "virtual/virtual_stream_encoder.h"
0068 #include "dce110/dce110_resource.h"
0069 #include "dml/display_mode_vba.h"
0070 #include "dml/dcn31/dcn31_fpu.h"
0071 #include "dcn31/dcn31_dccg.h"
0072 #include "dcn10/dcn10_resource.h"
0073 #include "dcn31_panel_cntl.h"
0074 
0075 #include "dcn30/dcn30_dwb.h"
0076 #include "dcn30/dcn30_mmhubbub.h"
0077 
0078 // TODO: change include headers /amd/include/asic_reg after upstream
0079 #include "yellow_carp_offset.h"
0080 #include "dcn/dcn_3_1_2_offset.h"
0081 #include "dcn/dcn_3_1_2_sh_mask.h"
0082 #include "nbio/nbio_7_2_0_offset.h"
0083 #include "dpcs/dpcs_4_2_0_offset.h"
0084 #include "dpcs/dpcs_4_2_0_sh_mask.h"
0085 #include "mmhub/mmhub_2_3_0_offset.h"
0086 #include "mmhub/mmhub_2_3_0_sh_mask.h"
0087 
0088 
0089 #define regDCHUBBUB_DEBUG_CTRL_0                                              0x04d6
0090 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX                                     2
0091 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT                               0x10
0092 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK                                 0x01FF0000L
0093 
0094 #include "reg_helper.h"
0095 #include "dce/dmub_abm.h"
0096 #include "dce/dmub_psr.h"
0097 #include "dce/dce_aux.h"
0098 #include "dce/dce_i2c.h"
0099 
0100 #include "dml/dcn30/display_mode_vba_30.h"
0101 #include "vm_helper.h"
0102 #include "dcn20/dcn20_vmid.h"
0103 
0104 #include "link_enc_cfg.h"
0105 
0106 #define DC_LOGGER_INIT(logger)
0107 
0108 enum dcn31_clk_src_array_id {
0109     DCN31_CLK_SRC_PLL0,
0110     DCN31_CLK_SRC_PLL1,
0111     DCN31_CLK_SRC_PLL2,
0112     DCN31_CLK_SRC_PLL3,
0113     DCN31_CLK_SRC_PLL4,
0114     DCN30_CLK_SRC_TOTAL
0115 };
0116 
0117 /* begin *********************
0118  * macros to expend register list macro defined in HW object header file
0119  */
0120 
0121 /* DCN */
0122 /* TODO awful hack. fixup dcn20_dwb.h */
0123 #undef BASE_INNER
0124 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
0125 
0126 #define BASE(seg) BASE_INNER(seg)
0127 
0128 #define SR(reg_name)\
0129         .reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
0130                     reg ## reg_name
0131 
0132 #define SRI(reg_name, block, id)\
0133     .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0134                     reg ## block ## id ## _ ## reg_name
0135 
0136 #define SRI2(reg_name, block, id)\
0137     .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
0138                     reg ## reg_name
0139 
0140 #define SRIR(var_name, reg_name, block, id)\
0141     .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0142                     reg ## block ## id ## _ ## reg_name
0143 
0144 #define SRII(reg_name, block, id)\
0145     .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0146                     reg ## block ## id ## _ ## reg_name
0147 
0148 #define SRII_MPC_RMU(reg_name, block, id)\
0149     .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0150                     reg ## block ## id ## _ ## reg_name
0151 
0152 #define SRII_DWB(reg_name, temp_name, block, id)\
0153     .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
0154                     reg ## block ## id ## _ ## temp_name
0155 
0156 #define DCCG_SRII(reg_name, block, id)\
0157     .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0158                     reg ## block ## id ## _ ## reg_name
0159 
0160 #define VUPDATE_SRII(reg_name, block, id)\
0161     .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
0162                     reg ## reg_name ## _ ## block ## id
0163 
0164 /* NBIO */
0165 #define NBIO_BASE_INNER(seg) \
0166     NBIO_BASE__INST0_SEG ## seg
0167 
0168 #define NBIO_BASE(seg) \
0169     NBIO_BASE_INNER(seg)
0170 
0171 #define NBIO_SR(reg_name)\
0172         .reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
0173                     regBIF_BX1_ ## reg_name
0174 
0175 /* MMHUB */
0176 #define MMHUB_BASE_INNER(seg) \
0177     MMHUB_BASE__INST0_SEG ## seg
0178 
0179 #define MMHUB_BASE(seg) \
0180     MMHUB_BASE_INNER(seg)
0181 
0182 #define MMHUB_SR(reg_name)\
0183         .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
0184                     mm ## reg_name
0185 
0186 /* CLOCK */
0187 #define CLK_BASE_INNER(seg) \
0188     CLK_BASE__INST0_SEG ## seg
0189 
0190 #define CLK_BASE(seg) \
0191     CLK_BASE_INNER(seg)
0192 
0193 #define CLK_SRI(reg_name, block, inst)\
0194     .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
0195                     reg ## block ## _ ## inst ## _ ## reg_name
0196 
0197 
0198 static const struct bios_registers bios_regs = {
0199         NBIO_SR(BIOS_SCRATCH_3),
0200         NBIO_SR(BIOS_SCRATCH_6)
0201 };
0202 
0203 #define clk_src_regs(index, pllid)\
0204 [index] = {\
0205     CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
0206 }
0207 
0208 static const struct dce110_clk_src_regs clk_src_regs[] = {
0209     clk_src_regs(0, A),
0210     clk_src_regs(1, B),
0211     clk_src_regs(2, C),
0212     clk_src_regs(3, D),
0213     clk_src_regs(4, E)
0214 };
0215 /*pll_id being rempped in dmub, in driver it is logical instance*/
0216 static const struct dce110_clk_src_regs clk_src_regs_b0[] = {
0217     clk_src_regs(0, A),
0218     clk_src_regs(1, B),
0219     clk_src_regs(2, F),
0220     clk_src_regs(3, G),
0221     clk_src_regs(4, E)
0222 };
0223 
0224 static const struct dce110_clk_src_shift cs_shift = {
0225         CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
0226 };
0227 
0228 static const struct dce110_clk_src_mask cs_mask = {
0229         CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
0230 };
0231 
0232 #define abm_regs(id)\
0233 [id] = {\
0234         ABM_DCN302_REG_LIST(id)\
0235 }
0236 
0237 static const struct dce_abm_registers abm_regs[] = {
0238         abm_regs(0),
0239         abm_regs(1),
0240         abm_regs(2),
0241         abm_regs(3),
0242 };
0243 
0244 static const struct dce_abm_shift abm_shift = {
0245         ABM_MASK_SH_LIST_DCN30(__SHIFT)
0246 };
0247 
0248 static const struct dce_abm_mask abm_mask = {
0249         ABM_MASK_SH_LIST_DCN30(_MASK)
0250 };
0251 
0252 #define audio_regs(id)\
0253 [id] = {\
0254         AUD_COMMON_REG_LIST(id)\
0255 }
0256 
0257 static const struct dce_audio_registers audio_regs[] = {
0258     audio_regs(0),
0259     audio_regs(1),
0260     audio_regs(2),
0261     audio_regs(3),
0262     audio_regs(4),
0263     audio_regs(5),
0264     audio_regs(6)
0265 };
0266 
0267 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
0268         SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
0269         SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
0270         AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
0271 
0272 static const struct dce_audio_shift audio_shift = {
0273         DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
0274 };
0275 
0276 static const struct dce_audio_mask audio_mask = {
0277         DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
0278 };
0279 
0280 #define vpg_regs(id)\
0281 [id] = {\
0282     VPG_DCN31_REG_LIST(id)\
0283 }
0284 
0285 static const struct dcn31_vpg_registers vpg_regs[] = {
0286     vpg_regs(0),
0287     vpg_regs(1),
0288     vpg_regs(2),
0289     vpg_regs(3),
0290     vpg_regs(4),
0291     vpg_regs(5),
0292     vpg_regs(6),
0293     vpg_regs(7),
0294     vpg_regs(8),
0295     vpg_regs(9),
0296 };
0297 
0298 static const struct dcn31_vpg_shift vpg_shift = {
0299     DCN31_VPG_MASK_SH_LIST(__SHIFT)
0300 };
0301 
0302 static const struct dcn31_vpg_mask vpg_mask = {
0303     DCN31_VPG_MASK_SH_LIST(_MASK)
0304 };
0305 
0306 #define afmt_regs(id)\
0307 [id] = {\
0308     AFMT_DCN31_REG_LIST(id)\
0309 }
0310 
0311 static const struct dcn31_afmt_registers afmt_regs[] = {
0312     afmt_regs(0),
0313     afmt_regs(1),
0314     afmt_regs(2),
0315     afmt_regs(3),
0316     afmt_regs(4),
0317     afmt_regs(5)
0318 };
0319 
0320 static const struct dcn31_afmt_shift afmt_shift = {
0321     DCN31_AFMT_MASK_SH_LIST(__SHIFT)
0322 };
0323 
0324 static const struct dcn31_afmt_mask afmt_mask = {
0325     DCN31_AFMT_MASK_SH_LIST(_MASK)
0326 };
0327 
0328 #define apg_regs(id)\
0329 [id] = {\
0330     APG_DCN31_REG_LIST(id)\
0331 }
0332 
0333 static const struct dcn31_apg_registers apg_regs[] = {
0334     apg_regs(0),
0335     apg_regs(1),
0336     apg_regs(2),
0337     apg_regs(3)
0338 };
0339 
0340 static const struct dcn31_apg_shift apg_shift = {
0341     DCN31_APG_MASK_SH_LIST(__SHIFT)
0342 };
0343 
0344 static const struct dcn31_apg_mask apg_mask = {
0345         DCN31_APG_MASK_SH_LIST(_MASK)
0346 };
0347 
0348 #define stream_enc_regs(id)\
0349 [id] = {\
0350     SE_DCN3_REG_LIST(id)\
0351 }
0352 
0353 /* Some encoders won't be initialized here - but they're logical, not physical. */
0354 static const struct dcn10_stream_enc_registers stream_enc_regs[ENGINE_ID_COUNT] = {
0355     stream_enc_regs(0),
0356     stream_enc_regs(1),
0357     stream_enc_regs(2),
0358     stream_enc_regs(3),
0359     stream_enc_regs(4)
0360 };
0361 
0362 static const struct dcn10_stream_encoder_shift se_shift = {
0363         SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
0364 };
0365 
0366 static const struct dcn10_stream_encoder_mask se_mask = {
0367         SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
0368 };
0369 
0370 
0371 #define aux_regs(id)\
0372 [id] = {\
0373     DCN2_AUX_REG_LIST(id)\
0374 }
0375 
0376 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
0377         aux_regs(0),
0378         aux_regs(1),
0379         aux_regs(2),
0380         aux_regs(3),
0381         aux_regs(4)
0382 };
0383 
0384 #define hpd_regs(id)\
0385 [id] = {\
0386     HPD_REG_LIST(id)\
0387 }
0388 
0389 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
0390         hpd_regs(0),
0391         hpd_regs(1),
0392         hpd_regs(2),
0393         hpd_regs(3),
0394         hpd_regs(4)
0395 };
0396 
0397 #define link_regs(id, phyid)\
0398 [id] = {\
0399     LE_DCN31_REG_LIST(id), \
0400     UNIPHY_DCN2_REG_LIST(phyid), \
0401     DPCS_DCN31_REG_LIST(id), \
0402 }
0403 
0404 static const struct dce110_aux_registers_shift aux_shift = {
0405     DCN_AUX_MASK_SH_LIST(__SHIFT)
0406 };
0407 
0408 static const struct dce110_aux_registers_mask aux_mask = {
0409     DCN_AUX_MASK_SH_LIST(_MASK)
0410 };
0411 
0412 static const struct dcn10_link_enc_registers link_enc_regs[] = {
0413     link_regs(0, A),
0414     link_regs(1, B),
0415     link_regs(2, C),
0416     link_regs(3, D),
0417     link_regs(4, E)
0418 };
0419 
0420 static const struct dcn10_link_enc_shift le_shift = {
0421     LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
0422     DPCS_DCN31_MASK_SH_LIST(__SHIFT)
0423 };
0424 
0425 static const struct dcn10_link_enc_mask le_mask = {
0426     LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
0427     DPCS_DCN31_MASK_SH_LIST(_MASK)
0428 };
0429 
0430 #define hpo_dp_stream_encoder_reg_list(id)\
0431 [id] = {\
0432     DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
0433 }
0434 
0435 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
0436     hpo_dp_stream_encoder_reg_list(0),
0437     hpo_dp_stream_encoder_reg_list(1),
0438     hpo_dp_stream_encoder_reg_list(2),
0439     hpo_dp_stream_encoder_reg_list(3),
0440 };
0441 
0442 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
0443     DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
0444 };
0445 
0446 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
0447     DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
0448 };
0449 
0450 #define hpo_dp_link_encoder_reg_list(id)\
0451 [id] = {\
0452     DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
0453     DCN3_1_RDPCSTX_REG_LIST(0),\
0454     DCN3_1_RDPCSTX_REG_LIST(1),\
0455     DCN3_1_RDPCSTX_REG_LIST(2),\
0456     DCN3_1_RDPCSTX_REG_LIST(3),\
0457     DCN3_1_RDPCSTX_REG_LIST(4)\
0458 }
0459 
0460 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
0461     hpo_dp_link_encoder_reg_list(0),
0462     hpo_dp_link_encoder_reg_list(1),
0463 };
0464 
0465 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
0466     DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
0467 };
0468 
0469 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
0470     DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
0471 };
0472 
0473 #define dpp_regs(id)\
0474 [id] = {\
0475     DPP_REG_LIST_DCN30(id),\
0476 }
0477 
0478 static const struct dcn3_dpp_registers dpp_regs[] = {
0479     dpp_regs(0),
0480     dpp_regs(1),
0481     dpp_regs(2),
0482     dpp_regs(3)
0483 };
0484 
0485 static const struct dcn3_dpp_shift tf_shift = {
0486         DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
0487 };
0488 
0489 static const struct dcn3_dpp_mask tf_mask = {
0490         DPP_REG_LIST_SH_MASK_DCN30(_MASK)
0491 };
0492 
0493 #define opp_regs(id)\
0494 [id] = {\
0495     OPP_REG_LIST_DCN30(id),\
0496 }
0497 
0498 static const struct dcn20_opp_registers opp_regs[] = {
0499     opp_regs(0),
0500     opp_regs(1),
0501     opp_regs(2),
0502     opp_regs(3)
0503 };
0504 
0505 static const struct dcn20_opp_shift opp_shift = {
0506     OPP_MASK_SH_LIST_DCN20(__SHIFT)
0507 };
0508 
0509 static const struct dcn20_opp_mask opp_mask = {
0510     OPP_MASK_SH_LIST_DCN20(_MASK)
0511 };
0512 
0513 #define aux_engine_regs(id)\
0514 [id] = {\
0515     AUX_COMMON_REG_LIST0(id), \
0516     .AUXN_IMPCAL = 0, \
0517     .AUXP_IMPCAL = 0, \
0518     .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
0519 }
0520 
0521 static const struct dce110_aux_registers aux_engine_regs[] = {
0522         aux_engine_regs(0),
0523         aux_engine_regs(1),
0524         aux_engine_regs(2),
0525         aux_engine_regs(3),
0526         aux_engine_regs(4)
0527 };
0528 
0529 #define dwbc_regs_dcn3(id)\
0530 [id] = {\
0531     DWBC_COMMON_REG_LIST_DCN30(id),\
0532 }
0533 
0534 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
0535     dwbc_regs_dcn3(0),
0536 };
0537 
0538 static const struct dcn30_dwbc_shift dwbc30_shift = {
0539     DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
0540 };
0541 
0542 static const struct dcn30_dwbc_mask dwbc30_mask = {
0543     DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
0544 };
0545 
0546 #define mcif_wb_regs_dcn3(id)\
0547 [id] = {\
0548     MCIF_WB_COMMON_REG_LIST_DCN30(id),\
0549 }
0550 
0551 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
0552     mcif_wb_regs_dcn3(0)
0553 };
0554 
0555 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
0556     MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
0557 };
0558 
0559 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
0560     MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
0561 };
0562 
0563 #define dsc_regsDCN20(id)\
0564 [id] = {\
0565     DSC_REG_LIST_DCN20(id)\
0566 }
0567 
0568 static const struct dcn20_dsc_registers dsc_regs[] = {
0569     dsc_regsDCN20(0),
0570     dsc_regsDCN20(1),
0571     dsc_regsDCN20(2)
0572 };
0573 
0574 static const struct dcn20_dsc_shift dsc_shift = {
0575     DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
0576 };
0577 
0578 static const struct dcn20_dsc_mask dsc_mask = {
0579     DSC_REG_LIST_SH_MASK_DCN20(_MASK)
0580 };
0581 
0582 static const struct dcn30_mpc_registers mpc_regs = {
0583         MPC_REG_LIST_DCN3_0(0),
0584         MPC_REG_LIST_DCN3_0(1),
0585         MPC_REG_LIST_DCN3_0(2),
0586         MPC_REG_LIST_DCN3_0(3),
0587         MPC_OUT_MUX_REG_LIST_DCN3_0(0),
0588         MPC_OUT_MUX_REG_LIST_DCN3_0(1),
0589         MPC_OUT_MUX_REG_LIST_DCN3_0(2),
0590         MPC_OUT_MUX_REG_LIST_DCN3_0(3),
0591         MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
0592         MPC_RMU_REG_LIST_DCN3AG(0),
0593         MPC_RMU_REG_LIST_DCN3AG(1),
0594         //MPC_RMU_REG_LIST_DCN3AG(2),
0595         MPC_DWB_MUX_REG_LIST_DCN3_0(0),
0596 };
0597 
0598 static const struct dcn30_mpc_shift mpc_shift = {
0599     MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
0600 };
0601 
0602 static const struct dcn30_mpc_mask mpc_mask = {
0603     MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
0604 };
0605 
0606 #define optc_regs(id)\
0607 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)}
0608 
0609 static const struct dcn_optc_registers optc_regs[] = {
0610     optc_regs(0),
0611     optc_regs(1),
0612     optc_regs(2),
0613     optc_regs(3)
0614 };
0615 
0616 static const struct dcn_optc_shift optc_shift = {
0617     OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT)
0618 };
0619 
0620 static const struct dcn_optc_mask optc_mask = {
0621     OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK)
0622 };
0623 
0624 #define hubp_regs(id)\
0625 [id] = {\
0626     HUBP_REG_LIST_DCN30(id)\
0627 }
0628 
0629 static const struct dcn_hubp2_registers hubp_regs[] = {
0630         hubp_regs(0),
0631         hubp_regs(1),
0632         hubp_regs(2),
0633         hubp_regs(3)
0634 };
0635 
0636 
0637 static const struct dcn_hubp2_shift hubp_shift = {
0638         HUBP_MASK_SH_LIST_DCN31(__SHIFT)
0639 };
0640 
0641 static const struct dcn_hubp2_mask hubp_mask = {
0642         HUBP_MASK_SH_LIST_DCN31(_MASK)
0643 };
0644 static const struct dcn_hubbub_registers hubbub_reg = {
0645         HUBBUB_REG_LIST_DCN31(0)
0646 };
0647 
0648 static const struct dcn_hubbub_shift hubbub_shift = {
0649         HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)
0650 };
0651 
0652 static const struct dcn_hubbub_mask hubbub_mask = {
0653         HUBBUB_MASK_SH_LIST_DCN31(_MASK)
0654 };
0655 
0656 static const struct dccg_registers dccg_regs = {
0657         DCCG_REG_LIST_DCN31()
0658 };
0659 
0660 static const struct dccg_shift dccg_shift = {
0661         DCCG_MASK_SH_LIST_DCN31(__SHIFT)
0662 };
0663 
0664 static const struct dccg_mask dccg_mask = {
0665         DCCG_MASK_SH_LIST_DCN31(_MASK)
0666 };
0667 
0668 
0669 #define SRII2(reg_name_pre, reg_name_post, id)\
0670     .reg_name_pre ## _ ##  reg_name_post[id] = BASE(reg ## reg_name_pre \
0671             ## id ## _ ## reg_name_post ## _BASE_IDX) + \
0672             reg ## reg_name_pre ## id ## _ ## reg_name_post
0673 
0674 
0675 #define HWSEQ_DCN31_REG_LIST()\
0676     SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
0677     SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
0678     SR(DIO_MEM_PWR_CTRL), \
0679     SR(ODM_MEM_PWR_CTRL3), \
0680     SR(DMU_MEM_PWR_CNTL), \
0681     SR(MMHUBBUB_MEM_PWR_CNTL), \
0682     SR(DCCG_GATE_DISABLE_CNTL), \
0683     SR(DCCG_GATE_DISABLE_CNTL2), \
0684     SR(DCFCLK_CNTL),\
0685     SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
0686     SRII(PIXEL_RATE_CNTL, OTG, 0), \
0687     SRII(PIXEL_RATE_CNTL, OTG, 1),\
0688     SRII(PIXEL_RATE_CNTL, OTG, 2),\
0689     SRII(PIXEL_RATE_CNTL, OTG, 3),\
0690     SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
0691     SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
0692     SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
0693     SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
0694     SR(MICROSECOND_TIME_BASE_DIV), \
0695     SR(MILLISECOND_TIME_BASE_DIV), \
0696     SR(DISPCLK_FREQ_CHANGE_CNTL), \
0697     SR(RBBMIF_TIMEOUT_DIS), \
0698     SR(RBBMIF_TIMEOUT_DIS_2), \
0699     SR(DCHUBBUB_CRC_CTRL), \
0700     SR(DPP_TOP0_DPP_CRC_CTRL), \
0701     SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
0702     SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
0703     SR(MPC_CRC_CTRL), \
0704     SR(MPC_CRC_RESULT_GB), \
0705     SR(MPC_CRC_RESULT_C), \
0706     SR(MPC_CRC_RESULT_AR), \
0707     SR(DOMAIN0_PG_CONFIG), \
0708     SR(DOMAIN1_PG_CONFIG), \
0709     SR(DOMAIN2_PG_CONFIG), \
0710     SR(DOMAIN3_PG_CONFIG), \
0711     SR(DOMAIN16_PG_CONFIG), \
0712     SR(DOMAIN17_PG_CONFIG), \
0713     SR(DOMAIN18_PG_CONFIG), \
0714     SR(DOMAIN0_PG_STATUS), \
0715     SR(DOMAIN1_PG_STATUS), \
0716     SR(DOMAIN2_PG_STATUS), \
0717     SR(DOMAIN3_PG_STATUS), \
0718     SR(DOMAIN16_PG_STATUS), \
0719     SR(DOMAIN17_PG_STATUS), \
0720     SR(DOMAIN18_PG_STATUS), \
0721     SR(D1VGA_CONTROL), \
0722     SR(D2VGA_CONTROL), \
0723     SR(D3VGA_CONTROL), \
0724     SR(D4VGA_CONTROL), \
0725     SR(D5VGA_CONTROL), \
0726     SR(D6VGA_CONTROL), \
0727     SR(DC_IP_REQUEST_CNTL), \
0728     SR(AZALIA_AUDIO_DTO), \
0729     SR(AZALIA_CONTROLLER_CLOCK_GATING), \
0730     SR(HPO_TOP_HW_CONTROL)
0731 
0732 static const struct dce_hwseq_registers hwseq_reg = {
0733         HWSEQ_DCN31_REG_LIST()
0734 };
0735 
0736 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\
0737     HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
0738     HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
0739     HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
0740     HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
0741     HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
0742     HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
0743     HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
0744     HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
0745     HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
0746     HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
0747     HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
0748     HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
0749     HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
0750     HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
0751     HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
0752     HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
0753     HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
0754     HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
0755     HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
0756     HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
0757     HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
0758     HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
0759     HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
0760     HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
0761     HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
0762     HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
0763     HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
0764     HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
0765     HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
0766     HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
0767     HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \
0768     HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
0769     HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh)
0770 
0771 static const struct dce_hwseq_shift hwseq_shift = {
0772         HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)
0773 };
0774 
0775 static const struct dce_hwseq_mask hwseq_mask = {
0776         HWSEQ_DCN31_MASK_SH_LIST(_MASK)
0777 };
0778 #define vmid_regs(id)\
0779 [id] = {\
0780         DCN20_VMID_REG_LIST(id)\
0781 }
0782 
0783 static const struct dcn_vmid_registers vmid_regs[] = {
0784     vmid_regs(0),
0785     vmid_regs(1),
0786     vmid_regs(2),
0787     vmid_regs(3),
0788     vmid_regs(4),
0789     vmid_regs(5),
0790     vmid_regs(6),
0791     vmid_regs(7),
0792     vmid_regs(8),
0793     vmid_regs(9),
0794     vmid_regs(10),
0795     vmid_regs(11),
0796     vmid_regs(12),
0797     vmid_regs(13),
0798     vmid_regs(14),
0799     vmid_regs(15)
0800 };
0801 
0802 static const struct dcn20_vmid_shift vmid_shifts = {
0803         DCN20_VMID_MASK_SH_LIST(__SHIFT)
0804 };
0805 
0806 static const struct dcn20_vmid_mask vmid_masks = {
0807         DCN20_VMID_MASK_SH_LIST(_MASK)
0808 };
0809 
0810 static const struct resource_caps res_cap_dcn31 = {
0811     .num_timing_generator = 4,
0812     .num_opp = 4,
0813     .num_video_plane = 4,
0814     .num_audio = 5,
0815     .num_stream_encoder = 5,
0816     .num_dig_link_enc = 5,
0817     .num_hpo_dp_stream_encoder = 4,
0818     .num_hpo_dp_link_encoder = 2,
0819     .num_pll = 5,
0820     .num_dwb = 1,
0821     .num_ddc = 5,
0822     .num_vmid = 16,
0823     .num_mpc_3dlut = 2,
0824     .num_dsc = 3,
0825 };
0826 
0827 static const struct dc_plane_cap plane_cap = {
0828     .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
0829     .blends_with_above = true,
0830     .blends_with_below = true,
0831     .per_pixel_alpha = true,
0832 
0833     .pixel_format_support = {
0834             .argb8888 = true,
0835             .nv12 = true,
0836             .fp16 = true,
0837             .p010 = true,
0838             .ayuv = false,
0839     },
0840 
0841     .max_upscale_factor = {
0842             .argb8888 = 16000,
0843             .nv12 = 16000,
0844             .fp16 = 16000
0845     },
0846 
0847     // 6:1 downscaling ratio: 1000/6 = 166.666
0848     .max_downscale_factor = {
0849             .argb8888 = 167,
0850             .nv12 = 167,
0851             .fp16 = 167
0852     },
0853     64,
0854     64
0855 };
0856 
0857 static const struct dc_debug_options debug_defaults_drv = {
0858     .disable_dmcu = true,
0859     .force_abm_enable = false,
0860     .timing_trace = false,
0861     .clock_trace = true,
0862     .disable_pplib_clock_request = false,
0863     .pipe_split_policy = MPC_SPLIT_DYNAMIC,
0864     .force_single_disp_pipe_split = false,
0865     .disable_dcc = DCC_ENABLE,
0866     .vsr_support = true,
0867     .performance_trace = false,
0868     .max_downscale_src_width = 4096,/*upto true 4K*/
0869     .disable_pplib_wm_range = false,
0870     .scl_reset_length10 = true,
0871     .sanity_checks = true,
0872     .underflow_assert_delay_us = 0xFFFFFFFF,
0873     .dwb_fi_phase = -1, // -1 = disable,
0874     .dmub_command_table = true,
0875     .pstate_enabled = true,
0876     .use_max_lb = true,
0877     .enable_mem_low_power = {
0878         .bits = {
0879             .vga = true,
0880             .i2c = true,
0881             .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
0882             .dscl = true,
0883             .cm = true,
0884             .mpc = true,
0885             .optc = true,
0886             .vpg = true,
0887             .afmt = true,
0888         }
0889     },
0890     .disable_z10 = true,
0891     .optimize_edp_link_rate = true,
0892     .enable_sw_cntl_psr = true,
0893     .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/
0894     .dml_hostvm_override = DML_HOSTVM_OVERRIDE_FALSE,
0895 };
0896 
0897 static const struct dc_debug_options debug_defaults_diags = {
0898     .disable_dmcu = true,
0899     .force_abm_enable = false,
0900     .timing_trace = true,
0901     .clock_trace = true,
0902     .disable_dpp_power_gate = true,
0903     .disable_hubp_power_gate = true,
0904     .disable_clock_gate = true,
0905     .disable_pplib_clock_request = true,
0906     .disable_pplib_wm_range = true,
0907     .disable_stutter = false,
0908     .scl_reset_length10 = true,
0909     .dwb_fi_phase = -1, // -1 = disable
0910     .dmub_command_table = true,
0911     .enable_tri_buf = true,
0912     .use_max_lb = true
0913 };
0914 
0915 static void dcn31_dpp_destroy(struct dpp **dpp)
0916 {
0917     kfree(TO_DCN20_DPP(*dpp));
0918     *dpp = NULL;
0919 }
0920 
0921 static struct dpp *dcn31_dpp_create(
0922     struct dc_context *ctx,
0923     uint32_t inst)
0924 {
0925     struct dcn3_dpp *dpp =
0926         kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
0927 
0928     if (!dpp)
0929         return NULL;
0930 
0931     if (dpp3_construct(dpp, ctx, inst,
0932             &dpp_regs[inst], &tf_shift, &tf_mask))
0933         return &dpp->base;
0934 
0935     BREAK_TO_DEBUGGER();
0936     kfree(dpp);
0937     return NULL;
0938 }
0939 
0940 static struct output_pixel_processor *dcn31_opp_create(
0941     struct dc_context *ctx, uint32_t inst)
0942 {
0943     struct dcn20_opp *opp =
0944         kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
0945 
0946     if (!opp) {
0947         BREAK_TO_DEBUGGER();
0948         return NULL;
0949     }
0950 
0951     dcn20_opp_construct(opp, ctx, inst,
0952             &opp_regs[inst], &opp_shift, &opp_mask);
0953     return &opp->base;
0954 }
0955 
0956 static struct dce_aux *dcn31_aux_engine_create(
0957     struct dc_context *ctx,
0958     uint32_t inst)
0959 {
0960     struct aux_engine_dce110 *aux_engine =
0961         kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
0962 
0963     if (!aux_engine)
0964         return NULL;
0965 
0966     dce110_aux_engine_construct(aux_engine, ctx, inst,
0967                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
0968                     &aux_engine_regs[inst],
0969                     &aux_mask,
0970                     &aux_shift,
0971                     ctx->dc->caps.extended_aux_timeout_support);
0972 
0973     return &aux_engine->base;
0974 }
0975 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
0976 
0977 static const struct dce_i2c_registers i2c_hw_regs[] = {
0978         i2c_inst_regs(1),
0979         i2c_inst_regs(2),
0980         i2c_inst_regs(3),
0981         i2c_inst_regs(4),
0982         i2c_inst_regs(5),
0983 };
0984 
0985 static const struct dce_i2c_shift i2c_shifts = {
0986         I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
0987 };
0988 
0989 static const struct dce_i2c_mask i2c_masks = {
0990         I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
0991 };
0992 
0993 static struct dce_i2c_hw *dcn31_i2c_hw_create(
0994     struct dc_context *ctx,
0995     uint32_t inst)
0996 {
0997     struct dce_i2c_hw *dce_i2c_hw =
0998         kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
0999 
1000     if (!dce_i2c_hw)
1001         return NULL;
1002 
1003     dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1004                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1005 
1006     return dce_i2c_hw;
1007 }
1008 static struct mpc *dcn31_mpc_create(
1009         struct dc_context *ctx,
1010         int num_mpcc,
1011         int num_rmu)
1012 {
1013     struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
1014                       GFP_KERNEL);
1015 
1016     if (!mpc30)
1017         return NULL;
1018 
1019     dcn30_mpc_construct(mpc30, ctx,
1020             &mpc_regs,
1021             &mpc_shift,
1022             &mpc_mask,
1023             num_mpcc,
1024             num_rmu);
1025 
1026     return &mpc30->base;
1027 }
1028 
1029 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)
1030 {
1031     int i;
1032 
1033     struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
1034                       GFP_KERNEL);
1035 
1036     if (!hubbub3)
1037         return NULL;
1038 
1039     hubbub31_construct(hubbub3, ctx,
1040             &hubbub_reg,
1041             &hubbub_shift,
1042             &hubbub_mask,
1043             dcn3_1_ip.det_buffer_size_kbytes,
1044             dcn3_1_ip.pixel_chunk_size_kbytes,
1045             dcn3_1_ip.config_return_buffer_size_in_kbytes);
1046 
1047 
1048     for (i = 0; i < res_cap_dcn31.num_vmid; i++) {
1049         struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1050 
1051         vmid->ctx = ctx;
1052 
1053         vmid->regs = &vmid_regs[i];
1054         vmid->shifts = &vmid_shifts;
1055         vmid->masks = &vmid_masks;
1056     }
1057 
1058     return &hubbub3->base;
1059 }
1060 
1061 static struct timing_generator *dcn31_timing_generator_create(
1062         struct dc_context *ctx,
1063         uint32_t instance)
1064 {
1065     struct optc *tgn10 =
1066         kzalloc(sizeof(struct optc), GFP_KERNEL);
1067 
1068     if (!tgn10)
1069         return NULL;
1070 
1071     tgn10->base.inst = instance;
1072     tgn10->base.ctx = ctx;
1073 
1074     tgn10->tg_regs = &optc_regs[instance];
1075     tgn10->tg_shift = &optc_shift;
1076     tgn10->tg_mask = &optc_mask;
1077 
1078     dcn31_timing_generator_init(tgn10);
1079 
1080     return &tgn10->base;
1081 }
1082 
1083 static const struct encoder_feature_support link_enc_feature = {
1084         .max_hdmi_deep_color = COLOR_DEPTH_121212,
1085         .max_hdmi_pixel_clock = 600000,
1086         .hdmi_ycbcr420_supported = true,
1087         .dp_ycbcr420_supported = true,
1088         .fec_supported = true,
1089         .flags.bits.IS_HBR2_CAPABLE = true,
1090         .flags.bits.IS_HBR3_CAPABLE = true,
1091         .flags.bits.IS_TPS3_CAPABLE = true,
1092         .flags.bits.IS_TPS4_CAPABLE = true
1093 };
1094 
1095 static struct link_encoder *dcn31_link_encoder_create(
1096     struct dc_context *ctx,
1097     const struct encoder_init_data *enc_init_data)
1098 {
1099     struct dcn20_link_encoder *enc20 =
1100         kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1101 
1102     if (!enc20)
1103         return NULL;
1104 
1105     dcn31_link_encoder_construct(enc20,
1106             enc_init_data,
1107             &link_enc_feature,
1108             &link_enc_regs[enc_init_data->transmitter],
1109             &link_enc_aux_regs[enc_init_data->channel - 1],
1110             &link_enc_hpd_regs[enc_init_data->hpd_source],
1111             &le_shift,
1112             &le_mask);
1113 
1114     return &enc20->enc10.base;
1115 }
1116 
1117 /* Create a minimal link encoder object not associated with a particular
1118  * physical connector.
1119  * resource_funcs.link_enc_create_minimal
1120  */
1121 static struct link_encoder *dcn31_link_enc_create_minimal(
1122         struct dc_context *ctx, enum engine_id eng_id)
1123 {
1124     struct dcn20_link_encoder *enc20;
1125 
1126     if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1127         return NULL;
1128 
1129     enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1130     if (!enc20)
1131         return NULL;
1132 
1133     dcn31_link_encoder_construct_minimal(
1134             enc20,
1135             ctx,
1136             &link_enc_feature,
1137             &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1138             eng_id);
1139 
1140     return &enc20->enc10.base;
1141 }
1142 
1143 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1144 {
1145     struct dcn31_panel_cntl *panel_cntl =
1146         kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1147 
1148     if (!panel_cntl)
1149         return NULL;
1150 
1151     dcn31_panel_cntl_construct(panel_cntl, init_data);
1152 
1153     return &panel_cntl->base;
1154 }
1155 
1156 static void read_dce_straps(
1157     struct dc_context *ctx,
1158     struct resource_straps *straps)
1159 {
1160     generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1161         FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1162 
1163 }
1164 
1165 static struct audio *dcn31_create_audio(
1166         struct dc_context *ctx, unsigned int inst)
1167 {
1168     return dce_audio_create(ctx, inst,
1169             &audio_regs[inst], &audio_shift, &audio_mask);
1170 }
1171 
1172 static struct vpg *dcn31_vpg_create(
1173     struct dc_context *ctx,
1174     uint32_t inst)
1175 {
1176     struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1177 
1178     if (!vpg31)
1179         return NULL;
1180 
1181     vpg31_construct(vpg31, ctx, inst,
1182             &vpg_regs[inst],
1183             &vpg_shift,
1184             &vpg_mask);
1185 
1186     return &vpg31->base;
1187 }
1188 
1189 static struct afmt *dcn31_afmt_create(
1190     struct dc_context *ctx,
1191     uint32_t inst)
1192 {
1193     struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);
1194 
1195     if (!afmt31)
1196         return NULL;
1197 
1198     afmt31_construct(afmt31, ctx, inst,
1199             &afmt_regs[inst],
1200             &afmt_shift,
1201             &afmt_mask);
1202 
1203     // Light sleep by default, no need to power down here
1204 
1205     return &afmt31->base;
1206 }
1207 
1208 static struct apg *dcn31_apg_create(
1209     struct dc_context *ctx,
1210     uint32_t inst)
1211 {
1212     struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1213 
1214     if (!apg31)
1215         return NULL;
1216 
1217     apg31_construct(apg31, ctx, inst,
1218             &apg_regs[inst],
1219             &apg_shift,
1220             &apg_mask);
1221 
1222     return &apg31->base;
1223 }
1224 
1225 static struct stream_encoder *dcn31_stream_encoder_create(
1226     enum engine_id eng_id,
1227     struct dc_context *ctx)
1228 {
1229     struct dcn10_stream_encoder *enc1;
1230     struct vpg *vpg;
1231     struct afmt *afmt;
1232     int vpg_inst;
1233     int afmt_inst;
1234 
1235     /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1236     if (eng_id <= ENGINE_ID_DIGF) {
1237         vpg_inst = eng_id;
1238         afmt_inst = eng_id;
1239     } else
1240         return NULL;
1241 
1242     enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1243     vpg = dcn31_vpg_create(ctx, vpg_inst);
1244     afmt = dcn31_afmt_create(ctx, afmt_inst);
1245 
1246     if (!enc1 || !vpg || !afmt) {
1247         kfree(enc1);
1248         kfree(vpg);
1249         kfree(afmt);
1250         return NULL;
1251     }
1252 
1253     dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1254                     eng_id, vpg, afmt,
1255                     &stream_enc_regs[eng_id],
1256                     &se_shift, &se_mask);
1257 
1258     return &enc1->base;
1259 }
1260 
1261 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1262     enum engine_id eng_id,
1263     struct dc_context *ctx)
1264 {
1265     struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1266     struct vpg *vpg;
1267     struct apg *apg;
1268     uint32_t hpo_dp_inst;
1269     uint32_t vpg_inst;
1270     uint32_t apg_inst;
1271 
1272     ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1273     hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1274 
1275     /* Mapping of VPG register blocks to HPO DP block instance:
1276      * VPG[6] -> HPO_DP[0]
1277      * VPG[7] -> HPO_DP[1]
1278      * VPG[8] -> HPO_DP[2]
1279      * VPG[9] -> HPO_DP[3]
1280      */
1281     vpg_inst = hpo_dp_inst + 6;
1282 
1283     /* Mapping of APG register blocks to HPO DP block instance:
1284      * APG[0] -> HPO_DP[0]
1285      * APG[1] -> HPO_DP[1]
1286      * APG[2] -> HPO_DP[2]
1287      * APG[3] -> HPO_DP[3]
1288      */
1289     apg_inst = hpo_dp_inst;
1290 
1291     /* allocate HPO stream encoder and create VPG sub-block */
1292     hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1293     vpg = dcn31_vpg_create(ctx, vpg_inst);
1294     apg = dcn31_apg_create(ctx, apg_inst);
1295 
1296     if (!hpo_dp_enc31 || !vpg || !apg) {
1297         kfree(hpo_dp_enc31);
1298         kfree(vpg);
1299         kfree(apg);
1300         return NULL;
1301     }
1302 
1303     dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1304                     hpo_dp_inst, eng_id, vpg, apg,
1305                     &hpo_dp_stream_enc_regs[hpo_dp_inst],
1306                     &hpo_dp_se_shift, &hpo_dp_se_mask);
1307 
1308     return &hpo_dp_enc31->base;
1309 }
1310 
1311 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1312     uint8_t inst,
1313     struct dc_context *ctx)
1314 {
1315     struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1316 
1317     /* allocate HPO link encoder */
1318     hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1319 
1320     hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1321                     &hpo_dp_link_enc_regs[inst],
1322                     &hpo_dp_le_shift, &hpo_dp_le_mask);
1323 
1324     return &hpo_dp_enc31->base;
1325 }
1326 
1327 static struct dce_hwseq *dcn31_hwseq_create(
1328     struct dc_context *ctx)
1329 {
1330     struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1331 
1332     if (hws) {
1333         hws->ctx = ctx;
1334         hws->regs = &hwseq_reg;
1335         hws->shifts = &hwseq_shift;
1336         hws->masks = &hwseq_mask;
1337         /* DCN3.1 FPGA Workaround
1338          * Need to enable HPO DP Stream Encoder before setting OTG master enable.
1339          * To do so, move calling function enable_stream_timing to only be done AFTER calling
1340          * function core_link_enable_stream
1341          */
1342         if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
1343             hws->wa.dp_hpo_and_otg_sequence = true;
1344     }
1345     return hws;
1346 }
1347 static const struct resource_create_funcs res_create_funcs = {
1348     .read_dce_straps = read_dce_straps,
1349     .create_audio = dcn31_create_audio,
1350     .create_stream_encoder = dcn31_stream_encoder_create,
1351     .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1352     .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1353     .create_hwseq = dcn31_hwseq_create,
1354 };
1355 
1356 static const struct resource_create_funcs res_create_maximus_funcs = {
1357     .read_dce_straps = NULL,
1358     .create_audio = NULL,
1359     .create_stream_encoder = NULL,
1360     .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1361     .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1362     .create_hwseq = dcn31_hwseq_create,
1363 };
1364 
1365 static void dcn31_resource_destruct(struct dcn31_resource_pool *pool)
1366 {
1367     unsigned int i;
1368 
1369     for (i = 0; i < pool->base.stream_enc_count; i++) {
1370         if (pool->base.stream_enc[i] != NULL) {
1371             if (pool->base.stream_enc[i]->vpg != NULL) {
1372                 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1373                 pool->base.stream_enc[i]->vpg = NULL;
1374             }
1375             if (pool->base.stream_enc[i]->afmt != NULL) {
1376                 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1377                 pool->base.stream_enc[i]->afmt = NULL;
1378             }
1379             kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1380             pool->base.stream_enc[i] = NULL;
1381         }
1382     }
1383 
1384     for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1385         if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1386             if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1387                 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1388                 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1389             }
1390             if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1391                 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1392                 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1393             }
1394             kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1395             pool->base.hpo_dp_stream_enc[i] = NULL;
1396         }
1397     }
1398 
1399     for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1400         if (pool->base.hpo_dp_link_enc[i] != NULL) {
1401             kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1402             pool->base.hpo_dp_link_enc[i] = NULL;
1403         }
1404     }
1405 
1406     for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1407         if (pool->base.dscs[i] != NULL)
1408             dcn20_dsc_destroy(&pool->base.dscs[i]);
1409     }
1410 
1411     if (pool->base.mpc != NULL) {
1412         kfree(TO_DCN20_MPC(pool->base.mpc));
1413         pool->base.mpc = NULL;
1414     }
1415     if (pool->base.hubbub != NULL) {
1416         kfree(pool->base.hubbub);
1417         pool->base.hubbub = NULL;
1418     }
1419     for (i = 0; i < pool->base.pipe_count; i++) {
1420         if (pool->base.dpps[i] != NULL)
1421             dcn31_dpp_destroy(&pool->base.dpps[i]);
1422 
1423         if (pool->base.ipps[i] != NULL)
1424             pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1425 
1426         if (pool->base.hubps[i] != NULL) {
1427             kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1428             pool->base.hubps[i] = NULL;
1429         }
1430 
1431         if (pool->base.irqs != NULL) {
1432             dal_irq_service_destroy(&pool->base.irqs);
1433         }
1434     }
1435 
1436     for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1437         if (pool->base.engines[i] != NULL)
1438             dce110_engine_destroy(&pool->base.engines[i]);
1439         if (pool->base.hw_i2cs[i] != NULL) {
1440             kfree(pool->base.hw_i2cs[i]);
1441             pool->base.hw_i2cs[i] = NULL;
1442         }
1443         if (pool->base.sw_i2cs[i] != NULL) {
1444             kfree(pool->base.sw_i2cs[i]);
1445             pool->base.sw_i2cs[i] = NULL;
1446         }
1447     }
1448 
1449     for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1450         if (pool->base.opps[i] != NULL)
1451             pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1452     }
1453 
1454     for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1455         if (pool->base.timing_generators[i] != NULL)    {
1456             kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1457             pool->base.timing_generators[i] = NULL;
1458         }
1459     }
1460 
1461     for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1462         if (pool->base.dwbc[i] != NULL) {
1463             kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1464             pool->base.dwbc[i] = NULL;
1465         }
1466         if (pool->base.mcif_wb[i] != NULL) {
1467             kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1468             pool->base.mcif_wb[i] = NULL;
1469         }
1470     }
1471 
1472     for (i = 0; i < pool->base.audio_count; i++) {
1473         if (pool->base.audios[i])
1474             dce_aud_destroy(&pool->base.audios[i]);
1475     }
1476 
1477     for (i = 0; i < pool->base.clk_src_count; i++) {
1478         if (pool->base.clock_sources[i] != NULL) {
1479             dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1480             pool->base.clock_sources[i] = NULL;
1481         }
1482     }
1483 
1484     for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1485         if (pool->base.mpc_lut[i] != NULL) {
1486             dc_3dlut_func_release(pool->base.mpc_lut[i]);
1487             pool->base.mpc_lut[i] = NULL;
1488         }
1489         if (pool->base.mpc_shaper[i] != NULL) {
1490             dc_transfer_func_release(pool->base.mpc_shaper[i]);
1491             pool->base.mpc_shaper[i] = NULL;
1492         }
1493     }
1494 
1495     if (pool->base.dp_clock_source != NULL) {
1496         dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1497         pool->base.dp_clock_source = NULL;
1498     }
1499 
1500     for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1501         if (pool->base.multiple_abms[i] != NULL)
1502             dce_abm_destroy(&pool->base.multiple_abms[i]);
1503     }
1504 
1505     if (pool->base.psr != NULL)
1506         dmub_psr_destroy(&pool->base.psr);
1507 
1508     if (pool->base.dccg != NULL)
1509         dcn_dccg_destroy(&pool->base.dccg);
1510 }
1511 
1512 static struct hubp *dcn31_hubp_create(
1513     struct dc_context *ctx,
1514     uint32_t inst)
1515 {
1516     struct dcn20_hubp *hubp2 =
1517         kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1518 
1519     if (!hubp2)
1520         return NULL;
1521 
1522     if (hubp31_construct(hubp2, ctx, inst,
1523             &hubp_regs[inst], &hubp_shift, &hubp_mask))
1524         return &hubp2->base;
1525 
1526     BREAK_TO_DEBUGGER();
1527     kfree(hubp2);
1528     return NULL;
1529 }
1530 
1531 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1532 {
1533     int i;
1534     uint32_t pipe_count = pool->res_cap->num_dwb;
1535 
1536     for (i = 0; i < pipe_count; i++) {
1537         struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1538                             GFP_KERNEL);
1539 
1540         if (!dwbc30) {
1541             dm_error("DC: failed to create dwbc30!\n");
1542             return false;
1543         }
1544 
1545         dcn30_dwbc_construct(dwbc30, ctx,
1546                 &dwbc30_regs[i],
1547                 &dwbc30_shift,
1548                 &dwbc30_mask,
1549                 i);
1550 
1551         pool->dwbc[i] = &dwbc30->base;
1552     }
1553     return true;
1554 }
1555 
1556 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1557 {
1558     int i;
1559     uint32_t pipe_count = pool->res_cap->num_dwb;
1560 
1561     for (i = 0; i < pipe_count; i++) {
1562         struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1563                             GFP_KERNEL);
1564 
1565         if (!mcif_wb30) {
1566             dm_error("DC: failed to create mcif_wb30!\n");
1567             return false;
1568         }
1569 
1570         dcn30_mmhubbub_construct(mcif_wb30, ctx,
1571                 &mcif_wb30_regs[i],
1572                 &mcif_wb30_shift,
1573                 &mcif_wb30_mask,
1574                 i);
1575 
1576         pool->mcif_wb[i] = &mcif_wb30->base;
1577     }
1578     return true;
1579 }
1580 
1581 static struct display_stream_compressor *dcn31_dsc_create(
1582     struct dc_context *ctx, uint32_t inst)
1583 {
1584     struct dcn20_dsc *dsc =
1585         kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1586 
1587     if (!dsc) {
1588         BREAK_TO_DEBUGGER();
1589         return NULL;
1590     }
1591 
1592     dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1593     return &dsc->base;
1594 }
1595 
1596 static void dcn31_destroy_resource_pool(struct resource_pool **pool)
1597 {
1598     struct dcn31_resource_pool *dcn31_pool = TO_DCN31_RES_POOL(*pool);
1599 
1600     dcn31_resource_destruct(dcn31_pool);
1601     kfree(dcn31_pool);
1602     *pool = NULL;
1603 }
1604 
1605 static struct clock_source *dcn31_clock_source_create(
1606         struct dc_context *ctx,
1607         struct dc_bios *bios,
1608         enum clock_source_id id,
1609         const struct dce110_clk_src_regs *regs,
1610         bool dp_clk_src)
1611 {
1612     struct dce110_clk_src *clk_src =
1613         kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1614 
1615     if (!clk_src)
1616         return NULL;
1617 
1618     if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
1619             regs, &cs_shift, &cs_mask)) {
1620         clk_src->base.dp_clk_src = dp_clk_src;
1621         return &clk_src->base;
1622     }
1623 
1624     BREAK_TO_DEBUGGER();
1625     return NULL;
1626 }
1627 
1628 static bool is_dual_plane(enum surface_pixel_format format)
1629 {
1630     return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
1631 }
1632 
1633 int dcn31_populate_dml_pipes_from_context(
1634     struct dc *dc, struct dc_state *context,
1635     display_e2e_pipe_params_st *pipes,
1636     bool fast_validate)
1637 {
1638     int i, pipe_cnt;
1639     struct resource_context *res_ctx = &context->res_ctx;
1640     struct pipe_ctx *pipe;
1641     bool upscaled = false;
1642 
1643     DC_FP_START();
1644     dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1645     DC_FP_END();
1646 
1647     for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1648         struct dc_crtc_timing *timing;
1649 
1650         if (!res_ctx->pipe_ctx[i].stream)
1651             continue;
1652         pipe = &res_ctx->pipe_ctx[i];
1653         timing = &pipe->stream->timing;
1654         if (pipe->plane_state &&
1655                 (pipe->plane_state->src_rect.height < pipe->plane_state->dst_rect.height ||
1656                 pipe->plane_state->src_rect.width < pipe->plane_state->dst_rect.width))
1657             upscaled = true;
1658 
1659         /*
1660          * Immediate flip can be set dynamically after enabling the plane.
1661          * We need to require support for immediate flip or underflow can be
1662          * intermittently experienced depending on peak b/w requirements.
1663          */
1664         pipes[pipe_cnt].pipe.src.immediate_flip = true;
1665         pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
1666         pipes[pipe_cnt].pipe.src.gpuvm = true;
1667         pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
1668         pipes[pipe_cnt].pipe.src.dcc_rate = 3;
1669         pipes[pipe_cnt].dout.dsc_input_bpc = 0;
1670         DC_FP_START();
1671         dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt);
1672         DC_FP_END();
1673 
1674         if (dc->debug.dml_hostvm_override == DML_HOSTVM_NO_OVERRIDE)
1675             pipes[pipe_cnt].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active;
1676         else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_FALSE)
1677             pipes[pipe_cnt].pipe.src.hostvm = false;
1678         else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_TRUE)
1679             pipes[pipe_cnt].pipe.src.hostvm = true;
1680 
1681         if (pipes[pipe_cnt].dout.dsc_enable) {
1682             switch (timing->display_color_depth) {
1683             case COLOR_DEPTH_888:
1684                 pipes[pipe_cnt].dout.dsc_input_bpc = 8;
1685                 break;
1686             case COLOR_DEPTH_101010:
1687                 pipes[pipe_cnt].dout.dsc_input_bpc = 10;
1688                 break;
1689             case COLOR_DEPTH_121212:
1690                 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
1691                 break;
1692             default:
1693                 ASSERT(0);
1694                 break;
1695             }
1696         }
1697 
1698         pipe_cnt++;
1699     }
1700     context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE;
1701     dc->config.enable_4to1MPC = false;
1702     if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {
1703         if (is_dual_plane(pipe->plane_state->format)
1704                 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {
1705             dc->config.enable_4to1MPC = true;
1706         } else if (!is_dual_plane(pipe->plane_state->format) && pipe->plane_state->src_rect.width <= 5120) {
1707             /* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */
1708             context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
1709             pipes[0].pipe.src.unbounded_req_mode = true;
1710         }
1711     } else if (context->stream_count >= dc->debug.crb_alloc_policy_min_disp_count
1712             && dc->debug.crb_alloc_policy > DET_SIZE_DEFAULT) {
1713         context->bw_ctx.dml.ip.det_buffer_size_kbytes = dc->debug.crb_alloc_policy * 64;
1714     } else if (context->stream_count >= 3 && upscaled) {
1715         context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
1716     }
1717 
1718     return pipe_cnt;
1719 }
1720 
1721 void dcn31_calculate_wm_and_dlg(
1722         struct dc *dc, struct dc_state *context,
1723         display_e2e_pipe_params_st *pipes,
1724         int pipe_cnt,
1725         int vlevel)
1726 {
1727     DC_FP_START();
1728     dcn31_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);
1729     DC_FP_END();
1730 }
1731 
1732 void
1733 dcn31_populate_dml_writeback_from_context(struct dc *dc,
1734                       struct resource_context *res_ctx,
1735                       display_e2e_pipe_params_st *pipes)
1736 {
1737     DC_FP_START();
1738     dcn30_populate_dml_writeback_from_context(dc, res_ctx, pipes);
1739     DC_FP_END();
1740 }
1741 
1742 void
1743 dcn31_set_mcif_arb_params(struct dc *dc,
1744               struct dc_state *context,
1745               display_e2e_pipe_params_st *pipes,
1746               int pipe_cnt)
1747 {
1748     DC_FP_START();
1749     dcn30_set_mcif_arb_params(dc, context, pipes, pipe_cnt);
1750     DC_FP_END();
1751 }
1752 
1753 bool dcn31_validate_bandwidth(struct dc *dc,
1754         struct dc_state *context,
1755         bool fast_validate)
1756 {
1757     bool out = false;
1758 
1759     BW_VAL_TRACE_SETUP();
1760 
1761     int vlevel = 0;
1762     int pipe_cnt = 0;
1763     display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
1764     DC_LOGGER_INIT(dc->ctx->logger);
1765 
1766     BW_VAL_TRACE_COUNT();
1767 
1768     DC_FP_START();
1769     out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate);
1770     DC_FP_END();
1771 
1772     // Disable fast_validate to set min dcfclk in alculate_wm_and_dlg
1773     if (pipe_cnt == 0)
1774         fast_validate = false;
1775 
1776     if (!out)
1777         goto validate_fail;
1778 
1779     BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1780 
1781     if (fast_validate) {
1782         BW_VAL_TRACE_SKIP(fast);
1783         goto validate_out;
1784     }
1785 
1786     dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
1787 
1788     BW_VAL_TRACE_END_WATERMARKS();
1789 
1790     goto validate_out;
1791 
1792 validate_fail:
1793     DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1794         dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1795 
1796     BW_VAL_TRACE_SKIP(fail);
1797     out = false;
1798 
1799 validate_out:
1800     kfree(pipes);
1801 
1802     BW_VAL_TRACE_FINISH();
1803 
1804     return out;
1805 }
1806 
1807 static struct dc_cap_funcs cap_funcs = {
1808     .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1809 };
1810 
1811 static struct resource_funcs dcn31_res_pool_funcs = {
1812     .destroy = dcn31_destroy_resource_pool,
1813     .link_enc_create = dcn31_link_encoder_create,
1814     .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1815     .link_encs_assign = link_enc_cfg_link_encs_assign,
1816     .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1817     .panel_cntl_create = dcn31_panel_cntl_create,
1818     .validate_bandwidth = dcn31_validate_bandwidth,
1819     .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
1820     .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1821     .populate_dml_pipes = dcn31_populate_dml_pipes_from_context,
1822     .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1823     .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1824     .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1825     .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1826     .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context,
1827     .set_mcif_arb_params = dcn31_set_mcif_arb_params,
1828     .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1829     .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1830     .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1831     .update_bw_bounding_box = dcn31_update_bw_bounding_box,
1832     .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1833 };
1834 
1835 static struct clock_source *dcn30_clock_source_create(
1836         struct dc_context *ctx,
1837         struct dc_bios *bios,
1838         enum clock_source_id id,
1839         const struct dce110_clk_src_regs *regs,
1840         bool dp_clk_src)
1841 {
1842     struct dce110_clk_src *clk_src =
1843         kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1844 
1845     if (!clk_src)
1846         return NULL;
1847 
1848     if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1849             regs, &cs_shift, &cs_mask)) {
1850         clk_src->base.dp_clk_src = dp_clk_src;
1851         return &clk_src->base;
1852     }
1853 
1854     BREAK_TO_DEBUGGER();
1855     return NULL;
1856 }
1857 
1858 static bool dcn31_resource_construct(
1859     uint8_t num_virtual_links,
1860     struct dc *dc,
1861     struct dcn31_resource_pool *pool)
1862 {
1863     int i;
1864     struct dc_context *ctx = dc->ctx;
1865     struct irq_service_init_data init_data;
1866 
1867     ctx->dc_bios->regs = &bios_regs;
1868 
1869     pool->base.res_cap = &res_cap_dcn31;
1870 
1871     pool->base.funcs = &dcn31_res_pool_funcs;
1872 
1873     /*************************************************
1874      *  Resource + asic cap harcoding                *
1875      *************************************************/
1876     pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1877     pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1878     pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1879     dc->caps.max_downscale_ratio = 600;
1880     dc->caps.i2c_speed_in_khz = 100;
1881     dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/
1882     dc->caps.max_cursor_size = 256;
1883     dc->caps.min_horizontal_blanking_period = 80;
1884     dc->caps.dmdata_alloc_size = 2048;
1885 
1886     dc->caps.max_slave_planes = 2;
1887     dc->caps.max_slave_yuv_planes = 2;
1888     dc->caps.max_slave_rgb_planes = 2;
1889     dc->caps.post_blend_color_processing = true;
1890     dc->caps.force_dp_tps4_for_cp2520 = true;
1891     dc->caps.dp_hpo = true;
1892     dc->caps.dp_hdmi21_pcon_support = true;
1893     dc->caps.edp_dsc_support = true;
1894     dc->caps.extended_aux_timeout_support = true;
1895     dc->caps.dmcub_support = true;
1896     dc->caps.is_apu = true;
1897     dc->caps.zstate_support = true;
1898 
1899     /* Color pipeline capabilities */
1900     dc->caps.color.dpp.dcn_arch = 1;
1901     dc->caps.color.dpp.input_lut_shared = 0;
1902     dc->caps.color.dpp.icsc = 1;
1903     dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1904     dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1905     dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1906     dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1907     dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1908     dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1909     dc->caps.color.dpp.post_csc = 1;
1910     dc->caps.color.dpp.gamma_corr = 1;
1911     dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1912 
1913     dc->caps.color.dpp.hw_3d_lut = 1;
1914     dc->caps.color.dpp.ogam_ram = 1;
1915     // no OGAM ROM on DCN301
1916     dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1917     dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1918     dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1919     dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1920     dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1921     dc->caps.color.dpp.ocsc = 0;
1922 
1923     dc->caps.color.mpc.gamut_remap = 1;
1924     dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1925     dc->caps.color.mpc.ogam_ram = 1;
1926     dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1927     dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1928     dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1929     dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1930     dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1931     dc->caps.color.mpc.ocsc = 1;
1932 
1933     /* Use pipe context based otg sync logic */
1934     dc->config.use_pipe_ctx_sync_logic = true;
1935 
1936     /* read VBIOS LTTPR caps */
1937     {
1938         if (ctx->dc_bios->funcs->get_lttpr_caps) {
1939             enum bp_result bp_query_result;
1940             uint8_t is_vbios_lttpr_enable = 0;
1941 
1942             bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1943             dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1944         }
1945 
1946         /* interop bit is implicit */
1947         {
1948             dc->caps.vbios_lttpr_aware = true;
1949         }
1950     }
1951 
1952     if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1953         dc->debug = debug_defaults_drv;
1954     else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
1955         dc->debug = debug_defaults_diags;
1956     } else
1957         dc->debug = debug_defaults_diags;
1958     // Init the vm_helper
1959     if (dc->vm_helper)
1960         vm_helper_init(dc->vm_helper, 16);
1961 
1962     /*************************************************
1963      *  Create resources                             *
1964      *************************************************/
1965 
1966     /* Clock Sources for Pixel Clock*/
1967     pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =
1968             dcn30_clock_source_create(ctx, ctx->dc_bios,
1969                 CLOCK_SOURCE_COMBO_PHY_PLL0,
1970                 &clk_src_regs[0], false);
1971     pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =
1972             dcn30_clock_source_create(ctx, ctx->dc_bios,
1973                 CLOCK_SOURCE_COMBO_PHY_PLL1,
1974                 &clk_src_regs[1], false);
1975     /*move phypllx_pixclk_resync to dmub next*/
1976     if (dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
1977         pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
1978             dcn30_clock_source_create(ctx, ctx->dc_bios,
1979                 CLOCK_SOURCE_COMBO_PHY_PLL2,
1980                 &clk_src_regs_b0[2], false);
1981         pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
1982             dcn30_clock_source_create(ctx, ctx->dc_bios,
1983                 CLOCK_SOURCE_COMBO_PHY_PLL3,
1984                 &clk_src_regs_b0[3], false);
1985     } else {
1986         pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
1987             dcn30_clock_source_create(ctx, ctx->dc_bios,
1988                 CLOCK_SOURCE_COMBO_PHY_PLL2,
1989                 &clk_src_regs[2], false);
1990         pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
1991             dcn30_clock_source_create(ctx, ctx->dc_bios,
1992                 CLOCK_SOURCE_COMBO_PHY_PLL3,
1993                 &clk_src_regs[3], false);
1994     }
1995 
1996     pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
1997             dcn30_clock_source_create(ctx, ctx->dc_bios,
1998                 CLOCK_SOURCE_COMBO_PHY_PLL4,
1999                 &clk_src_regs[4], false);
2000 
2001     pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
2002 
2003     /* todo: not reuse phy_pll registers */
2004     pool->base.dp_clock_source =
2005             dcn31_clock_source_create(ctx, ctx->dc_bios,
2006                 CLOCK_SOURCE_ID_DP_DTO,
2007                 &clk_src_regs[0], true);
2008 
2009     for (i = 0; i < pool->base.clk_src_count; i++) {
2010         if (pool->base.clock_sources[i] == NULL) {
2011             dm_error("DC: failed to create clock sources!\n");
2012             BREAK_TO_DEBUGGER();
2013             goto create_fail;
2014         }
2015     }
2016 
2017     /* TODO: DCCG */
2018     pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2019     if (pool->base.dccg == NULL) {
2020         dm_error("DC: failed to create dccg!\n");
2021         BREAK_TO_DEBUGGER();
2022         goto create_fail;
2023     }
2024 
2025     /* TODO: IRQ */
2026     init_data.ctx = dc->ctx;
2027     pool->base.irqs = dal_irq_service_dcn31_create(&init_data);
2028     if (!pool->base.irqs)
2029         goto create_fail;
2030 
2031     /* HUBBUB */
2032     pool->base.hubbub = dcn31_hubbub_create(ctx);
2033     if (pool->base.hubbub == NULL) {
2034         BREAK_TO_DEBUGGER();
2035         dm_error("DC: failed to create hubbub!\n");
2036         goto create_fail;
2037     }
2038 
2039     /* HUBPs, DPPs, OPPs and TGs */
2040     for (i = 0; i < pool->base.pipe_count; i++) {
2041         pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
2042         if (pool->base.hubps[i] == NULL) {
2043             BREAK_TO_DEBUGGER();
2044             dm_error(
2045                 "DC: failed to create hubps!\n");
2046             goto create_fail;
2047         }
2048 
2049         pool->base.dpps[i] = dcn31_dpp_create(ctx, i);
2050         if (pool->base.dpps[i] == NULL) {
2051             BREAK_TO_DEBUGGER();
2052             dm_error(
2053                 "DC: failed to create dpps!\n");
2054             goto create_fail;
2055         }
2056     }
2057 
2058     for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2059         pool->base.opps[i] = dcn31_opp_create(ctx, i);
2060         if (pool->base.opps[i] == NULL) {
2061             BREAK_TO_DEBUGGER();
2062             dm_error(
2063                 "DC: failed to create output pixel processor!\n");
2064             goto create_fail;
2065         }
2066     }
2067 
2068     for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2069         pool->base.timing_generators[i] = dcn31_timing_generator_create(
2070                 ctx, i);
2071         if (pool->base.timing_generators[i] == NULL) {
2072             BREAK_TO_DEBUGGER();
2073             dm_error("DC: failed to create tg!\n");
2074             goto create_fail;
2075         }
2076     }
2077     pool->base.timing_generator_count = i;
2078 
2079     /* PSR */
2080     pool->base.psr = dmub_psr_create(ctx);
2081     if (pool->base.psr == NULL) {
2082         dm_error("DC: failed to create psr obj!\n");
2083         BREAK_TO_DEBUGGER();
2084         goto create_fail;
2085     }
2086 
2087     /* ABM */
2088     for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2089         pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2090                 &abm_regs[i],
2091                 &abm_shift,
2092                 &abm_mask);
2093         if (pool->base.multiple_abms[i] == NULL) {
2094             dm_error("DC: failed to create abm for pipe %d!\n", i);
2095             BREAK_TO_DEBUGGER();
2096             goto create_fail;
2097         }
2098     }
2099 
2100     /* MPC and DSC */
2101     pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2102     if (pool->base.mpc == NULL) {
2103         BREAK_TO_DEBUGGER();
2104         dm_error("DC: failed to create mpc!\n");
2105         goto create_fail;
2106     }
2107 
2108     for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2109         pool->base.dscs[i] = dcn31_dsc_create(ctx, i);
2110         if (pool->base.dscs[i] == NULL) {
2111             BREAK_TO_DEBUGGER();
2112             dm_error("DC: failed to create display stream compressor %d!\n", i);
2113             goto create_fail;
2114         }
2115     }
2116 
2117     /* DWB and MMHUBBUB */
2118     if (!dcn31_dwbc_create(ctx, &pool->base)) {
2119         BREAK_TO_DEBUGGER();
2120         dm_error("DC: failed to create dwbc!\n");
2121         goto create_fail;
2122     }
2123 
2124     if (!dcn31_mmhubbub_create(ctx, &pool->base)) {
2125         BREAK_TO_DEBUGGER();
2126         dm_error("DC: failed to create mcif_wb!\n");
2127         goto create_fail;
2128     }
2129 
2130     /* AUX and I2C */
2131     for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2132         pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2133         if (pool->base.engines[i] == NULL) {
2134             BREAK_TO_DEBUGGER();
2135             dm_error(
2136                 "DC:failed to create aux engine!!\n");
2137             goto create_fail;
2138         }
2139         pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2140         if (pool->base.hw_i2cs[i] == NULL) {
2141             BREAK_TO_DEBUGGER();
2142             dm_error(
2143                 "DC:failed to create hw i2c!!\n");
2144             goto create_fail;
2145         }
2146         pool->base.sw_i2cs[i] = NULL;
2147     }
2148 
2149     if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&
2150         dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&
2151         !dc->debug.dpia_debug.bits.disable_dpia) {
2152         /* YELLOW CARP B0 has 4 DPIA's */
2153         pool->base.usb4_dpia_count = 4;
2154     }
2155 
2156     if (dc->ctx->asic_id.chip_family == AMDGPU_FAMILY_GC_11_0_1)
2157         pool->base.usb4_dpia_count = 4;
2158 
2159     /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2160     if (!resource_construct(num_virtual_links, dc, &pool->base,
2161             (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2162             &res_create_funcs : &res_create_maximus_funcs)))
2163             goto create_fail;
2164 
2165     /* HW Sequencer and Plane caps */
2166     dcn31_hw_sequencer_construct(dc);
2167 
2168     dc->caps.max_planes =  pool->base.pipe_count;
2169 
2170     for (i = 0; i < dc->caps.max_planes; ++i)
2171         dc->caps.planes[i] = plane_cap;
2172 
2173     dc->cap_funcs = cap_funcs;
2174 
2175     dc->dcn_ip->max_num_dpp = dcn3_1_ip.max_num_dpp;
2176 
2177     return true;
2178 
2179 create_fail:
2180     dcn31_resource_destruct(pool);
2181 
2182     return false;
2183 }
2184 
2185 struct resource_pool *dcn31_create_resource_pool(
2186         const struct dc_init_data *init_data,
2187         struct dc *dc)
2188 {
2189     struct dcn31_resource_pool *pool =
2190         kzalloc(sizeof(struct dcn31_resource_pool), GFP_KERNEL);
2191 
2192     if (!pool)
2193         return NULL;
2194 
2195     if (dcn31_resource_construct(init_data->num_virtual_links, dc, pool))
2196         return &pool->base;
2197 
2198     BREAK_TO_DEBUGGER();
2199     kfree(pool);
2200     return NULL;
2201 }
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