dc/dcn31/dcn31_optc.c

0001 /*
0002  * Copyright 2012-15 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include "dcn31_optc.h"
0027
0028 #include "dcn30/dcn30_optc.h"
0029 #include "reg_helper.h"
0030 #include "dc.h"
0031 #include "dcn_calc_math.h"
0032
0033 #define REG(reg)\
0034     optc1->tg_regs->reg
0035
0036 #define CTX \
0037     optc1->base.ctx
0038
0039 #undef FN
0040 #define FN(reg_name, field_name) \
0041     optc1->tg_shift->field_name, optc1->tg_mask->field_name
0042
0043 static void optc31_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
0044         struct dc_crtc_timing *timing)
0045 {
0046     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0047     int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right)
0048             / opp_cnt;
0049     uint32_t memory_mask = 0;
0050     int mem_count_per_opp = (mpcc_hactive + 2559) / 2560;
0051
0052     /* Assume less than 6 pipes */
0053     if (opp_cnt == 4) {
0054         if (mem_count_per_opp == 1)
0055             memory_mask = 0xf;
0056         else {
0057             ASSERT(mem_count_per_opp == 2);
0058             memory_mask = 0xff;
0059         }
0060     } else if (mem_count_per_opp == 1)
0061         memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2);
0062     else if (mem_count_per_opp == 2)
0063         memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
0064     else if (mem_count_per_opp == 3)
0065         memory_mask = 0x77;
0066     else if (mem_count_per_opp == 4)
0067         memory_mask = 0xff;
0068
0069     if (REG(OPTC_MEMORY_CONFIG))
0070         REG_SET(OPTC_MEMORY_CONFIG, 0,
0071             OPTC_MEM_SEL, memory_mask);
0072
0073     if (opp_cnt == 2) {
0074         REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
0075                 OPTC_NUM_OF_INPUT_SEGMENT, 1,
0076                 OPTC_SEG0_SRC_SEL, opp_id[0],
0077                 OPTC_SEG1_SRC_SEL, opp_id[1]);
0078     } else if (opp_cnt == 4) {
0079         REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
0080                 OPTC_NUM_OF_INPUT_SEGMENT, 3,
0081                 OPTC_SEG0_SRC_SEL, opp_id[0],
0082                 OPTC_SEG1_SRC_SEL, opp_id[1],
0083                 OPTC_SEG2_SRC_SEL, opp_id[2],
0084                 OPTC_SEG3_SRC_SEL, opp_id[3]);
0085     }
0086
0087     REG_UPDATE(OPTC_WIDTH_CONTROL,
0088             OPTC_SEGMENT_WIDTH, mpcc_hactive);
0089
0090     REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
0091     optc1->opp_count = opp_cnt;
0092 }
0093
0094 /*
0095  * Enable CRTC - call ASIC Control Object to enable Timing generator.
0096  */
0097 static bool optc31_enable_crtc(struct timing_generator *optc)
0098 {
0099     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0100
0101     /* opp instance for OTG, 1 to 1 mapping and odm will adjust */
0102     REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
0103             OPTC_SEG0_SRC_SEL, optc->inst);
0104
0105     /* VTG enable first is for HW workaround */
0106     REG_UPDATE(CONTROL,
0107             VTG0_ENABLE, 1);
0108
0109     REG_SEQ_START();
0110
0111     /* Enable CRTC */
0112     REG_UPDATE_2(OTG_CONTROL,
0113             OTG_DISABLE_POINT_CNTL, 2,
0114             OTG_MASTER_EN, 1);
0115
0116     REG_SEQ_SUBMIT();
0117     REG_SEQ_WAIT_DONE();
0118
0119     return true;
0120 }
0121
0122 /* disable_crtc - call ASIC Control Object to disable Timing generator. */
0123 static bool optc31_disable_crtc(struct timing_generator *optc)
0124 {
0125     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0126     /* disable otg request until end of the first line
0127      * in the vertical blank region
0128      */
0129     REG_UPDATE(OTG_CONTROL,
0130             OTG_MASTER_EN, 0);
0131
0132     REG_UPDATE(CONTROL,
0133             VTG0_ENABLE, 0);
0134
0135     /* CRTC disabled, so disable  clock. */
0136     REG_WAIT(OTG_CLOCK_CONTROL,
0137             OTG_BUSY, 0,
0138             1, 100000);
0139     optc1_clear_optc_underflow(optc);
0140
0141     return true;
0142 }
0143
0144 bool optc31_immediate_disable_crtc(struct timing_generator *optc)
0145 {
0146     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0147
0148     REG_UPDATE_2(OTG_CONTROL,
0149             OTG_DISABLE_POINT_CNTL, 0,
0150             OTG_MASTER_EN, 0);
0151
0152     REG_UPDATE(CONTROL,
0153             VTG0_ENABLE, 0);
0154
0155     /* CRTC disabled, so disable  clock. */
0156     REG_WAIT(OTG_CLOCK_CONTROL,
0157             OTG_BUSY, 0,
0158             1, 100000);
0159
0160     /* clear the false state */
0161     optc1_clear_optc_underflow(optc);
0162
0163     return true;
0164 }
0165
0166 void optc31_set_drr(
0167     struct timing_generator *optc,
0168     const struct drr_params *params)
0169 {
0170     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0171
0172     if (params != NULL &&
0173         params->vertical_total_max > 0 &&
0174         params->vertical_total_min > 0) {
0175
0176         if (params->vertical_total_mid != 0) {
0177
0178             REG_SET(OTG_V_TOTAL_MID, 0,
0179                 OTG_V_TOTAL_MID, params->vertical_total_mid - 1);
0180
0181             REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
0182                     OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
0183                     OTG_VTOTAL_MID_FRAME_NUM,
0184                     (uint8_t)params->vertical_total_mid_frame_num);
0185
0186         }
0187
0188         optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);
0189
0190         /*
0191          * MIN_MASK_EN is gone and MASK is now always enabled.
0192          *
0193          * To get it to it work with manual trigger we need to make sure
0194          * we program the correct bit.
0195          */
0196         REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
0197                 OTG_V_TOTAL_MIN_SEL, 1,
0198                 OTG_V_TOTAL_MAX_SEL, 1,
0199                 OTG_FORCE_LOCK_ON_EVENT, 0,
0200                 OTG_SET_V_TOTAL_MIN_MASK, (1 << 1)); /* TRIGA */
0201
0202         // Setup manual flow control for EOF via TRIG_A
0203         optc->funcs->setup_manual_trigger(optc);
0204
0205     } else {
0206         REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
0207                 OTG_SET_V_TOTAL_MIN_MASK, 0,
0208                 OTG_V_TOTAL_MIN_SEL, 0,
0209                 OTG_V_TOTAL_MAX_SEL, 0,
0210                 OTG_FORCE_LOCK_ON_EVENT, 0);
0211
0212         optc->funcs->set_vtotal_min_max(optc, 0, 0);
0213     }
0214 }
0215
0216 void optc3_init_odm(struct timing_generator *optc)
0217 {
0218     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0219
0220     REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
0221             OPTC_NUM_OF_INPUT_SEGMENT, 0,
0222             OPTC_SEG0_SRC_SEL, optc->inst,
0223             OPTC_SEG1_SRC_SEL, 0xf,
0224             OPTC_SEG2_SRC_SEL, 0xf,
0225             OPTC_SEG3_SRC_SEL, 0xf
0226             );
0227
0228     REG_SET(OTG_H_TIMING_CNTL, 0,
0229             OTG_H_TIMING_DIV_MODE, 0);
0230
0231     REG_SET(OPTC_MEMORY_CONFIG, 0,
0232             OPTC_MEM_SEL, 0);
0233     optc1->opp_count = 1;
0234 }
0235
0236 static struct timing_generator_funcs dcn31_tg_funcs = {
0237         .validate_timing = optc1_validate_timing,
0238         .program_timing = optc1_program_timing,
0239         .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
0240         .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
0241         .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
0242         .program_global_sync = optc1_program_global_sync,
0243         .enable_crtc = optc31_enable_crtc,
0244         .disable_crtc = optc31_disable_crtc,
0245         .immediate_disable_crtc = optc31_immediate_disable_crtc,
0246         /* used by enable_timing_synchronization. Not need for FPGA */
0247         .is_counter_moving = optc1_is_counter_moving,
0248         .get_position = optc1_get_position,
0249         .get_frame_count = optc1_get_vblank_counter,
0250         .get_scanoutpos = optc1_get_crtc_scanoutpos,
0251         .get_otg_active_size = optc1_get_otg_active_size,
0252         .set_early_control = optc1_set_early_control,
0253         /* used by enable_timing_synchronization. Not need for FPGA */
0254         .wait_for_state = optc1_wait_for_state,
0255         .set_blank_color = optc3_program_blank_color,
0256         .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
0257         .triplebuffer_lock = optc3_triplebuffer_lock,
0258         .triplebuffer_unlock = optc2_triplebuffer_unlock,
0259         .enable_reset_trigger = optc1_enable_reset_trigger,
0260         .enable_crtc_reset = optc1_enable_crtc_reset,
0261         .disable_reset_trigger = optc1_disable_reset_trigger,
0262         .lock = optc3_lock,
0263         .is_locked = optc1_is_locked,
0264         .unlock = optc1_unlock,
0265         .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
0266         .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
0267         .enable_optc_clock = optc1_enable_optc_clock,
0268         .set_drr = optc31_set_drr,
0269         .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
0270         .set_vtotal_min_max = optc1_set_vtotal_min_max,
0271         .set_static_screen_control = optc1_set_static_screen_control,
0272         .program_stereo = optc1_program_stereo,
0273         .is_stereo_left_eye = optc1_is_stereo_left_eye,
0274         .tg_init = optc3_tg_init,
0275         .is_tg_enabled = optc1_is_tg_enabled,
0276         .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
0277         .clear_optc_underflow = optc1_clear_optc_underflow,
0278         .setup_global_swap_lock = NULL,
0279         .get_crc = optc1_get_crc,
0280         .configure_crc = optc2_configure_crc,
0281         .set_dsc_config = optc3_set_dsc_config,
0282         .get_dsc_status = optc2_get_dsc_status,
0283         .set_dwb_source = NULL,
0284         .set_odm_bypass = optc3_set_odm_bypass,
0285         .set_odm_combine = optc31_set_odm_combine,
0286         .get_optc_source = optc2_get_optc_source,
0287         .set_out_mux = optc3_set_out_mux,
0288         .set_drr_trigger_window = optc3_set_drr_trigger_window,
0289         .set_vtotal_change_limit = optc3_set_vtotal_change_limit,
0290         .set_gsl = optc2_set_gsl,
0291         .set_gsl_source_select = optc2_set_gsl_source_select,
0292         .set_vtg_params = optc1_set_vtg_params,
0293         .program_manual_trigger = optc2_program_manual_trigger,
0294         .setup_manual_trigger = optc2_setup_manual_trigger,
0295         .get_hw_timing = optc1_get_hw_timing,
0296         .init_odm = optc3_init_odm,
0297 };
0298
0299 void dcn31_timing_generator_init(struct optc *optc1)
0300 {
0301     optc1->base.funcs = &dcn31_tg_funcs;
0302
0303     optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
0304     optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
0305
0306     optc1->min_h_blank = 32;
0307     optc1->min_v_blank = 3;
0308     optc1->min_v_blank_interlace = 5;
0309     optc1->min_h_sync_width = 4;
0310     optc1->min_v_sync_width = 1;
0311 }
0312