dc/dcn31/dcn31_dio_link_encoder.h

0001 /*
0002  * Copyright 2012-15 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  *  and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef __DC_LINK_ENCODER__DCN31_H__
0027 #define __DC_LINK_ENCODER__DCN31_H__
0028
0029 #include "dcn30/dcn30_dio_link_encoder.h"
0030
0031
0032 #define LE_DCN31_REG_LIST(id)\
0033     LE_DCN3_REG_LIST(id),\
0034     SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
0035     SR(DIO_LINKA_CNTL), \
0036     SR(DIO_LINKB_CNTL), \
0037     SR(DIO_LINKC_CNTL), \
0038     SR(DIO_LINKD_CNTL), \
0039     SR(DIO_LINKE_CNTL), \
0040     SR(DIO_LINKF_CNTL)
0041
0042 #define LINK_ENCODER_MASK_SH_LIST_DCN31(mask_sh) \
0043     LINK_ENCODER_MASK_SH_LIST_DCN10(mask_sh),\
0044     LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_EN, mask_sh),\
0045     LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, mask_sh),\
0046     LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, mask_sh),\
0047     LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
0048     LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_START_WINDOW, mask_sh),\
0049     LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_HALF_SYM_DETECT_LEN, mask_sh),\
0050     LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_TRANSITION_FILTER_EN, mask_sh),\
0051     LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT, mask_sh),\
0052     LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_START, mask_sh),\
0053     LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_STOP, mask_sh),\
0054     LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_PHASE_DETECT_LEN, mask_sh),\
0055     LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_DETECTION_THRESHOLD, mask_sh), \
0056     LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_LEN, mask_sh),\
0057     LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_SYMBOLS, mask_sh),\
0058     LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_MODE_DET_CHECK_DELAY, mask_sh),\
0059     LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_PRECHARGE_SKIP, mask_sh),\
0060     LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, mask_sh),\
0061     LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN_MUL, mask_sh),\
0062     LE_SF(DIO_LINKA_CNTL, ENC_TYPE_SEL, mask_sh),\
0063     LE_SF(DIO_LINKA_CNTL, HPO_DP_ENC_SEL, mask_sh),\
0064     LE_SF(DIO_LINKA_CNTL, HPO_HDMI_ENC_SEL, mask_sh)
0065
0066 #define DPCS_DCN31_REG_LIST(id) \
0067     SRI(TMDS_CTL_BITS, DIG, id), \
0068     SRI(RDPCSTX_PHY_CNTL3, RDPCSTX, id), \
0069     SRI(RDPCSTX_PHY_CNTL4, RDPCSTX, id), \
0070     SRI(RDPCSTX_PHY_CNTL5, RDPCSTX, id), \
0071     SRI(RDPCSTX_PHY_CNTL6, RDPCSTX, id), \
0072     SRI(RDPCSPIPE_PHY_CNTL6, RDPCSPIPE, id), \
0073     SRI(RDPCSTX_PHY_CNTL7, RDPCSTX, id), \
0074     SRI(RDPCSTX_PHY_CNTL8, RDPCSTX, id), \
0075     SRI(RDPCSTX_PHY_CNTL9, RDPCSTX, id), \
0076     SRI(RDPCSTX_PHY_CNTL10, RDPCSTX, id), \
0077     SRI(RDPCSTX_PHY_CNTL11, RDPCSTX, id), \
0078     SRI(RDPCSTX_PHY_CNTL12, RDPCSTX, id), \
0079     SRI(RDPCSTX_PHY_CNTL13, RDPCSTX, id), \
0080     SRI(RDPCSTX_PHY_CNTL14, RDPCSTX, id), \
0081     SRI(RDPCSTX_CNTL, RDPCSTX, id), \
0082     SRI(RDPCSTX_CLOCK_CNTL, RDPCSTX, id), \
0083     SRI(RDPCSTX_INTERRUPT_CONTROL, RDPCSTX, id), \
0084     SRI(RDPCSTX_PHY_CNTL0, RDPCSTX, id), \
0085     SRI(RDPCSTX_PHY_CNTL2, RDPCSTX, id), \
0086     SRI(RDPCS_TX_CR_ADDR, RDPCSTX, id), \
0087     SRI(RDPCS_TX_CR_DATA, RDPCSTX, id), \
0088     SRI(RDPCSTX_PHY_FUSE0, RDPCSTX, id), \
0089     SRI(RDPCSTX_PHY_FUSE1, RDPCSTX, id), \
0090     SRI(RDPCSTX_PHY_FUSE2, RDPCSTX, id), \
0091     SRI(RDPCSTX_PHY_FUSE3, RDPCSTX, id), \
0092     SR(RDPCSTX0_RDPCSTX_SCRATCH), \
0093     SRI(RDPCSTX_PHY_RX_LD_VAL, RDPCSTX, id),\
0094     SRI(RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG, RDPCSTX, id)
0095
0096 #define DPCS_DCN31_MASK_SH_LIST(mask_sh)\
0097     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_CLK_RDY, mask_sh),\
0098     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_DATA_EN, mask_sh),\
0099     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_CLK_RDY, mask_sh),\
0100     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_DATA_EN, mask_sh),\
0101     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_CLK_RDY, mask_sh),\
0102     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_DATA_EN, mask_sh),\
0103     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_CLK_RDY, mask_sh),\
0104     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_DATA_EN, mask_sh),\
0105     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX0_TERM_CTRL, mask_sh),\
0106     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX1_TERM_CTRL, mask_sh),\
0107     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX2_TERM_CTRL, mask_sh),\
0108     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX3_TERM_CTRL, mask_sh),\
0109     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_DP_MPLLB_MULTIPLIER, mask_sh),\
0110     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX0_WIDTH, mask_sh),\
0111     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX0_RATE, mask_sh),\
0112     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX1_WIDTH, mask_sh),\
0113     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX1_RATE, mask_sh),\
0114     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX2_PSTATE, mask_sh),\
0115     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX3_PSTATE, mask_sh),\
0116     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX2_MPLL_EN, mask_sh),\
0117     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX3_MPLL_EN, mask_sh),\
0118     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, mask_sh),\
0119     LE_SF(RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, mask_sh),\
0120     LE_SF(RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, mask_sh),\
0121     LE_SF(RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE_ACK, mask_sh),\
0122     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL7, RDPCS_PHY_DP_MPLLB_FRACN_QUOT, mask_sh),\
0123     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL7, RDPCS_PHY_DP_MPLLB_FRACN_DEN, mask_sh),\
0124     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL8, RDPCS_PHY_DP_MPLLB_SSC_PEAK, mask_sh),\
0125     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL9, RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD, mask_sh),\
0126     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL9, RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE, mask_sh),\
0127     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL10, RDPCS_PHY_DP_MPLLB_FRACN_REM, mask_sh),\
0128     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_DP_REF_CLK_MPLLB_DIV, mask_sh),\
0129     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_HDMI_MPLLB_HDMI_DIV, mask_sh),\
0130     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_SSC_EN, mask_sh),\
0131     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN, mask_sh),\
0132     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_TX_CLK_DIV, mask_sh),\
0133     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN, mask_sh),\
0134     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_STATE, mask_sh),\
0135     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL13, RDPCS_PHY_DP_MPLLB_DIV_CLK_EN, mask_sh),\
0136     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL13, RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER, mask_sh),\
0137     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL14, RDPCS_PHY_DP_MPLLB_FRACN_EN, mask_sh),\
0138     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL14, RDPCS_PHY_DP_MPLLB_PMIX_EN, mask_sh),\
0139     LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE0_EN, mask_sh),\
0140     LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE1_EN, mask_sh),\
0141     LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE2_EN, mask_sh),\
0142     LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE3_EN, mask_sh),\
0143     LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_EN, mask_sh),\
0144     LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_RD_START_DELAY, mask_sh),\
0145     LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_EXT_REFCLK_EN, mask_sh),\
0146     LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_BYPASS, mask_sh),\
0147     LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_EN, mask_sh),\
0148     LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_CLOCK_ON, mask_sh),\
0149     LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_CLOCK_ON, mask_sh),\
0150     LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_GATE_DIS, mask_sh),\
0151     LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_EN, mask_sh),\
0152     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_DISABLE, mask_sh),\
0153     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_DISABLE, mask_sh),\
0154     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_DISABLE, mask_sh),\
0155     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_DISABLE, mask_sh),\
0156     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_REQ, mask_sh),\
0157     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_REQ, mask_sh),\
0158     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_REQ, mask_sh),\
0159     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_REQ, mask_sh),\
0160     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_ACK, mask_sh),\
0161     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_ACK, mask_sh),\
0162     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_ACK, mask_sh),\
0163     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_ACK, mask_sh),\
0164     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_RESET, mask_sh),\
0165     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_RESET, mask_sh),\
0166     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_RESET, mask_sh),\
0167     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_RESET, mask_sh),\
0168     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_RESET, mask_sh),\
0169     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_CR_MUX_SEL, mask_sh),\
0170     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_REF_RANGE, mask_sh),\
0171     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_BYPASS, mask_sh),\
0172     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_EXT_LD_DONE, mask_sh),\
0173     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_HDMIMODE_ENABLE, mask_sh),\
0174     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_INIT_DONE, mask_sh),\
0175     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL2, RDPCS_PHY_DP4_POR, mask_sh),\
0176     LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_REG_FIFO_ERROR_MASK, mask_sh),\
0177     LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_TX_FIFO_ERROR_MASK, mask_sh),\
0178     LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_DPALT_DISABLE_TOGGLE_MASK, mask_sh),\
0179     LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_DPALT_4LANE_TOGGLE_MASK, mask_sh),\
0180     LE_SF(RDPCSTX0_RDPCS_TX_CR_ADDR, RDPCS_TX_CR_ADDR, mask_sh),\
0181     LE_SF(RDPCSTX0_RDPCS_TX_CR_DATA, RDPCS_TX_CR_DATA, mask_sh),\
0182     LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_MPLLB_V2I, mask_sh),\
0183     LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_MAIN, mask_sh),\
0184     LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_PRE, mask_sh),\
0185     LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_POST, mask_sh),\
0186     LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_MPLLB_FREQ_VCO, mask_sh),\
0187     LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_MPLLB_CP_INT, mask_sh),\
0188     LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_MPLLB_CP_PROP, mask_sh),\
0189     LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_MAIN, mask_sh),\
0190     LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_PRE, mask_sh),\
0191     LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_POST, mask_sh),\
0192     LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_MAIN, mask_sh),\
0193     LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_PRE, mask_sh),\
0194     LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_POST, mask_sh),\
0195     LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_MAIN, mask_sh),\
0196     LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DCO_FINETUNE, mask_sh),\
0197     LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DCO_RANGE, mask_sh),\
0198     LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_PRE, mask_sh),\
0199     LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_POST, mask_sh)
0200
0201 #define DPCS_DCN314_REG_LIST(id) \
0202     SRI(TMDS_CTL_BITS, DIG, id), \
0203     SRI(RDPCSTX_PHY_CNTL3, RDPCSTX, id), \
0204     SRI(RDPCSTX_PHY_CNTL4, RDPCSTX, id), \
0205     SRI(RDPCSTX_PHY_CNTL5, RDPCSTX, id), \
0206     SRI(RDPCSTX_PHY_CNTL7, RDPCSTX, id), \
0207     SRI(RDPCSTX_PHY_CNTL8, RDPCSTX, id), \
0208     SRI(RDPCSTX_PHY_CNTL9, RDPCSTX, id), \
0209     SRI(RDPCSTX_PHY_CNTL10, RDPCSTX, id), \
0210     SRI(RDPCSTX_PHY_CNTL11, RDPCSTX, id), \
0211     SRI(RDPCSTX_PHY_CNTL12, RDPCSTX, id), \
0212     SRI(RDPCSTX_PHY_CNTL13, RDPCSTX, id), \
0213     SRI(RDPCSTX_PHY_CNTL14, RDPCSTX, id), \
0214     SRI(RDPCSTX_CNTL, RDPCSTX, id), \
0215     SRI(RDPCSTX_CLOCK_CNTL, RDPCSTX, id), \
0216     SRI(RDPCSTX_INTERRUPT_CONTROL, RDPCSTX, id), \
0217     SRI(RDPCSTX_PHY_CNTL0, RDPCSTX, id), \
0218     SRI(RDPCSTX_PHY_CNTL2, RDPCSTX, id), \
0219     SRI(RDPCS_TX_CR_ADDR, RDPCSTX, id), \
0220     SRI(RDPCS_TX_CR_DATA, RDPCSTX, id), \
0221     SRI(RDPCSTX_PHY_FUSE0, RDPCSTX, id), \
0222     SRI(RDPCSTX_PHY_FUSE1, RDPCSTX, id), \
0223     SRI(RDPCSTX_PHY_FUSE2, RDPCSTX, id), \
0224     SRI(RDPCSTX_PHY_FUSE3, RDPCSTX, id), \
0225     SR(RDPCSTX0_RDPCSTX_SCRATCH), \
0226     SRI(RDPCSTX_PHY_RX_LD_VAL, RDPCSTX, id),\
0227     SRI(RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG, RDPCSTX, id)
0228
0229 void dcn31_link_encoder_construct(
0230     struct dcn20_link_encoder *enc20,
0231     const struct encoder_init_data *init_data,
0232     const struct encoder_feature_support *enc_features,
0233     const struct dcn10_link_enc_registers *link_regs,
0234     const struct dcn10_link_enc_aux_registers *aux_regs,
0235     const struct dcn10_link_enc_hpd_registers *hpd_regs,
0236     const struct dcn10_link_enc_shift *link_shift,
0237     const struct dcn10_link_enc_mask *link_mask);
0238
0239 /*
0240  * Create a minimal link encoder object with no dc_link object associated with it.
0241  */
0242 void dcn31_link_encoder_construct_minimal(
0243     struct dcn20_link_encoder *enc20,
0244     struct dc_context *ctx,
0245     const struct encoder_feature_support *enc_features,
0246     const struct dcn10_link_enc_registers *link_regs,
0247     enum engine_id eng_id);
0248
0249 void dcn31_link_encoder_set_dio_phy_mux(
0250     struct link_encoder *enc,
0251     enum encoder_type_select sel,
0252     uint32_t hpo_inst);
0253
0254 /*
0255  * Enable DP transmitter and its encoder.
0256  */
0257 void dcn31_link_encoder_enable_dp_output(
0258     struct link_encoder *enc,
0259     const struct dc_link_settings *link_settings,
0260     enum clock_source_id clock_source);
0261
0262 /*
0263  * Enable DP transmitter and its encoder in MST mode.
0264  */
0265 void dcn31_link_encoder_enable_dp_mst_output(
0266     struct link_encoder *enc,
0267     const struct dc_link_settings *link_settings,
0268     enum clock_source_id clock_source);
0269
0270 /*
0271  * Disable transmitter and its encoder.
0272  */
0273 void dcn31_link_encoder_disable_output(
0274     struct link_encoder *enc,
0275     enum signal_type signal);
0276
0277 /*
0278  * Check whether USB-C DP Alt mode is disabled
0279  */
0280 bool dcn31_link_encoder_is_in_alt_mode(
0281     struct link_encoder *enc);
0282
0283 void dcn31_link_encoder_get_max_link_cap(struct link_encoder *enc,
0284     struct dc_link_settings *link_settings);
0285
0286 #endif /* __DC_LINK_ENCODER__DCN31_H__ */