dc/dcn31/dcn31_dccg.h

0001 /*
0002  * Copyright 2018 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef __DCN31_DCCG_H__
0027 #define __DCN31_DCCG_H__
0028
0029 #include "dcn30/dcn30_dccg.h"
0030
0031 #define DCCG_REG_LIST_DCN31() \
0032     SR(DPPCLK_DTO_CTRL),\
0033     DCCG_SRII(DTO_PARAM, DPPCLK, 0),\
0034     DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
0035     DCCG_SRII(DTO_PARAM, DPPCLK, 2),\
0036     DCCG_SRII(DTO_PARAM, DPPCLK, 3),\
0037     SR(PHYASYMCLK_CLOCK_CNTL),\
0038     SR(PHYBSYMCLK_CLOCK_CNTL),\
0039     SR(PHYCSYMCLK_CLOCK_CNTL),\
0040     SR(PHYDSYMCLK_CLOCK_CNTL),\
0041     SR(PHYESYMCLK_CLOCK_CNTL),\
0042     SR(DPSTREAMCLK_CNTL),\
0043     SR(SYMCLK32_SE_CNTL),\
0044     SR(SYMCLK32_LE_CNTL),\
0045     DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
0046     DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\
0047     DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
0048     DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
0049     DCCG_SRII(MODULO, DTBCLK_DTO, 0),\
0050     DCCG_SRII(MODULO, DTBCLK_DTO, 1),\
0051     DCCG_SRII(MODULO, DTBCLK_DTO, 2),\
0052     DCCG_SRII(MODULO, DTBCLK_DTO, 3),\
0053     DCCG_SRII(PHASE, DTBCLK_DTO, 0),\
0054     DCCG_SRII(PHASE, DTBCLK_DTO, 1),\
0055     DCCG_SRII(PHASE, DTBCLK_DTO, 2),\
0056     DCCG_SRII(PHASE, DTBCLK_DTO, 3),\
0057     SR(DCCG_AUDIO_DTBCLK_DTO_MODULO),\
0058     SR(DCCG_AUDIO_DTBCLK_DTO_PHASE),\
0059     SR(DCCG_AUDIO_DTO_SOURCE),\
0060     SR(DENTIST_DISPCLK_CNTL),\
0061     SR(DSCCLK0_DTO_PARAM),\
0062     SR(DSCCLK1_DTO_PARAM),\
0063     SR(DSCCLK2_DTO_PARAM),\
0064     SR(DSCCLK_DTO_CTRL),\
0065     SR(DCCG_GATE_DISABLE_CNTL2),\
0066     SR(DCCG_GATE_DISABLE_CNTL3),\
0067     SR(HDMISTREAMCLK0_DTO_PARAM)
0068
0069
0070 #define DCCG_MASK_SH_LIST_DCN31(mask_sh) \
0071     DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\
0072     DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\
0073     DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 1, mask_sh),\
0074     DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\
0075     DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 2, mask_sh),\
0076     DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 2, mask_sh),\
0077     DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 3, mask_sh),\
0078     DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 3, mask_sh),\
0079     DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\
0080     DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\
0081     DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\
0082     DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\
0083     DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\
0084     DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\
0085     DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\
0086     DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh),\
0087     DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_FORCE_EN, mask_sh),\
0088     DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_FORCE_SRC_SEL, mask_sh),\
0089     DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_FORCE_EN, mask_sh),\
0090     DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_FORCE_SRC_SEL, mask_sh),\
0091     DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE0_EN, mask_sh),\
0092     DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE1_EN, mask_sh),\
0093     DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE2_EN, mask_sh),\
0094     DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE3_EN, mask_sh),\
0095     DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_SRC_SEL, mask_sh),\
0096     DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_SRC_SEL, mask_sh),\
0097     DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_SRC_SEL, mask_sh),\
0098     DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_SRC_SEL, mask_sh),\
0099     DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_EN, mask_sh),\
0100     DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_EN, mask_sh),\
0101     DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_EN, mask_sh),\
0102     DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_EN, mask_sh),\
0103     DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_SRC_SEL, mask_sh),\
0104     DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_SRC_SEL, mask_sh),\
0105     DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_EN, mask_sh),\
0106     DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_EN, mask_sh),\
0107     DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\
0108     DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\
0109     DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\
0110     DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\
0111     DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 0, mask_sh),\
0112     DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 1, mask_sh),\
0113     DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 2, mask_sh),\
0114     DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 3, mask_sh),\
0115     DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\
0116     DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\
0117     DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\
0118     DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\
0119     DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 0, mask_sh),\
0120     DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 1, mask_sh),\
0121     DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 2, mask_sh),\
0122     DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 3, mask_sh),\
0123     DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
0124     DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
0125     DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
0126     DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
0127     DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
0128     DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
0129     DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_MODE, mask_sh), \
0130     DCCG_SF(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_PHASE, mask_sh),\
0131     DCCG_SF(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_MODULO, mask_sh),\
0132     DCCG_SF(DSCCLK1_DTO_PARAM, DSCCLK1_DTO_PHASE, mask_sh),\
0133     DCCG_SF(DSCCLK1_DTO_PARAM, DSCCLK1_DTO_MODULO, mask_sh),\
0134     DCCG_SF(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_PHASE, mask_sh),\
0135     DCCG_SF(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_MODULO, mask_sh),\
0136     DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK0_DTO_ENABLE, mask_sh),\
0137     DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK1_DTO_ENABLE, mask_sh),\
0138     DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK2_DTO_ENABLE, mask_sh),\
0139     DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_GATE_DISABLE, mask_sh),\
0140     DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_GATE_DISABLE, mask_sh),\
0141     DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_GATE_DISABLE, mask_sh),\
0142     DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_GATE_DISABLE, mask_sh),\
0143     DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_GATE_DISABLE, mask_sh),\
0144     DCCG_SF(DCCG_GATE_DISABLE_CNTL3, DPSTREAMCLK_ROOT_GATE_DISABLE, mask_sh),\
0145     DCCG_SF(DCCG_GATE_DISABLE_CNTL3, DPSTREAMCLK_GATE_DISABLE, mask_sh),\
0146     DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE0_GATE_DISABLE, mask_sh),\
0147     DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE1_GATE_DISABLE, mask_sh),\
0148     DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE2_GATE_DISABLE, mask_sh),\
0149     DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE3_GATE_DISABLE, mask_sh),\
0150     DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE0_GATE_DISABLE, mask_sh),\
0151     DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE1_GATE_DISABLE, mask_sh),\
0152     DCCG_SF(HDMISTREAMCLK0_DTO_PARAM, HDMISTREAMCLK0_DTO_PHASE, mask_sh),\
0153     DCCG_SF(HDMISTREAMCLK0_DTO_PARAM, HDMISTREAMCLK0_DTO_MODULO, mask_sh)
0154
0155
0156 struct dccg *dccg31_create(
0157     struct dc_context *ctx,
0158     const struct dccg_registers *regs,
0159     const struct dccg_shift *dccg_shift,
0160     const struct dccg_mask *dccg_mask);
0161
0162 void dccg31_init(struct dccg *dccg);
0163
0164 void dccg31_enable_symclk32_se(
0165         struct dccg *dccg,
0166         int hpo_se_inst,
0167         enum phyd32clk_clock_source phyd32clk);
0168
0169 void dccg31_disable_symclk32_se(
0170         struct dccg *dccg,
0171         int hpo_se_inst);
0172
0173 void dccg31_enable_symclk32_le(
0174         struct dccg *dccg,
0175         int hpo_le_inst,
0176         enum phyd32clk_clock_source phyd32clk);
0177
0178 void dccg31_disable_symclk32_le(
0179         struct dccg *dccg,
0180         int hpo_le_inst);
0181
0182 void dccg31_set_physymclk(
0183         struct dccg *dccg,
0184         int phy_inst,
0185         enum physymclk_clock_source clk_src,
0186         bool force_enable);
0187
0188 void dccg31_set_audio_dtbclk_dto(
0189         struct dccg *dccg,
0190         const struct dtbclk_dto_params *params);
0191
0192 void dccg31_update_dpp_dto(
0193     struct dccg *dccg,
0194     int dpp_inst,
0195     int req_dppclk);
0196
0197 void dccg31_get_dccg_ref_freq(
0198     struct dccg *dccg,
0199     unsigned int xtalin_freq_inKhz,
0200     unsigned int *dccg_ref_freq_inKhz);
0201
0202 void dccg31_set_dpstreamclk(
0203     struct dccg *dccg,
0204     enum streamclk_source src,
0205     int otg_inst,
0206     int dp_hpo_inst);
0207
0208 void dccg31_set_dtbclk_dto(
0209         struct dccg *dccg,
0210         const struct dtbclk_dto_params *params);
0211
0212 void dccg31_otg_add_pixel(
0213     struct dccg *dccg,
0214     uint32_t otg_inst);
0215
0216 void dccg31_otg_drop_pixel(
0217     struct dccg *dccg,
0218     uint32_t otg_inst);
0219
0220 void dccg31_set_dispclk_change_mode(
0221     struct dccg *dccg,
0222     enum dentist_dispclk_change_mode change_mode);
0223
0224 void dccg31_disable_dscclk(struct dccg *dccg, int inst);
0225
0226 void dccg31_enable_dscclk(struct dccg *dccg, int inst);
0227
0228 #endif //__DCN31_DCCG_H__