dc/dcn31/dcn31_apg.h

0001 /*
0002  * Copyright 2020 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef __DAL_DCN31_AGP_H__
0027 #define __DAL_DCN31_AGP_H__
0028
0029
0030 #define DCN31_APG_FROM_APG(apg)\
0031     container_of(apg, struct dcn31_apg, base)
0032
0033 #define APG_DCN31_REG_LIST(id) \
0034     SRI(APG_CONTROL, APG, id), \
0035     SRI(APG_CONTROL2, APG, id),\
0036     SRI(APG_MEM_PWR, APG, id),\
0037     SRI(APG_DBG_GEN_CONTROL, APG, id)
0038
0039 struct dcn31_apg_registers {
0040     uint32_t APG_CONTROL;
0041     uint32_t APG_CONTROL2;
0042     uint32_t APG_MEM_PWR;
0043     uint32_t APG_DBG_GEN_CONTROL;
0044 };
0045
0046
0047 #define DCN31_APG_MASK_SH_LIST(mask_sh)\
0048     SE_SF(APG0_APG_CONTROL, APG_RESET, mask_sh),\
0049     SE_SF(APG0_APG_CONTROL, APG_RESET_DONE, mask_sh),\
0050     SE_SF(APG0_APG_CONTROL2, APG_ENABLE, mask_sh),\
0051     SE_SF(APG0_APG_CONTROL2, APG_DP_AUDIO_STREAM_ID, mask_sh),\
0052     SE_SF(APG0_APG_DBG_GEN_CONTROL, APG_DBG_AUDIO_CHANNEL_ENABLE, mask_sh),\
0053     SE_SF(APG0_APG_MEM_PWR, APG_MEM_PWR_FORCE, mask_sh)
0054
0055 #define APG_DCN31_REG_FIELD_LIST(type) \
0056         type APG_RESET;\
0057         type APG_RESET_DONE;\
0058         type APG_ENABLE;\
0059         type APG_DP_AUDIO_STREAM_ID;\
0060         type APG_DBG_AUDIO_CHANNEL_ENABLE;\
0061         type APG_MEM_PWR_FORCE
0062
0063 struct dcn31_apg_shift {
0064     APG_DCN31_REG_FIELD_LIST(uint8_t);
0065 };
0066
0067 struct dcn31_apg_mask {
0068     APG_DCN31_REG_FIELD_LIST(uint32_t);
0069 };
0070
0071 struct apg {
0072     const struct apg_funcs *funcs;
0073     struct dc_context *ctx;
0074     int inst;
0075 };
0076
0077 struct apg_funcs {
0078
0079     void (*setup_hdmi_audio)(
0080         struct apg *apg);
0081
0082     void (*se_audio_setup)(
0083         struct apg *apg,
0084         unsigned int az_inst,
0085         struct audio_info *audio_info);
0086
0087     void (*audio_mute_control)(
0088         struct apg *apg,
0089         bool mute);
0090
0091     void (*enable_apg)(
0092         struct apg *apg);
0093
0094     void (*disable_apg)(
0095         struct apg *apg);
0096 };
0097
0098
0099
0100 struct dcn31_apg {
0101     struct apg base;
0102     const struct dcn31_apg_registers *regs;
0103     const struct dcn31_apg_shift *apg_shift;
0104     const struct dcn31_apg_mask *apg_mask;
0105 };
0106
0107 void apg31_construct(struct dcn31_apg *apg3,
0108     struct dc_context *ctx,
0109     uint32_t inst,
0110     const struct dcn31_apg_registers *apg_regs,
0111     const struct dcn31_apg_shift *apg_shift,
0112     const struct dcn31_apg_mask *apg_mask);
0113
0114
0115 #endif