dc/dcn31/dcn31_afmt.h

0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef __DAL_DCN31_AFMT_H__
0027 #define __DAL_DCN31_AFMT_H__
0028
0029
0030 #define DCN31_AFMT_FROM_AFMT(afmt)\
0031     container_of(afmt, struct dcn31_afmt, base)
0032
0033 #define AFMT_DCN31_REG_LIST(id) \
0034     SRI(AFMT_INFOFRAME_CONTROL0, AFMT, id), \
0035     SRI(AFMT_VBI_PACKET_CONTROL, AFMT, id), \
0036     SRI(AFMT_AUDIO_PACKET_CONTROL, AFMT, id), \
0037     SRI(AFMT_AUDIO_PACKET_CONTROL2, AFMT, id), \
0038     SRI(AFMT_AUDIO_SRC_CONTROL, AFMT, id), \
0039     SRI(AFMT_60958_0, AFMT, id), \
0040     SRI(AFMT_60958_1, AFMT, id), \
0041     SRI(AFMT_60958_2, AFMT, id), \
0042     SRI(AFMT_MEM_PWR, AFMT, id)
0043
0044 struct dcn31_afmt_registers {
0045     uint32_t AFMT_INFOFRAME_CONTROL0;
0046     uint32_t AFMT_VBI_PACKET_CONTROL;
0047     uint32_t AFMT_AUDIO_PACKET_CONTROL;
0048     uint32_t AFMT_AUDIO_PACKET_CONTROL2;
0049     uint32_t AFMT_AUDIO_SRC_CONTROL;
0050     uint32_t AFMT_60958_0;
0051     uint32_t AFMT_60958_1;
0052     uint32_t AFMT_60958_2;
0053     uint32_t AFMT_MEM_PWR;
0054 };
0055
0056 #define DCN31_AFMT_MASK_SH_LIST(mask_sh)\
0057     SE_SF(AFMT0_AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\
0058     SE_SF(AFMT0_AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, mask_sh),\
0059     SE_SF(AFMT0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, mask_sh),\
0060     SE_SF(AFMT0_AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, mask_sh),\
0061     SE_SF(AFMT0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_LAYOUT_OVRD, mask_sh),\
0062     SE_SF(AFMT0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_60958_OSF_OVRD, mask_sh),\
0063     SE_SF(AFMT0_AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, mask_sh),\
0064     SE_SF(AFMT0_AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, mask_sh),\
0065     SE_SF(AFMT0_AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, mask_sh),\
0066     SE_SF(AFMT0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, mask_sh),\
0067     SE_SF(AFMT0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, mask_sh),\
0068     SE_SF(AFMT0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, mask_sh),\
0069     SE_SF(AFMT0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, mask_sh),\
0070     SE_SF(AFMT0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, mask_sh),\
0071     SE_SF(AFMT0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, mask_sh),\
0072     SE_SF(AFMT0_AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh),\
0073     SE_SF(AFMT0_AFMT_MEM_PWR, AFMT_MEM_PWR_FORCE, mask_sh),\
0074     SE_SF(AFMT0_AFMT_MEM_PWR, AFMT_MEM_PWR_DIS, mask_sh),\
0075     SE_SF(AFMT0_AFMT_MEM_PWR, AFMT_MEM_PWR_STATE, mask_sh)
0076
0077 #define AFMT_DCN31_REG_FIELD_LIST(type) \
0078         type AFMT_AUDIO_INFO_UPDATE;\
0079         type AFMT_AUDIO_SRC_SELECT;\
0080         type AFMT_AUDIO_CHANNEL_ENABLE;\
0081         type AFMT_60958_CS_UPDATE;\
0082         type AFMT_AUDIO_LAYOUT_OVRD;\
0083         type AFMT_60958_OSF_OVRD;\
0084         type AFMT_60958_CS_CHANNEL_NUMBER_L;\
0085         type AFMT_60958_CS_CLOCK_ACCURACY;\
0086         type AFMT_60958_CS_CHANNEL_NUMBER_R;\
0087         type AFMT_60958_CS_CHANNEL_NUMBER_2;\
0088         type AFMT_60958_CS_CHANNEL_NUMBER_3;\
0089         type AFMT_60958_CS_CHANNEL_NUMBER_4;\
0090         type AFMT_60958_CS_CHANNEL_NUMBER_5;\
0091         type AFMT_60958_CS_CHANNEL_NUMBER_6;\
0092         type AFMT_60958_CS_CHANNEL_NUMBER_7;\
0093         type AFMT_AUDIO_SAMPLE_SEND;\
0094         type AFMT_MEM_PWR_FORCE;\
0095         type AFMT_MEM_PWR_DIS;\
0096         type AFMT_MEM_PWR_STATE
0097
0098 struct dcn31_afmt_shift {
0099     AFMT_DCN31_REG_FIELD_LIST(uint8_t);
0100 };
0101
0102 struct dcn31_afmt_mask {
0103     AFMT_DCN31_REG_FIELD_LIST(uint32_t);
0104 };
0105
0106 struct dcn31_afmt {
0107     struct afmt base;
0108     const struct dcn31_afmt_registers *regs;
0109     const struct dcn31_afmt_shift *afmt_shift;
0110     const struct dcn31_afmt_mask *afmt_mask;
0111 };
0112
0113 void afmt31_poweron(
0114         struct afmt *afmt);
0115
0116 void afmt31_powerdown(
0117         struct afmt *afmt);
0118
0119 void afmt31_construct(struct dcn31_afmt *afmt31,
0120     struct dc_context *ctx,
0121     uint32_t inst,
0122     const struct dcn31_afmt_registers *afmt_regs,
0123     const struct dcn31_afmt_shift *afmt_shift,
0124     const struct dcn31_afmt_mask *afmt_mask);
0125
0126 #endif