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0001 // SPDX-License-Identifier: MIT
0002 /*
0003  * Copyright (C) 2021 Advanced Micro Devices, Inc.
0004  *
0005  * Authors: AMD
0006  */
0007 
0008 #include "dcn303_init.h"
0009 #include "dcn303_resource.h"
0010 #include "dcn303_dccg.h"
0011 #include "irq/dcn303/irq_service_dcn303.h"
0012 
0013 #include "dcn30/dcn30_dio_link_encoder.h"
0014 #include "dcn30/dcn30_dio_stream_encoder.h"
0015 #include "dcn30/dcn30_dpp.h"
0016 #include "dcn30/dcn30_dwb.h"
0017 #include "dcn30/dcn30_hubbub.h"
0018 #include "dcn30/dcn30_hubp.h"
0019 #include "dcn30/dcn30_mmhubbub.h"
0020 #include "dcn30/dcn30_mpc.h"
0021 #include "dcn30/dcn30_opp.h"
0022 #include "dcn30/dcn30_optc.h"
0023 #include "dcn30/dcn30_resource.h"
0024 
0025 #include "dcn20/dcn20_dsc.h"
0026 #include "dcn20/dcn20_resource.h"
0027 
0028 #include "dml/dcn30/dcn30_fpu.h"
0029 
0030 #include "dcn10/dcn10_resource.h"
0031 
0032 #include "dc_link_ddc.h"
0033 
0034 #include "dce/dce_abm.h"
0035 #include "dce/dce_audio.h"
0036 #include "dce/dce_aux.h"
0037 #include "dce/dce_clock_source.h"
0038 #include "dce/dce_hwseq.h"
0039 #include "dce/dce_i2c_hw.h"
0040 #include "dce/dce_panel_cntl.h"
0041 #include "dce/dmub_abm.h"
0042 #include "dce/dmub_psr.h"
0043 #include "clk_mgr.h"
0044 
0045 #include "hw_sequencer_private.h"
0046 #include "reg_helper.h"
0047 #include "resource.h"
0048 #include "vm_helper.h"
0049 
0050 #include "sienna_cichlid_ip_offset.h"
0051 #include "dcn/dcn_3_0_3_offset.h"
0052 #include "dcn/dcn_3_0_3_sh_mask.h"
0053 #include "dpcs/dpcs_3_0_3_offset.h"
0054 #include "dpcs/dpcs_3_0_3_sh_mask.h"
0055 #include "nbio/nbio_2_3_offset.h"
0056 
0057 #include "dml/dcn303/dcn303_fpu.h"
0058 
0059 #define DC_LOGGER_INIT(logger)
0060 
0061 
0062 static const struct dc_debug_options debug_defaults_drv = {
0063         .disable_dmcu = true,
0064         .force_abm_enable = false,
0065         .timing_trace = false,
0066         .clock_trace = true,
0067         .disable_pplib_clock_request = true,
0068         .pipe_split_policy = MPC_SPLIT_DYNAMIC,
0069         .force_single_disp_pipe_split = false,
0070         .disable_dcc = DCC_ENABLE,
0071         .vsr_support = true,
0072         .performance_trace = false,
0073         .max_downscale_src_width = 7680,/*upto 8K*/
0074         .disable_pplib_wm_range = false,
0075         .scl_reset_length10 = true,
0076         .sanity_checks = false,
0077         .underflow_assert_delay_us = 0xFFFFFFFF,
0078         .dwb_fi_phase = -1, // -1 = disable,
0079         .dmub_command_table = true,
0080         .disable_idle_power_optimizations = false,
0081 };
0082 
0083 static const struct dc_debug_options debug_defaults_diags = {
0084         .disable_dmcu = true,
0085         .force_abm_enable = false,
0086         .timing_trace = true,
0087         .clock_trace = true,
0088         .disable_dpp_power_gate = true,
0089         .disable_hubp_power_gate = true,
0090         .disable_clock_gate = true,
0091         .disable_pplib_clock_request = true,
0092         .disable_pplib_wm_range = true,
0093         .disable_stutter = false,
0094         .scl_reset_length10 = true,
0095         .dwb_fi_phase = -1, // -1 = disable
0096         .dmub_command_table = true,
0097         .enable_tri_buf = true,
0098         .disable_psr = true,
0099 };
0100 
0101 enum dcn303_clk_src_array_id {
0102     DCN303_CLK_SRC_PLL0,
0103     DCN303_CLK_SRC_PLL1,
0104     DCN303_CLK_SRC_TOTAL
0105 };
0106 
0107 static const struct resource_caps res_cap_dcn303 = {
0108         .num_timing_generator = 2,
0109         .num_opp = 2,
0110         .num_video_plane = 2,
0111         .num_audio = 2,
0112         .num_stream_encoder = 2,
0113         .num_dwb = 1,
0114         .num_ddc = 2,
0115         .num_vmid = 16,
0116         .num_mpc_3dlut = 1,
0117         .num_dsc = 2,
0118 };
0119 
0120 static const struct dc_plane_cap plane_cap = {
0121         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
0122         .blends_with_above = true,
0123         .blends_with_below = true,
0124         .per_pixel_alpha = true,
0125         .pixel_format_support = {
0126                 .argb8888 = true,
0127                 .nv12 = true,
0128                 .fp16 = true,
0129                 .p010 = true,
0130                 .ayuv = false,
0131         },
0132         .max_upscale_factor = {
0133                 .argb8888 = 16000,
0134                 .nv12 = 16000,
0135                 .fp16 = 16000
0136         },
0137         .max_downscale_factor = {
0138                 .argb8888 = 600,
0139                 .nv12 = 600,
0140                 .fp16 = 600
0141         },
0142         16,
0143         16
0144 };
0145 
0146 /* NBIO */
0147 #define NBIO_BASE_INNER(seg) \
0148         NBIO_BASE__INST0_SEG ## seg
0149 
0150 #define NBIO_BASE(seg) \
0151         NBIO_BASE_INNER(seg)
0152 
0153 #define NBIO_SR(reg_name)\
0154         .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
0155         mm ## reg_name
0156 
0157 /* DCN */
0158 #undef BASE_INNER
0159 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
0160 
0161 #define BASE(seg) BASE_INNER(seg)
0162 
0163 #define SR(reg_name)\
0164         .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
0165 
0166 #define SF(reg_name, field_name, post_fix)\
0167         .field_name = reg_name ## __ ## field_name ## post_fix
0168 
0169 #define SRI(reg_name, block, id)\
0170         .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name
0171 
0172 #define SRI2(reg_name, block, id)\
0173         .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
0174 
0175 #define SRII(reg_name, block, id)\
0176         .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0177         mm ## block ## id ## _ ## reg_name
0178 
0179 #define DCCG_SRII(reg_name, block, id)\
0180         .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0181         mm ## block ## id ## _ ## reg_name
0182 
0183 #define VUPDATE_SRII(reg_name, block, id)\
0184         .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
0185         mm ## reg_name ## _ ## block ## id
0186 
0187 #define SRII_DWB(reg_name, temp_name, block, id)\
0188         .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
0189         mm ## block ## id ## _ ## temp_name
0190 
0191 #define SRII_MPC_RMU(reg_name, block, id)\
0192         .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0193         mm ## block ## id ## _ ## reg_name
0194 
0195 static const struct dcn_hubbub_registers hubbub_reg = {
0196         HUBBUB_REG_LIST_DCN30(0)
0197 };
0198 
0199 static const struct dcn_hubbub_shift hubbub_shift = {
0200         HUBBUB_MASK_SH_LIST_DCN30(__SHIFT)
0201 };
0202 
0203 static const struct dcn_hubbub_mask hubbub_mask = {
0204         HUBBUB_MASK_SH_LIST_DCN30(_MASK)
0205 };
0206 
0207 #define vmid_regs(id)\
0208         [id] = { DCN20_VMID_REG_LIST(id) }
0209 
0210 static const struct dcn_vmid_registers vmid_regs[] = {
0211         vmid_regs(0),
0212         vmid_regs(1),
0213         vmid_regs(2),
0214         vmid_regs(3),
0215         vmid_regs(4),
0216         vmid_regs(5),
0217         vmid_regs(6),
0218         vmid_regs(7),
0219         vmid_regs(8),
0220         vmid_regs(9),
0221         vmid_regs(10),
0222         vmid_regs(11),
0223         vmid_regs(12),
0224         vmid_regs(13),
0225         vmid_regs(14),
0226         vmid_regs(15)
0227 };
0228 
0229 static const struct dcn20_vmid_shift vmid_shifts = {
0230         DCN20_VMID_MASK_SH_LIST(__SHIFT)
0231 };
0232 
0233 static const struct dcn20_vmid_mask vmid_masks = {
0234         DCN20_VMID_MASK_SH_LIST(_MASK)
0235 };
0236 
0237 static struct hubbub *dcn303_hubbub_create(struct dc_context *ctx)
0238 {
0239     int i;
0240 
0241     struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL);
0242 
0243     if (!hubbub3)
0244         return NULL;
0245 
0246     hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask);
0247 
0248     for (i = 0; i < res_cap_dcn303.num_vmid; i++) {
0249         struct dcn20_vmid *vmid = &hubbub3->vmid[i];
0250 
0251         vmid->ctx = ctx;
0252 
0253         vmid->regs = &vmid_regs[i];
0254         vmid->shifts = &vmid_shifts;
0255         vmid->masks = &vmid_masks;
0256     }
0257 
0258     return &hubbub3->base;
0259 }
0260 
0261 #define vpg_regs(id)\
0262         [id] = { VPG_DCN3_REG_LIST(id) }
0263 
0264 static const struct dcn30_vpg_registers vpg_regs[] = {
0265         vpg_regs(0),
0266         vpg_regs(1),
0267         vpg_regs(2)
0268 };
0269 
0270 static const struct dcn30_vpg_shift vpg_shift = {
0271         DCN3_VPG_MASK_SH_LIST(__SHIFT)
0272 };
0273 
0274 static const struct dcn30_vpg_mask vpg_mask = {
0275         DCN3_VPG_MASK_SH_LIST(_MASK)
0276 };
0277 
0278 static struct vpg *dcn303_vpg_create(struct dc_context *ctx, uint32_t inst)
0279 {
0280     struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
0281 
0282     if (!vpg3)
0283         return NULL;
0284 
0285     vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask);
0286 
0287     return &vpg3->base;
0288 }
0289 
0290 #define afmt_regs(id)\
0291         [id] = { AFMT_DCN3_REG_LIST(id) }
0292 
0293 static const struct dcn30_afmt_registers afmt_regs[] = {
0294         afmt_regs(0),
0295         afmt_regs(1),
0296         afmt_regs(2)
0297 };
0298 
0299 static const struct dcn30_afmt_shift afmt_shift = {
0300         DCN3_AFMT_MASK_SH_LIST(__SHIFT)
0301 };
0302 
0303 static const struct dcn30_afmt_mask afmt_mask = {
0304         DCN3_AFMT_MASK_SH_LIST(_MASK)
0305 };
0306 
0307 static struct afmt *dcn303_afmt_create(struct dc_context *ctx, uint32_t inst)
0308 {
0309     struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
0310 
0311     if (!afmt3)
0312         return NULL;
0313 
0314     afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask);
0315 
0316     return &afmt3->base;
0317 }
0318 
0319 #define audio_regs(id)\
0320         [id] = { AUD_COMMON_REG_LIST(id) }
0321 
0322 static const struct dce_audio_registers audio_regs[] = {
0323         audio_regs(0),
0324         audio_regs(1),
0325         audio_regs(2),
0326         audio_regs(3),
0327         audio_regs(4),
0328         audio_regs(5),
0329         audio_regs(6)
0330 };
0331 
0332 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
0333         SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
0334         SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
0335         AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
0336 
0337 static const struct dce_audio_shift audio_shift = {
0338         DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
0339 };
0340 
0341 static const struct dce_audio_mask audio_mask = {
0342         DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
0343 };
0344 
0345 static struct audio *dcn303_create_audio(struct dc_context *ctx, unsigned int inst)
0346 {
0347     return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask);
0348 }
0349 
0350 #define stream_enc_regs(id)\
0351         [id] = { SE_DCN3_REG_LIST(id) }
0352 
0353 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
0354         stream_enc_regs(0),
0355         stream_enc_regs(1)
0356 };
0357 
0358 static const struct dcn10_stream_encoder_shift se_shift = {
0359         SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
0360 };
0361 
0362 static const struct dcn10_stream_encoder_mask se_mask = {
0363         SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
0364 };
0365 
0366 static struct stream_encoder *dcn303_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx)
0367 {
0368     struct dcn10_stream_encoder *enc1;
0369     struct vpg *vpg;
0370     struct afmt *afmt;
0371     int vpg_inst;
0372     int afmt_inst;
0373 
0374     /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
0375     if (eng_id <= ENGINE_ID_DIGB) {
0376         vpg_inst = eng_id;
0377         afmt_inst = eng_id;
0378     } else
0379         return NULL;
0380 
0381     enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
0382     vpg = dcn303_vpg_create(ctx, vpg_inst);
0383     afmt = dcn303_afmt_create(ctx, afmt_inst);
0384 
0385     if (!enc1 || !vpg || !afmt) {
0386         kfree(enc1);
0387         kfree(vpg);
0388         kfree(afmt);
0389         return NULL;
0390     }
0391 
0392     dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id],
0393             &se_shift, &se_mask);
0394 
0395     return &enc1->base;
0396 }
0397 
0398 #define clk_src_regs(index, pllid)\
0399         [index] = { CS_COMMON_REG_LIST_DCN3_03(index, pllid) }
0400 
0401 static const struct dce110_clk_src_regs clk_src_regs[] = {
0402         clk_src_regs(0, A),
0403         clk_src_regs(1, B)
0404 };
0405 
0406 static const struct dce110_clk_src_shift cs_shift = {
0407         CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
0408 };
0409 
0410 static const struct dce110_clk_src_mask cs_mask = {
0411         CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
0412 };
0413 
0414 static struct clock_source *dcn303_clock_source_create(struct dc_context *ctx, struct dc_bios *bios,
0415         enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src)
0416 {
0417     struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
0418 
0419     if (!clk_src)
0420         return NULL;
0421 
0422     if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) {
0423         clk_src->base.dp_clk_src = dp_clk_src;
0424         return &clk_src->base;
0425     }
0426 
0427     BREAK_TO_DEBUGGER();
0428     return NULL;
0429 }
0430 
0431 static const struct dce_hwseq_registers hwseq_reg = {
0432         HWSEQ_DCN303_REG_LIST()
0433 };
0434 
0435 static const struct dce_hwseq_shift hwseq_shift = {
0436         HWSEQ_DCN303_MASK_SH_LIST(__SHIFT)
0437 };
0438 
0439 static const struct dce_hwseq_mask hwseq_mask = {
0440         HWSEQ_DCN303_MASK_SH_LIST(_MASK)
0441 };
0442 
0443 static struct dce_hwseq *dcn303_hwseq_create(struct dc_context *ctx)
0444 {
0445     struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
0446 
0447     if (hws) {
0448         hws->ctx = ctx;
0449         hws->regs = &hwseq_reg;
0450         hws->shifts = &hwseq_shift;
0451         hws->masks = &hwseq_mask;
0452     }
0453     return hws;
0454 }
0455 
0456 #define hubp_regs(id)\
0457         [id] = { HUBP_REG_LIST_DCN30(id) }
0458 
0459 static const struct dcn_hubp2_registers hubp_regs[] = {
0460         hubp_regs(0),
0461         hubp_regs(1)
0462 };
0463 
0464 static const struct dcn_hubp2_shift hubp_shift = {
0465         HUBP_MASK_SH_LIST_DCN30(__SHIFT)
0466 };
0467 
0468 static const struct dcn_hubp2_mask hubp_mask = {
0469         HUBP_MASK_SH_LIST_DCN30(_MASK)
0470 };
0471 
0472 static struct hubp *dcn303_hubp_create(struct dc_context *ctx, uint32_t inst)
0473 {
0474     struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
0475 
0476     if (!hubp2)
0477         return NULL;
0478 
0479     if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask))
0480         return &hubp2->base;
0481 
0482     BREAK_TO_DEBUGGER();
0483     kfree(hubp2);
0484     return NULL;
0485 }
0486 
0487 #define dpp_regs(id)\
0488         [id] = { DPP_REG_LIST_DCN30(id) }
0489 
0490 static const struct dcn3_dpp_registers dpp_regs[] = {
0491         dpp_regs(0),
0492         dpp_regs(1)
0493 };
0494 
0495 static const struct dcn3_dpp_shift tf_shift = {
0496         DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
0497 };
0498 
0499 static const struct dcn3_dpp_mask tf_mask = {
0500         DPP_REG_LIST_SH_MASK_DCN30(_MASK)
0501 };
0502 
0503 static struct dpp *dcn303_dpp_create(struct dc_context *ctx, uint32_t inst)
0504 {
0505     struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
0506 
0507     if (!dpp)
0508         return NULL;
0509 
0510     if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask))
0511         return &dpp->base;
0512 
0513     BREAK_TO_DEBUGGER();
0514     kfree(dpp);
0515     return NULL;
0516 }
0517 
0518 #define opp_regs(id)\
0519         [id] = { OPP_REG_LIST_DCN30(id) }
0520 
0521 static const struct dcn20_opp_registers opp_regs[] = {
0522         opp_regs(0),
0523         opp_regs(1)
0524 };
0525 
0526 static const struct dcn20_opp_shift opp_shift = {
0527         OPP_MASK_SH_LIST_DCN20(__SHIFT)
0528 };
0529 
0530 static const struct dcn20_opp_mask opp_mask = {
0531         OPP_MASK_SH_LIST_DCN20(_MASK)
0532 };
0533 
0534 static struct output_pixel_processor *dcn303_opp_create(struct dc_context *ctx, uint32_t inst)
0535 {
0536     struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
0537 
0538     if (!opp) {
0539         BREAK_TO_DEBUGGER();
0540         return NULL;
0541     }
0542 
0543     dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
0544     return &opp->base;
0545 }
0546 
0547 #define optc_regs(id)\
0548         [id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) }
0549 
0550 static const struct dcn_optc_registers optc_regs[] = {
0551         optc_regs(0),
0552         optc_regs(1)
0553 };
0554 
0555 static const struct dcn_optc_shift optc_shift = {
0556         OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
0557 };
0558 
0559 static const struct dcn_optc_mask optc_mask = {
0560         OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
0561 };
0562 
0563 static struct timing_generator *dcn303_timing_generator_create(struct dc_context *ctx, uint32_t instance)
0564 {
0565     struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL);
0566 
0567     if (!tgn10)
0568         return NULL;
0569 
0570     tgn10->base.inst = instance;
0571     tgn10->base.ctx = ctx;
0572 
0573     tgn10->tg_regs = &optc_regs[instance];
0574     tgn10->tg_shift = &optc_shift;
0575     tgn10->tg_mask = &optc_mask;
0576 
0577     dcn30_timing_generator_init(tgn10);
0578 
0579     return &tgn10->base;
0580 }
0581 
0582 static const struct dcn30_mpc_registers mpc_regs = {
0583         MPC_REG_LIST_DCN3_0(0),
0584         MPC_REG_LIST_DCN3_0(1),
0585         MPC_OUT_MUX_REG_LIST_DCN3_0(0),
0586         MPC_OUT_MUX_REG_LIST_DCN3_0(1),
0587         MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
0588         MPC_RMU_REG_LIST_DCN3AG(0),
0589         MPC_DWB_MUX_REG_LIST_DCN3_0(0),
0590 };
0591 
0592 static const struct dcn30_mpc_shift mpc_shift = {
0593         MPC_COMMON_MASK_SH_LIST_DCN303(__SHIFT)
0594 };
0595 
0596 static const struct dcn30_mpc_mask mpc_mask = {
0597         MPC_COMMON_MASK_SH_LIST_DCN303(_MASK)
0598 };
0599 
0600 static struct mpc *dcn303_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu)
0601 {
0602     struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL);
0603 
0604     if (!mpc30)
0605         return NULL;
0606 
0607     dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu);
0608 
0609     return &mpc30->base;
0610 }
0611 
0612 #define dsc_regsDCN20(id)\
0613 [id] = { DSC_REG_LIST_DCN20(id) }
0614 
0615 static const struct dcn20_dsc_registers dsc_regs[] = {
0616         dsc_regsDCN20(0),
0617         dsc_regsDCN20(1)
0618 };
0619 
0620 static const struct dcn20_dsc_shift dsc_shift = {
0621         DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
0622 };
0623 
0624 static const struct dcn20_dsc_mask dsc_mask = {
0625         DSC_REG_LIST_SH_MASK_DCN20(_MASK)
0626 };
0627 
0628 static struct display_stream_compressor *dcn303_dsc_create(struct dc_context *ctx, uint32_t inst)
0629 {
0630     struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
0631 
0632     if (!dsc) {
0633         BREAK_TO_DEBUGGER();
0634         return NULL;
0635     }
0636 
0637     dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
0638     return &dsc->base;
0639 }
0640 
0641 #define dwbc_regs_dcn3(id)\
0642 [id] = { DWBC_COMMON_REG_LIST_DCN30(id) }
0643 
0644 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
0645         dwbc_regs_dcn3(0)
0646 };
0647 
0648 static const struct dcn30_dwbc_shift dwbc30_shift = {
0649         DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
0650 };
0651 
0652 static const struct dcn30_dwbc_mask dwbc30_mask = {
0653         DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
0654 };
0655 
0656 static bool dcn303_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
0657 {
0658     int i;
0659     uint32_t pipe_count = pool->res_cap->num_dwb;
0660 
0661     for (i = 0; i < pipe_count; i++) {
0662         struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL);
0663 
0664         if (!dwbc30) {
0665             dm_error("DC: failed to create dwbc30!\n");
0666             return false;
0667         }
0668 
0669         dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i);
0670 
0671         pool->dwbc[i] = &dwbc30->base;
0672     }
0673     return true;
0674 }
0675 
0676 #define mcif_wb_regs_dcn3(id)\
0677 [id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) }
0678 
0679 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
0680         mcif_wb_regs_dcn3(0)
0681 };
0682 
0683 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
0684         MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
0685 };
0686 
0687 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
0688         MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
0689 };
0690 
0691 static bool dcn303_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
0692 {
0693     int i;
0694     uint32_t pipe_count = pool->res_cap->num_dwb;
0695 
0696     for (i = 0; i < pipe_count; i++) {
0697         struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL);
0698 
0699         if (!mcif_wb30) {
0700             dm_error("DC: failed to create mcif_wb30!\n");
0701             return false;
0702         }
0703 
0704         dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i);
0705 
0706         pool->mcif_wb[i] = &mcif_wb30->base;
0707     }
0708     return true;
0709 }
0710 
0711 #define aux_engine_regs(id)\
0712 [id] = {\
0713         AUX_COMMON_REG_LIST0(id), \
0714         .AUXN_IMPCAL = 0, \
0715         .AUXP_IMPCAL = 0, \
0716         .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
0717 }
0718 
0719 static const struct dce110_aux_registers aux_engine_regs[] = {
0720         aux_engine_regs(0),
0721         aux_engine_regs(1)
0722 };
0723 
0724 static const struct dce110_aux_registers_shift aux_shift = {
0725         DCN_AUX_MASK_SH_LIST(__SHIFT)
0726 };
0727 
0728 static const struct dce110_aux_registers_mask aux_mask = {
0729         DCN_AUX_MASK_SH_LIST(_MASK)
0730 };
0731 
0732 static struct dce_aux *dcn303_aux_engine_create(struct dc_context *ctx, uint32_t inst)
0733 {
0734     struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
0735 
0736     if (!aux_engine)
0737         return NULL;
0738 
0739     dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
0740             &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support);
0741 
0742     return &aux_engine->base;
0743 }
0744 
0745 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
0746 
0747 static const struct dce_i2c_registers i2c_hw_regs[] = {
0748         i2c_inst_regs(1),
0749         i2c_inst_regs(2)
0750 };
0751 
0752 static const struct dce_i2c_shift i2c_shifts = {
0753         I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
0754 };
0755 
0756 static const struct dce_i2c_mask i2c_masks = {
0757         I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
0758 };
0759 
0760 static struct dce_i2c_hw *dcn303_i2c_hw_create(struct dc_context *ctx, uint32_t inst)
0761 {
0762     struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
0763 
0764     if (!dce_i2c_hw)
0765         return NULL;
0766 
0767     dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
0768 
0769     return dce_i2c_hw;
0770 }
0771 
0772 static const struct encoder_feature_support link_enc_feature = {
0773         .max_hdmi_deep_color = COLOR_DEPTH_121212,
0774         .max_hdmi_pixel_clock = 600000,
0775         .hdmi_ycbcr420_supported = true,
0776         .dp_ycbcr420_supported = true,
0777         .fec_supported = true,
0778         .flags.bits.IS_HBR2_CAPABLE = true,
0779         .flags.bits.IS_HBR3_CAPABLE = true,
0780         .flags.bits.IS_TPS3_CAPABLE = true,
0781         .flags.bits.IS_TPS4_CAPABLE = true
0782 };
0783 
0784 #define link_regs(id, phyid)\
0785         [id] = {\
0786                 LE_DCN3_REG_LIST(id), \
0787                 UNIPHY_DCN2_REG_LIST(phyid), \
0788                 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
0789         }
0790 
0791 static const struct dcn10_link_enc_registers link_enc_regs[] = {
0792         link_regs(0, A),
0793         link_regs(1, B)
0794 };
0795 
0796 static const struct dcn10_link_enc_shift le_shift = {
0797         LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT),
0798         DPCS_DCN2_MASK_SH_LIST(__SHIFT)
0799 };
0800 
0801 static const struct dcn10_link_enc_mask le_mask = {
0802         LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),
0803         DPCS_DCN2_MASK_SH_LIST(_MASK)
0804 };
0805 
0806 #define aux_regs(id)\
0807         [id] = { DCN2_AUX_REG_LIST(id) }
0808 
0809 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
0810         aux_regs(0),
0811         aux_regs(1)
0812 };
0813 
0814 #define hpd_regs(id)\
0815         [id] = { HPD_REG_LIST(id) }
0816 
0817 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
0818         hpd_regs(0),
0819         hpd_regs(1)
0820 };
0821 
0822 static struct link_encoder *dcn303_link_encoder_create(
0823     struct dc_context *ctx,
0824     const struct encoder_init_data *enc_init_data)
0825 {
0826     struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
0827 
0828     if (!enc20)
0829         return NULL;
0830 
0831     dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature,
0832             &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1],
0833             &link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask);
0834 
0835     return &enc20->enc10.base;
0836 }
0837 
0838 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
0839         { DCN_PANEL_CNTL_REG_LIST() }
0840 };
0841 
0842 static const struct dce_panel_cntl_shift panel_cntl_shift = {
0843         DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
0844 };
0845 
0846 static const struct dce_panel_cntl_mask panel_cntl_mask = {
0847         DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
0848 };
0849 
0850 static struct panel_cntl *dcn303_panel_cntl_create(const struct panel_cntl_init_data *init_data)
0851 {
0852     struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
0853 
0854     if (!panel_cntl)
0855         return NULL;
0856 
0857     dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst],
0858             &panel_cntl_shift, &panel_cntl_mask);
0859 
0860     return &panel_cntl->base;
0861 }
0862 
0863 static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps)
0864 {
0865     generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
0866             FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
0867 }
0868 
0869 static const struct resource_create_funcs res_create_funcs = {
0870         .read_dce_straps = read_dce_straps,
0871         .create_audio = dcn303_create_audio,
0872         .create_stream_encoder = dcn303_stream_encoder_create,
0873         .create_hwseq = dcn303_hwseq_create,
0874 };
0875 
0876 static const struct resource_create_funcs res_create_maximus_funcs = {
0877         .read_dce_straps = NULL,
0878         .create_audio = NULL,
0879         .create_stream_encoder = NULL,
0880         .create_hwseq = dcn303_hwseq_create,
0881 };
0882 
0883 static bool is_soc_bounding_box_valid(struct dc *dc)
0884 {
0885     uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
0886 
0887     if (ASICREV_IS_BEIGE_GOBY_P(hw_internal_rev))
0888         return true;
0889 
0890     return false;
0891 }
0892 
0893 static bool init_soc_bounding_box(struct dc *dc,  struct resource_pool *pool)
0894 {
0895     struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_03_soc;
0896     struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_03_ip;
0897 
0898     DC_LOGGER_INIT(dc->ctx->logger);
0899 
0900     if (!is_soc_bounding_box_valid(dc)) {
0901         DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
0902         return false;
0903     }
0904 
0905     loaded_ip->max_num_otg = pool->pipe_count;
0906     loaded_ip->max_num_dpp = pool->pipe_count;
0907     loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
0908     DC_FP_START();
0909     dcn20_patch_bounding_box(dc, loaded_bb);
0910     DC_FP_END();
0911 
0912     if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
0913         struct bp_soc_bb_info bb_info = { 0 };
0914 
0915         if (dc->ctx->dc_bios->funcs->get_soc_bb_info(
0916                 dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
0917                     DC_FP_START();
0918                     dcn303_fpu_init_soc_bounding_box(bb_info);
0919                     DC_FP_END();
0920         }
0921     }
0922 
0923     return true;
0924 }
0925 
0926 static void dcn303_resource_destruct(struct resource_pool *pool)
0927 {
0928     unsigned int i;
0929 
0930     for (i = 0; i < pool->stream_enc_count; i++) {
0931         if (pool->stream_enc[i] != NULL) {
0932             if (pool->stream_enc[i]->vpg != NULL) {
0933                 kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg));
0934                 pool->stream_enc[i]->vpg = NULL;
0935             }
0936             if (pool->stream_enc[i]->afmt != NULL) {
0937                 kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt));
0938                 pool->stream_enc[i]->afmt = NULL;
0939             }
0940             kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i]));
0941             pool->stream_enc[i] = NULL;
0942         }
0943     }
0944 
0945     for (i = 0; i < pool->res_cap->num_dsc; i++) {
0946         if (pool->dscs[i] != NULL)
0947             dcn20_dsc_destroy(&pool->dscs[i]);
0948     }
0949 
0950     if (pool->mpc != NULL) {
0951         kfree(TO_DCN20_MPC(pool->mpc));
0952         pool->mpc = NULL;
0953     }
0954 
0955     if (pool->hubbub != NULL) {
0956         kfree(pool->hubbub);
0957         pool->hubbub = NULL;
0958     }
0959 
0960     for (i = 0; i < pool->pipe_count; i++) {
0961         if (pool->dpps[i] != NULL) {
0962             kfree(TO_DCN20_DPP(pool->dpps[i]));
0963             pool->dpps[i] = NULL;
0964         }
0965 
0966         if (pool->hubps[i] != NULL) {
0967             kfree(TO_DCN20_HUBP(pool->hubps[i]));
0968             pool->hubps[i] = NULL;
0969         }
0970 
0971         if (pool->irqs != NULL)
0972             dal_irq_service_destroy(&pool->irqs);
0973     }
0974 
0975     for (i = 0; i < pool->res_cap->num_ddc; i++) {
0976         if (pool->engines[i] != NULL)
0977             dce110_engine_destroy(&pool->engines[i]);
0978         if (pool->hw_i2cs[i] != NULL) {
0979             kfree(pool->hw_i2cs[i]);
0980             pool->hw_i2cs[i] = NULL;
0981         }
0982         if (pool->sw_i2cs[i] != NULL) {
0983             kfree(pool->sw_i2cs[i]);
0984             pool->sw_i2cs[i] = NULL;
0985         }
0986     }
0987 
0988     for (i = 0; i < pool->res_cap->num_opp; i++) {
0989         if (pool->opps[i] != NULL)
0990             pool->opps[i]->funcs->opp_destroy(&pool->opps[i]);
0991     }
0992 
0993     for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
0994         if (pool->timing_generators[i] != NULL) {
0995             kfree(DCN10TG_FROM_TG(pool->timing_generators[i]));
0996             pool->timing_generators[i] = NULL;
0997         }
0998     }
0999 
1000     for (i = 0; i < pool->res_cap->num_dwb; i++) {
1001         if (pool->dwbc[i] != NULL) {
1002             kfree(TO_DCN30_DWBC(pool->dwbc[i]));
1003             pool->dwbc[i] = NULL;
1004         }
1005         if (pool->mcif_wb[i] != NULL) {
1006             kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i]));
1007             pool->mcif_wb[i] = NULL;
1008         }
1009     }
1010 
1011     for (i = 0; i < pool->audio_count; i++) {
1012         if (pool->audios[i])
1013             dce_aud_destroy(&pool->audios[i]);
1014     }
1015 
1016     for (i = 0; i < pool->clk_src_count; i++) {
1017         if (pool->clock_sources[i] != NULL)
1018             dcn20_clock_source_destroy(&pool->clock_sources[i]);
1019     }
1020 
1021     if (pool->dp_clock_source != NULL)
1022         dcn20_clock_source_destroy(&pool->dp_clock_source);
1023 
1024     for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1025         if (pool->mpc_lut[i] != NULL) {
1026             dc_3dlut_func_release(pool->mpc_lut[i]);
1027             pool->mpc_lut[i] = NULL;
1028         }
1029         if (pool->mpc_shaper[i] != NULL) {
1030             dc_transfer_func_release(pool->mpc_shaper[i]);
1031             pool->mpc_shaper[i] = NULL;
1032         }
1033     }
1034 
1035     for (i = 0; i < pool->pipe_count; i++) {
1036         if (pool->multiple_abms[i] != NULL)
1037             dce_abm_destroy(&pool->multiple_abms[i]);
1038     }
1039 
1040     if (pool->psr != NULL)
1041         dmub_psr_destroy(&pool->psr);
1042 
1043     if (pool->dccg != NULL)
1044         dcn_dccg_destroy(&pool->dccg);
1045 
1046     if (pool->oem_device != NULL)
1047         dal_ddc_service_destroy(&pool->oem_device);
1048 }
1049 
1050 static void dcn303_destroy_resource_pool(struct resource_pool **pool)
1051 {
1052     dcn303_resource_destruct(*pool);
1053     kfree(*pool);
1054     *pool = NULL;
1055 }
1056 
1057 
1058 void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1059 {
1060     DC_FP_START();
1061     dcn303_fpu_update_bw_bounding_box(dc, bw_params);
1062     DC_FP_END();
1063 }
1064 
1065 static struct resource_funcs dcn303_res_pool_funcs = {
1066         .destroy = dcn303_destroy_resource_pool,
1067         .link_enc_create = dcn303_link_encoder_create,
1068         .panel_cntl_create = dcn303_panel_cntl_create,
1069         .validate_bandwidth = dcn30_validate_bandwidth,
1070         .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
1071         .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1072         .populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
1073         .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1074         .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1075         .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1076         .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1077         .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1078         .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1079         .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1080         .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1081         .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1082         .update_bw_bounding_box = dcn303_update_bw_bounding_box,
1083         .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1084 };
1085 
1086 static struct dc_cap_funcs cap_funcs = {
1087         .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1088 };
1089 
1090 static const struct bios_registers bios_regs = {
1091         NBIO_SR(BIOS_SCRATCH_3),
1092         NBIO_SR(BIOS_SCRATCH_6)
1093 };
1094 
1095 static const struct dccg_registers dccg_regs = {
1096         DCCG_REG_LIST_DCN3_03()
1097 };
1098 
1099 static const struct dccg_shift dccg_shift = {
1100         DCCG_MASK_SH_LIST_DCN3_03(__SHIFT)
1101 };
1102 
1103 static const struct dccg_mask dccg_mask = {
1104         DCCG_MASK_SH_LIST_DCN3_03(_MASK)
1105 };
1106 
1107 #define abm_regs(id)\
1108         [id] = { ABM_DCN302_REG_LIST(id) }
1109 
1110 static const struct dce_abm_registers abm_regs[] = {
1111         abm_regs(0),
1112         abm_regs(1)
1113 };
1114 
1115 static const struct dce_abm_shift abm_shift = {
1116         ABM_MASK_SH_LIST_DCN30(__SHIFT)
1117 };
1118 
1119 static const struct dce_abm_mask abm_mask = {
1120         ABM_MASK_SH_LIST_DCN30(_MASK)
1121 };
1122 
1123 static bool dcn303_resource_construct(
1124         uint8_t num_virtual_links,
1125         struct dc *dc,
1126         struct resource_pool *pool)
1127 {
1128     int i;
1129     struct dc_context *ctx = dc->ctx;
1130     struct irq_service_init_data init_data;
1131     struct ddc_service_init_data ddc_init_data;
1132 
1133     ctx->dc_bios->regs = &bios_regs;
1134 
1135     pool->res_cap = &res_cap_dcn303;
1136 
1137     pool->funcs = &dcn303_res_pool_funcs;
1138 
1139     /*************************************************
1140      *  Resource + asic cap harcoding                *
1141      *************************************************/
1142     pool->underlay_pipe_index = NO_UNDERLAY_PIPE;
1143     pool->pipe_count = pool->res_cap->num_timing_generator;
1144     pool->mpcc_count = pool->res_cap->num_timing_generator;
1145     dc->caps.max_downscale_ratio = 600;
1146     dc->caps.i2c_speed_in_khz = 100;
1147     dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/
1148     dc->caps.max_cursor_size = 256;
1149     dc->caps.min_horizontal_blanking_period = 80;
1150     dc->caps.dmdata_alloc_size = 2048;
1151 #if defined(CONFIG_DRM_AMD_DC_DCN)
1152     dc->caps.mall_size_per_mem_channel = 4;
1153     /* total size = mall per channel * num channels * 1024 * 1024 */
1154     dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel *
1155                    dc->ctx->dc_bios->vram_info.num_chans *
1156                    1024 * 1024;
1157     dc->caps.cursor_cache_size =
1158         dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
1159 #endif
1160     dc->caps.max_slave_planes = 1;
1161     dc->caps.post_blend_color_processing = true;
1162     dc->caps.force_dp_tps4_for_cp2520 = true;
1163     dc->caps.extended_aux_timeout_support = true;
1164     dc->caps.dmcub_support = true;
1165 
1166     /* Color pipeline capabilities */
1167     dc->caps.color.dpp.dcn_arch = 1;
1168     dc->caps.color.dpp.input_lut_shared = 0;
1169     dc->caps.color.dpp.icsc = 1;
1170     dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1171     dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1172     dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1173     dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1174     dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1175     dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1176     dc->caps.color.dpp.post_csc = 1;
1177     dc->caps.color.dpp.gamma_corr = 1;
1178     dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1179 
1180     dc->caps.color.dpp.hw_3d_lut = 1;
1181     dc->caps.color.dpp.ogam_ram = 1;
1182     // no OGAM ROM on DCN3
1183     dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1184     dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1185     dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1186     dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1187     dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1188     dc->caps.color.dpp.ocsc = 0;
1189 
1190     dc->caps.color.mpc.gamut_remap = 1;
1191     dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3
1192     dc->caps.color.mpc.ogam_ram = 1;
1193     dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1194     dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1195     dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1196     dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1197     dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1198     dc->caps.color.mpc.ocsc = 1;
1199 
1200     /* read VBIOS LTTPR caps */
1201     if (ctx->dc_bios->funcs->get_lttpr_caps) {
1202         enum bp_result bp_query_result;
1203         uint8_t is_vbios_lttpr_enable = 0;
1204 
1205         bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1206         dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1207     }
1208 
1209     if (ctx->dc_bios->funcs->get_lttpr_interop) {
1210         enum bp_result bp_query_result;
1211         uint8_t is_vbios_interop_enabled = 0;
1212 
1213         bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, &is_vbios_interop_enabled);
1214         dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
1215     }
1216 
1217     if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1218         dc->debug = debug_defaults_drv;
1219     else
1220         dc->debug = debug_defaults_diags;
1221 
1222     // Init the vm_helper
1223     if (dc->vm_helper)
1224         vm_helper_init(dc->vm_helper, 16);
1225 
1226     /*************************************************
1227      *  Create resources                             *
1228      *************************************************/
1229 
1230     /* Clock Sources for Pixel Clock*/
1231     pool->clock_sources[DCN303_CLK_SRC_PLL0] =
1232             dcn303_clock_source_create(ctx, ctx->dc_bios,
1233                     CLOCK_SOURCE_COMBO_PHY_PLL0,
1234                     &clk_src_regs[0], false);
1235     pool->clock_sources[DCN303_CLK_SRC_PLL1] =
1236             dcn303_clock_source_create(ctx, ctx->dc_bios,
1237                     CLOCK_SOURCE_COMBO_PHY_PLL1,
1238                     &clk_src_regs[1], false);
1239 
1240     pool->clk_src_count = DCN303_CLK_SRC_TOTAL;
1241 
1242     /* todo: not reuse phy_pll registers */
1243     pool->dp_clock_source =
1244             dcn303_clock_source_create(ctx, ctx->dc_bios,
1245                     CLOCK_SOURCE_ID_DP_DTO,
1246                     &clk_src_regs[0], true);
1247 
1248     for (i = 0; i < pool->clk_src_count; i++) {
1249         if (pool->clock_sources[i] == NULL) {
1250             dm_error("DC: failed to create clock sources!\n");
1251             BREAK_TO_DEBUGGER();
1252             goto create_fail;
1253         }
1254     }
1255 
1256     /* DCCG */
1257     pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1258     if (pool->dccg == NULL) {
1259         dm_error("DC: failed to create dccg!\n");
1260         BREAK_TO_DEBUGGER();
1261         goto create_fail;
1262     }
1263 
1264     /* PP Lib and SMU interfaces */
1265     init_soc_bounding_box(dc, pool);
1266 
1267     /* DML */
1268     dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30);
1269 
1270     /* IRQ */
1271     init_data.ctx = dc->ctx;
1272     pool->irqs = dal_irq_service_dcn303_create(&init_data);
1273     if (!pool->irqs)
1274         goto create_fail;
1275 
1276     /* HUBBUB */
1277     pool->hubbub = dcn303_hubbub_create(ctx);
1278     if (pool->hubbub == NULL) {
1279         BREAK_TO_DEBUGGER();
1280         dm_error("DC: failed to create hubbub!\n");
1281         goto create_fail;
1282     }
1283 
1284     /* HUBPs, DPPs, OPPs and TGs */
1285     for (i = 0; i < pool->pipe_count; i++) {
1286         pool->hubps[i] = dcn303_hubp_create(ctx, i);
1287         if (pool->hubps[i] == NULL) {
1288             BREAK_TO_DEBUGGER();
1289             dm_error("DC: failed to create hubps!\n");
1290             goto create_fail;
1291         }
1292 
1293         pool->dpps[i] = dcn303_dpp_create(ctx, i);
1294         if (pool->dpps[i] == NULL) {
1295             BREAK_TO_DEBUGGER();
1296             dm_error("DC: failed to create dpps!\n");
1297             goto create_fail;
1298         }
1299     }
1300 
1301     for (i = 0; i < pool->res_cap->num_opp; i++) {
1302         pool->opps[i] = dcn303_opp_create(ctx, i);
1303         if (pool->opps[i] == NULL) {
1304             BREAK_TO_DEBUGGER();
1305             dm_error("DC: failed to create output pixel processor!\n");
1306             goto create_fail;
1307         }
1308     }
1309 
1310     for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1311         pool->timing_generators[i] = dcn303_timing_generator_create(ctx, i);
1312         if (pool->timing_generators[i] == NULL) {
1313             BREAK_TO_DEBUGGER();
1314             dm_error("DC: failed to create tg!\n");
1315             goto create_fail;
1316         }
1317     }
1318     pool->timing_generator_count = i;
1319 
1320     /* PSR */
1321     pool->psr = dmub_psr_create(ctx);
1322     if (pool->psr == NULL) {
1323         dm_error("DC: failed to create psr!\n");
1324         BREAK_TO_DEBUGGER();
1325         goto create_fail;
1326     }
1327 
1328     /* ABM */
1329     for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1330         pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask);
1331         if (pool->multiple_abms[i] == NULL) {
1332             dm_error("DC: failed to create abm for pipe %d!\n", i);
1333             BREAK_TO_DEBUGGER();
1334             goto create_fail;
1335         }
1336     }
1337 
1338     /* MPC and DSC */
1339     pool->mpc = dcn303_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut);
1340     if (pool->mpc == NULL) {
1341         BREAK_TO_DEBUGGER();
1342         dm_error("DC: failed to create mpc!\n");
1343         goto create_fail;
1344     }
1345 
1346     for (i = 0; i < pool->res_cap->num_dsc; i++) {
1347         pool->dscs[i] = dcn303_dsc_create(ctx, i);
1348         if (pool->dscs[i] == NULL) {
1349             BREAK_TO_DEBUGGER();
1350             dm_error("DC: failed to create display stream compressor %d!\n", i);
1351             goto create_fail;
1352         }
1353     }
1354 
1355     /* DWB and MMHUBBUB */
1356     if (!dcn303_dwbc_create(ctx, pool)) {
1357         BREAK_TO_DEBUGGER();
1358         dm_error("DC: failed to create dwbc!\n");
1359         goto create_fail;
1360     }
1361 
1362     if (!dcn303_mmhubbub_create(ctx, pool)) {
1363         BREAK_TO_DEBUGGER();
1364         dm_error("DC: failed to create mcif_wb!\n");
1365         goto create_fail;
1366     }
1367 
1368     /* AUX and I2C */
1369     for (i = 0; i < pool->res_cap->num_ddc; i++) {
1370         pool->engines[i] = dcn303_aux_engine_create(ctx, i);
1371         if (pool->engines[i] == NULL) {
1372             BREAK_TO_DEBUGGER();
1373             dm_error("DC:failed to create aux engine!!\n");
1374             goto create_fail;
1375         }
1376         pool->hw_i2cs[i] = dcn303_i2c_hw_create(ctx, i);
1377         if (pool->hw_i2cs[i] == NULL) {
1378             BREAK_TO_DEBUGGER();
1379             dm_error("DC:failed to create hw i2c!!\n");
1380             goto create_fail;
1381         }
1382         pool->sw_i2cs[i] = NULL;
1383     }
1384 
1385     /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
1386     if (!resource_construct(num_virtual_links, dc, pool,
1387             (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
1388                     &res_create_funcs : &res_create_maximus_funcs)))
1389         goto create_fail;
1390 
1391     /* HW Sequencer and Plane caps */
1392     dcn303_hw_sequencer_construct(dc);
1393 
1394     dc->caps.max_planes =  pool->pipe_count;
1395 
1396     for (i = 0; i < dc->caps.max_planes; ++i)
1397         dc->caps.planes[i] = plane_cap;
1398 
1399     dc->cap_funcs = cap_funcs;
1400 
1401     if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
1402         ddc_init_data.ctx = dc->ctx;
1403         ddc_init_data.link = NULL;
1404         ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
1405         ddc_init_data.id.enum_id = 0;
1406         ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
1407         pool->oem_device = dal_ddc_service_create(&ddc_init_data);
1408     } else {
1409         pool->oem_device = NULL;
1410     }
1411 
1412     return true;
1413 
1414 create_fail:
1415 
1416     dcn303_resource_destruct(pool);
1417 
1418     return false;
1419 }
1420 
1421 struct resource_pool *dcn303_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc)
1422 {
1423     struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL);
1424 
1425     if (!pool)
1426         return NULL;
1427 
1428     if (dcn303_resource_construct(init_data->num_virtual_links, dc, pool))
1429         return pool;
1430 
1431     BREAK_TO_DEBUGGER();
1432     kfree(pool);
1433     return NULL;
1434 }
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