dc/dcn303/dcn303_dccg.h

0001 // SPDX-License-Identifier: MIT
0002 /*
0003  * Copyright (C) 2021 Advanced Micro Devices, Inc.
0004  *
0005  * Authors: AMD
0006  */
0007
0008 #ifndef __DCN303_DCCG_H__
0009 #define __DCN303_DCCG_H__
0010
0011 #include "dcn30/dcn30_dccg.h"
0012
0013
0014 #define DCCG_REG_LIST_DCN3_03() \
0015     SR(DPPCLK_DTO_CTRL),\
0016     DCCG_SRII(DTO_PARAM, DPPCLK, 0),\
0017     DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
0018     SR(REFCLK_CNTL),\
0019     SR(DISPCLK_FREQ_CHANGE_CNTL),\
0020     DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
0021     DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1)
0022
0023
0024 #define DCCG_MASK_SH_LIST_DCN3_03(mask_sh) \
0025         DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\
0026         DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\
0027         DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 1, mask_sh),\
0028         DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\
0029         DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\
0030         DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\
0031         DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\
0032         DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh),\
0033         DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_DELAY, mask_sh),\
0034         DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_SIZE, mask_sh),\
0035         DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_FREQ_RAMP_DONE, mask_sh),\
0036         DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_MAX_ERRDET_CYCLES, mask_sh),\
0037         DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_RESET, mask_sh),\
0038         DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_STATE, mask_sh),\
0039         DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_OVR_EN, mask_sh),\
0040         DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_CHG_FWD_CORR_DISABLE, mask_sh),\
0041         DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
0042         DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
0043         DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\
0044         DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh)
0045
0046 #endif //__DCN303_DCCG_H__