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0001 /*
0002  * Copyright 2020 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 
0026 #include "dcn302_init.h"
0027 #include "dcn302_resource.h"
0028 #include "dcn302_dccg.h"
0029 #include "irq/dcn302/irq_service_dcn302.h"
0030 
0031 #include "dcn30/dcn30_dio_link_encoder.h"
0032 #include "dcn30/dcn30_dio_stream_encoder.h"
0033 #include "dcn30/dcn30_dwb.h"
0034 #include "dcn30/dcn30_dpp.h"
0035 #include "dcn30/dcn30_hubbub.h"
0036 #include "dcn30/dcn30_hubp.h"
0037 #include "dcn30/dcn30_mmhubbub.h"
0038 #include "dcn30/dcn30_mpc.h"
0039 #include "dcn30/dcn30_opp.h"
0040 #include "dcn30/dcn30_optc.h"
0041 #include "dcn30/dcn30_resource.h"
0042 
0043 #include "dcn20/dcn20_dsc.h"
0044 #include "dcn20/dcn20_resource.h"
0045 
0046 #include "dml/dcn30/dcn30_fpu.h"
0047 
0048 #include "dcn10/dcn10_resource.h"
0049 
0050 #include "dce/dce_abm.h"
0051 #include "dce/dce_audio.h"
0052 #include "dce/dce_aux.h"
0053 #include "dce/dce_clock_source.h"
0054 #include "dce/dce_hwseq.h"
0055 #include "dce/dce_i2c_hw.h"
0056 #include "dce/dce_panel_cntl.h"
0057 #include "dce/dmub_abm.h"
0058 #include "dce/dmub_psr.h"
0059 #include "clk_mgr.h"
0060 
0061 #include "hw_sequencer_private.h"
0062 #include "reg_helper.h"
0063 #include "resource.h"
0064 #include "vm_helper.h"
0065 
0066 #include "dml/dcn302/dcn302_fpu.h"
0067 
0068 #include "dimgrey_cavefish_ip_offset.h"
0069 #include "dcn/dcn_3_0_2_offset.h"
0070 #include "dcn/dcn_3_0_2_sh_mask.h"
0071 #include "dpcs/dpcs_3_0_0_offset.h"
0072 #include "dpcs/dpcs_3_0_0_sh_mask.h"
0073 #include "nbio/nbio_7_4_offset.h"
0074 #include "amdgpu_socbb.h"
0075 
0076 #define DC_LOGGER_INIT(logger)
0077 
0078 static const struct dc_debug_options debug_defaults_drv = {
0079         .disable_dmcu = true,
0080         .force_abm_enable = false,
0081         .timing_trace = false,
0082         .clock_trace = true,
0083         .disable_pplib_clock_request = true,
0084         .pipe_split_policy = MPC_SPLIT_DYNAMIC,
0085         .force_single_disp_pipe_split = false,
0086         .disable_dcc = DCC_ENABLE,
0087         .vsr_support = true,
0088         .performance_trace = false,
0089         .max_downscale_src_width = 7680,/*upto 8K*/
0090         .disable_pplib_wm_range = false,
0091         .scl_reset_length10 = true,
0092         .sanity_checks = false,
0093         .underflow_assert_delay_us = 0xFFFFFFFF,
0094         .dwb_fi_phase = -1, // -1 = disable,
0095         .dmub_command_table = true,
0096         .use_max_lb = true
0097 };
0098 
0099 static const struct dc_debug_options debug_defaults_diags = {
0100         .disable_dmcu = true,
0101         .force_abm_enable = false,
0102         .timing_trace = true,
0103         .clock_trace = true,
0104         .disable_dpp_power_gate = true,
0105         .disable_hubp_power_gate = true,
0106         .disable_clock_gate = true,
0107         .disable_pplib_clock_request = true,
0108         .disable_pplib_wm_range = true,
0109         .disable_stutter = false,
0110         .scl_reset_length10 = true,
0111         .dwb_fi_phase = -1, // -1 = disable
0112         .dmub_command_table = true,
0113         .enable_tri_buf = true,
0114         .disable_psr = true,
0115         .use_max_lb = true
0116 };
0117 
0118 enum dcn302_clk_src_array_id {
0119     DCN302_CLK_SRC_PLL0,
0120     DCN302_CLK_SRC_PLL1,
0121     DCN302_CLK_SRC_PLL2,
0122     DCN302_CLK_SRC_PLL3,
0123     DCN302_CLK_SRC_PLL4,
0124     DCN302_CLK_SRC_TOTAL
0125 };
0126 
0127 static const struct resource_caps res_cap_dcn302 = {
0128         .num_timing_generator = 5,
0129         .num_opp = 5,
0130         .num_video_plane = 5,
0131         .num_audio = 5,
0132         .num_stream_encoder = 5,
0133         .num_dwb = 1,
0134         .num_ddc = 5,
0135         .num_vmid = 16,
0136         .num_mpc_3dlut = 2,
0137         .num_dsc = 5,
0138 };
0139 
0140 static const struct dc_plane_cap plane_cap = {
0141         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
0142         .blends_with_above = true,
0143         .blends_with_below = true,
0144         .per_pixel_alpha = true,
0145         .pixel_format_support = {
0146                 .argb8888 = true,
0147                 .nv12 = true,
0148                 .fp16 = true,
0149                 .p010 = true,
0150                 .ayuv = false,
0151         },
0152         .max_upscale_factor = {
0153                 .argb8888 = 16000,
0154                 .nv12 = 16000,
0155                 .fp16 = 16000
0156         },
0157         /* 6:1 downscaling ratio: 1000/6 = 166.666 */
0158         .max_downscale_factor = {
0159                 .argb8888 = 167,
0160                 .nv12 = 167,
0161                 .fp16 = 167
0162         },
0163         16,
0164         16
0165 };
0166 
0167 /* NBIO */
0168 #define NBIO_BASE_INNER(seg) \
0169         NBIO_BASE__INST0_SEG ## seg
0170 
0171 #define NBIO_BASE(seg) \
0172         NBIO_BASE_INNER(seg)
0173 
0174 #define NBIO_SR(reg_name)\
0175         .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
0176         mm ## reg_name
0177 
0178 /* DCN */
0179 #undef BASE_INNER
0180 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
0181 
0182 #define BASE(seg) BASE_INNER(seg)
0183 
0184 #define SR(reg_name)\
0185         .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
0186 
0187 #define SF(reg_name, field_name, post_fix)\
0188         .field_name = reg_name ## __ ## field_name ## post_fix
0189 
0190 #define SRI(reg_name, block, id)\
0191         .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name
0192 
0193 #define SRI2(reg_name, block, id)\
0194         .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
0195 
0196 #define SRII(reg_name, block, id)\
0197         .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0198         mm ## block ## id ## _ ## reg_name
0199 
0200 #define DCCG_SRII(reg_name, block, id)\
0201         .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0202         mm ## block ## id ## _ ## reg_name
0203 
0204 #define VUPDATE_SRII(reg_name, block, id)\
0205         .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
0206         mm ## reg_name ## _ ## block ## id
0207 
0208 #define SRII_DWB(reg_name, temp_name, block, id)\
0209         .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
0210         mm ## block ## id ## _ ## temp_name
0211 
0212 #define SRII_MPC_RMU(reg_name, block, id)\
0213         .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0214         mm ## block ## id ## _ ## reg_name
0215 
0216 static const struct dcn_hubbub_registers hubbub_reg = {
0217         HUBBUB_REG_LIST_DCN30(0)
0218 };
0219 
0220 static const struct dcn_hubbub_shift hubbub_shift = {
0221         HUBBUB_MASK_SH_LIST_DCN30(__SHIFT)
0222 };
0223 
0224 static const struct dcn_hubbub_mask hubbub_mask = {
0225         HUBBUB_MASK_SH_LIST_DCN30(_MASK)
0226 };
0227 
0228 #define vmid_regs(id)\
0229         [id] = { DCN20_VMID_REG_LIST(id) }
0230 
0231 static const struct dcn_vmid_registers vmid_regs[] = {
0232         vmid_regs(0),
0233         vmid_regs(1),
0234         vmid_regs(2),
0235         vmid_regs(3),
0236         vmid_regs(4),
0237         vmid_regs(5),
0238         vmid_regs(6),
0239         vmid_regs(7),
0240         vmid_regs(8),
0241         vmid_regs(9),
0242         vmid_regs(10),
0243         vmid_regs(11),
0244         vmid_regs(12),
0245         vmid_regs(13),
0246         vmid_regs(14),
0247         vmid_regs(15)
0248 };
0249 
0250 static const struct dcn20_vmid_shift vmid_shifts = {
0251         DCN20_VMID_MASK_SH_LIST(__SHIFT)
0252 };
0253 
0254 static const struct dcn20_vmid_mask vmid_masks = {
0255         DCN20_VMID_MASK_SH_LIST(_MASK)
0256 };
0257 
0258 static struct hubbub *dcn302_hubbub_create(struct dc_context *ctx)
0259 {
0260     int i;
0261 
0262     struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL);
0263 
0264     if (!hubbub3)
0265         return NULL;
0266 
0267     hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask);
0268 
0269     for (i = 0; i < res_cap_dcn302.num_vmid; i++) {
0270         struct dcn20_vmid *vmid = &hubbub3->vmid[i];
0271 
0272         vmid->ctx = ctx;
0273 
0274         vmid->regs = &vmid_regs[i];
0275         vmid->shifts = &vmid_shifts;
0276         vmid->masks = &vmid_masks;
0277     }
0278 
0279     return &hubbub3->base;
0280 }
0281 
0282 #define vpg_regs(id)\
0283         [id] = { VPG_DCN3_REG_LIST(id) }
0284 
0285 static const struct dcn30_vpg_registers vpg_regs[] = {
0286         vpg_regs(0),
0287         vpg_regs(1),
0288         vpg_regs(2),
0289         vpg_regs(3),
0290         vpg_regs(4),
0291         vpg_regs(5)
0292 };
0293 
0294 static const struct dcn30_vpg_shift vpg_shift = {
0295         DCN3_VPG_MASK_SH_LIST(__SHIFT)
0296 };
0297 
0298 static const struct dcn30_vpg_mask vpg_mask = {
0299         DCN3_VPG_MASK_SH_LIST(_MASK)
0300 };
0301 
0302 static struct vpg *dcn302_vpg_create(struct dc_context *ctx, uint32_t inst)
0303 {
0304     struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
0305 
0306     if (!vpg3)
0307         return NULL;
0308 
0309     vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask);
0310 
0311     return &vpg3->base;
0312 }
0313 
0314 #define afmt_regs(id)\
0315         [id] = { AFMT_DCN3_REG_LIST(id) }
0316 
0317 static const struct dcn30_afmt_registers afmt_regs[] = {
0318         afmt_regs(0),
0319         afmt_regs(1),
0320         afmt_regs(2),
0321         afmt_regs(3),
0322         afmt_regs(4),
0323         afmt_regs(5)
0324 };
0325 
0326 static const struct dcn30_afmt_shift afmt_shift = {
0327         DCN3_AFMT_MASK_SH_LIST(__SHIFT)
0328 };
0329 
0330 static const struct dcn30_afmt_mask afmt_mask = {
0331         DCN3_AFMT_MASK_SH_LIST(_MASK)
0332 };
0333 
0334 static struct afmt *dcn302_afmt_create(struct dc_context *ctx, uint32_t inst)
0335 {
0336     struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
0337 
0338     if (!afmt3)
0339         return NULL;
0340 
0341     afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask);
0342 
0343     return &afmt3->base;
0344 }
0345 
0346 #define audio_regs(id)\
0347         [id] = { AUD_COMMON_REG_LIST(id) }
0348 
0349 static const struct dce_audio_registers audio_regs[] = {
0350         audio_regs(0),
0351         audio_regs(1),
0352         audio_regs(2),
0353         audio_regs(3),
0354         audio_regs(4),
0355         audio_regs(5),
0356         audio_regs(6)
0357 };
0358 
0359 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
0360         SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
0361         SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
0362         AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
0363 
0364 static const struct dce_audio_shift audio_shift = {
0365         DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
0366 };
0367 
0368 static const struct dce_audio_mask audio_mask = {
0369         DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
0370 };
0371 
0372 static struct audio *dcn302_create_audio(struct dc_context *ctx, unsigned int inst)
0373 {
0374     return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask);
0375 }
0376 
0377 #define stream_enc_regs(id)\
0378         [id] = { SE_DCN3_REG_LIST(id) }
0379 
0380 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
0381         stream_enc_regs(0),
0382         stream_enc_regs(1),
0383         stream_enc_regs(2),
0384         stream_enc_regs(3),
0385         stream_enc_regs(4)
0386 };
0387 
0388 static const struct dcn10_stream_encoder_shift se_shift = {
0389         SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
0390 };
0391 
0392 static const struct dcn10_stream_encoder_mask se_mask = {
0393         SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
0394 };
0395 
0396 static struct stream_encoder *dcn302_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx)
0397 {
0398     struct dcn10_stream_encoder *enc1;
0399     struct vpg *vpg;
0400     struct afmt *afmt;
0401     int vpg_inst;
0402     int afmt_inst;
0403 
0404     /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
0405     if (eng_id <= ENGINE_ID_DIGE) {
0406         vpg_inst = eng_id;
0407         afmt_inst = eng_id;
0408     } else
0409         return NULL;
0410 
0411     enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
0412     vpg = dcn302_vpg_create(ctx, vpg_inst);
0413     afmt = dcn302_afmt_create(ctx, afmt_inst);
0414 
0415     if (!enc1 || !vpg || !afmt) {
0416         kfree(enc1);
0417         kfree(vpg);
0418         kfree(afmt);
0419         return NULL;
0420     }
0421 
0422     dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id],
0423             &se_shift, &se_mask);
0424 
0425     return &enc1->base;
0426 }
0427 
0428 #define clk_src_regs(index, pllid)\
0429         [index] = { CS_COMMON_REG_LIST_DCN3_02(index, pllid) }
0430 
0431 static const struct dce110_clk_src_regs clk_src_regs[] = {
0432         clk_src_regs(0, A),
0433         clk_src_regs(1, B),
0434         clk_src_regs(2, C),
0435         clk_src_regs(3, D),
0436         clk_src_regs(4, E)
0437 };
0438 
0439 static const struct dce110_clk_src_shift cs_shift = {
0440         CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
0441 };
0442 
0443 static const struct dce110_clk_src_mask cs_mask = {
0444         CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
0445 };
0446 
0447 static struct clock_source *dcn302_clock_source_create(struct dc_context *ctx, struct dc_bios *bios,
0448         enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src)
0449 {
0450     struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
0451 
0452     if (!clk_src)
0453         return NULL;
0454 
0455     if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) {
0456         clk_src->base.dp_clk_src = dp_clk_src;
0457         return &clk_src->base;
0458     }
0459 
0460     BREAK_TO_DEBUGGER();
0461     return NULL;
0462 }
0463 
0464 static const struct dce_hwseq_registers hwseq_reg = {
0465         HWSEQ_DCN302_REG_LIST()
0466 };
0467 
0468 static const struct dce_hwseq_shift hwseq_shift = {
0469         HWSEQ_DCN302_MASK_SH_LIST(__SHIFT)
0470 };
0471 
0472 static const struct dce_hwseq_mask hwseq_mask = {
0473         HWSEQ_DCN302_MASK_SH_LIST(_MASK)
0474 };
0475 
0476 static struct dce_hwseq *dcn302_hwseq_create(struct dc_context *ctx)
0477 {
0478     struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
0479 
0480     if (hws) {
0481         hws->ctx = ctx;
0482         hws->regs = &hwseq_reg;
0483         hws->shifts = &hwseq_shift;
0484         hws->masks = &hwseq_mask;
0485     }
0486     return hws;
0487 }
0488 
0489 #define hubp_regs(id)\
0490         [id] = { HUBP_REG_LIST_DCN30(id) }
0491 
0492 static const struct dcn_hubp2_registers hubp_regs[] = {
0493         hubp_regs(0),
0494         hubp_regs(1),
0495         hubp_regs(2),
0496         hubp_regs(3),
0497         hubp_regs(4)
0498 };
0499 
0500 static const struct dcn_hubp2_shift hubp_shift = {
0501         HUBP_MASK_SH_LIST_DCN30(__SHIFT)
0502 };
0503 
0504 static const struct dcn_hubp2_mask hubp_mask = {
0505         HUBP_MASK_SH_LIST_DCN30(_MASK)
0506 };
0507 
0508 static struct hubp *dcn302_hubp_create(struct dc_context *ctx, uint32_t inst)
0509 {
0510     struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
0511 
0512     if (!hubp2)
0513         return NULL;
0514 
0515     if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask))
0516         return &hubp2->base;
0517 
0518     BREAK_TO_DEBUGGER();
0519     kfree(hubp2);
0520     return NULL;
0521 }
0522 
0523 #define dpp_regs(id)\
0524         [id] = { DPP_REG_LIST_DCN30(id) }
0525 
0526 static const struct dcn3_dpp_registers dpp_regs[] = {
0527         dpp_regs(0),
0528         dpp_regs(1),
0529         dpp_regs(2),
0530         dpp_regs(3),
0531         dpp_regs(4)
0532 };
0533 
0534 static const struct dcn3_dpp_shift tf_shift = {
0535         DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
0536 };
0537 
0538 static const struct dcn3_dpp_mask tf_mask = {
0539         DPP_REG_LIST_SH_MASK_DCN30(_MASK)
0540 };
0541 
0542 static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst)
0543 {
0544     struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
0545 
0546     if (!dpp)
0547         return NULL;
0548 
0549     if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask))
0550         return &dpp->base;
0551 
0552     BREAK_TO_DEBUGGER();
0553     kfree(dpp);
0554     return NULL;
0555 }
0556 
0557 #define opp_regs(id)\
0558         [id] = { OPP_REG_LIST_DCN30(id) }
0559 
0560 static const struct dcn20_opp_registers opp_regs[] = {
0561         opp_regs(0),
0562         opp_regs(1),
0563         opp_regs(2),
0564         opp_regs(3),
0565         opp_regs(4)
0566 };
0567 
0568 static const struct dcn20_opp_shift opp_shift = {
0569         OPP_MASK_SH_LIST_DCN20(__SHIFT)
0570 };
0571 
0572 static const struct dcn20_opp_mask opp_mask = {
0573         OPP_MASK_SH_LIST_DCN20(_MASK)
0574 };
0575 
0576 static struct output_pixel_processor *dcn302_opp_create(struct dc_context *ctx, uint32_t inst)
0577 {
0578     struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
0579 
0580     if (!opp) {
0581         BREAK_TO_DEBUGGER();
0582         return NULL;
0583     }
0584 
0585     dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
0586     return &opp->base;
0587 }
0588 
0589 #define optc_regs(id)\
0590         [id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) }
0591 
0592 static const struct dcn_optc_registers optc_regs[] = {
0593         optc_regs(0),
0594         optc_regs(1),
0595         optc_regs(2),
0596         optc_regs(3),
0597         optc_regs(4)
0598 };
0599 
0600 static const struct dcn_optc_shift optc_shift = {
0601         OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
0602 };
0603 
0604 static const struct dcn_optc_mask optc_mask = {
0605         OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
0606 };
0607 
0608 static struct timing_generator *dcn302_timing_generator_create(struct dc_context *ctx, uint32_t instance)
0609 {
0610     struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL);
0611 
0612     if (!tgn10)
0613         return NULL;
0614 
0615     tgn10->base.inst = instance;
0616     tgn10->base.ctx = ctx;
0617 
0618     tgn10->tg_regs = &optc_regs[instance];
0619     tgn10->tg_shift = &optc_shift;
0620     tgn10->tg_mask = &optc_mask;
0621 
0622     dcn30_timing_generator_init(tgn10);
0623 
0624     return &tgn10->base;
0625 }
0626 
0627 static const struct dcn30_mpc_registers mpc_regs = {
0628         MPC_REG_LIST_DCN3_0(0),
0629         MPC_REG_LIST_DCN3_0(1),
0630         MPC_REG_LIST_DCN3_0(2),
0631         MPC_REG_LIST_DCN3_0(3),
0632         MPC_REG_LIST_DCN3_0(4),
0633         MPC_OUT_MUX_REG_LIST_DCN3_0(0),
0634         MPC_OUT_MUX_REG_LIST_DCN3_0(1),
0635         MPC_OUT_MUX_REG_LIST_DCN3_0(2),
0636         MPC_OUT_MUX_REG_LIST_DCN3_0(3),
0637         MPC_OUT_MUX_REG_LIST_DCN3_0(4),
0638         MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
0639         MPC_RMU_REG_LIST_DCN3AG(0),
0640         MPC_RMU_REG_LIST_DCN3AG(1),
0641         MPC_RMU_REG_LIST_DCN3AG(2),
0642         MPC_DWB_MUX_REG_LIST_DCN3_0(0),
0643 };
0644 
0645 static const struct dcn30_mpc_shift mpc_shift = {
0646         MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
0647 };
0648 
0649 static const struct dcn30_mpc_mask mpc_mask = {
0650         MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
0651 };
0652 
0653 static struct mpc *dcn302_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu)
0654 {
0655     struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL);
0656 
0657     if (!mpc30)
0658         return NULL;
0659 
0660     dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu);
0661 
0662     return &mpc30->base;
0663 }
0664 
0665 #define dsc_regsDCN20(id)\
0666 [id] = { DSC_REG_LIST_DCN20(id) }
0667 
0668 static const struct dcn20_dsc_registers dsc_regs[] = {
0669         dsc_regsDCN20(0),
0670         dsc_regsDCN20(1),
0671         dsc_regsDCN20(2),
0672         dsc_regsDCN20(3),
0673         dsc_regsDCN20(4)
0674 };
0675 
0676 static const struct dcn20_dsc_shift dsc_shift = {
0677         DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
0678 };
0679 
0680 static const struct dcn20_dsc_mask dsc_mask = {
0681         DSC_REG_LIST_SH_MASK_DCN20(_MASK)
0682 };
0683 
0684 static struct display_stream_compressor *dcn302_dsc_create(struct dc_context *ctx, uint32_t inst)
0685 {
0686     struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
0687 
0688     if (!dsc) {
0689         BREAK_TO_DEBUGGER();
0690         return NULL;
0691     }
0692 
0693     dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
0694     return &dsc->base;
0695 }
0696 
0697 #define dwbc_regs_dcn3(id)\
0698 [id] = { DWBC_COMMON_REG_LIST_DCN30(id) }
0699 
0700 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
0701         dwbc_regs_dcn3(0)
0702 };
0703 
0704 static const struct dcn30_dwbc_shift dwbc30_shift = {
0705         DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
0706 };
0707 
0708 static const struct dcn30_dwbc_mask dwbc30_mask = {
0709         DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
0710 };
0711 
0712 static bool dcn302_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
0713 {
0714     int i;
0715     uint32_t pipe_count = pool->res_cap->num_dwb;
0716 
0717     for (i = 0; i < pipe_count; i++) {
0718         struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL);
0719 
0720         if (!dwbc30) {
0721             dm_error("DC: failed to create dwbc30!\n");
0722             return false;
0723         }
0724 
0725         dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i);
0726 
0727         pool->dwbc[i] = &dwbc30->base;
0728     }
0729     return true;
0730 }
0731 
0732 #define mcif_wb_regs_dcn3(id)\
0733 [id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) }
0734 
0735 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
0736         mcif_wb_regs_dcn3(0)
0737 };
0738 
0739 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
0740         MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
0741 };
0742 
0743 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
0744         MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
0745 };
0746 
0747 static bool dcn302_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
0748 {
0749     int i;
0750     uint32_t pipe_count = pool->res_cap->num_dwb;
0751 
0752     for (i = 0; i < pipe_count; i++) {
0753         struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL);
0754 
0755         if (!mcif_wb30) {
0756             dm_error("DC: failed to create mcif_wb30!\n");
0757             return false;
0758         }
0759 
0760         dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i);
0761 
0762         pool->mcif_wb[i] = &mcif_wb30->base;
0763     }
0764     return true;
0765 }
0766 
0767 #define aux_engine_regs(id)\
0768 [id] = {\
0769         AUX_COMMON_REG_LIST0(id), \
0770         .AUXN_IMPCAL = 0, \
0771         .AUXP_IMPCAL = 0, \
0772         .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
0773 }
0774 
0775 static const struct dce110_aux_registers aux_engine_regs[] = {
0776         aux_engine_regs(0),
0777         aux_engine_regs(1),
0778         aux_engine_regs(2),
0779         aux_engine_regs(3),
0780         aux_engine_regs(4)
0781 };
0782 
0783 static const struct dce110_aux_registers_shift aux_shift = {
0784         DCN_AUX_MASK_SH_LIST(__SHIFT)
0785 };
0786 
0787 static const struct dce110_aux_registers_mask aux_mask = {
0788         DCN_AUX_MASK_SH_LIST(_MASK)
0789 };
0790 
0791 static struct dce_aux *dcn302_aux_engine_create(struct dc_context *ctx, uint32_t inst)
0792 {
0793     struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
0794 
0795     if (!aux_engine)
0796         return NULL;
0797 
0798     dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
0799             &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support);
0800 
0801     return &aux_engine->base;
0802 }
0803 
0804 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
0805 
0806 static const struct dce_i2c_registers i2c_hw_regs[] = {
0807         i2c_inst_regs(1),
0808         i2c_inst_regs(2),
0809         i2c_inst_regs(3),
0810         i2c_inst_regs(4),
0811         i2c_inst_regs(5)
0812 };
0813 
0814 static const struct dce_i2c_shift i2c_shifts = {
0815         I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
0816 };
0817 
0818 static const struct dce_i2c_mask i2c_masks = {
0819         I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
0820 };
0821 
0822 static struct dce_i2c_hw *dcn302_i2c_hw_create(struct dc_context *ctx, uint32_t inst)
0823 {
0824     struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
0825 
0826     if (!dce_i2c_hw)
0827         return NULL;
0828 
0829     dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
0830 
0831     return dce_i2c_hw;
0832 }
0833 
0834 static const struct encoder_feature_support link_enc_feature = {
0835         .max_hdmi_deep_color = COLOR_DEPTH_121212,
0836         .max_hdmi_pixel_clock = 600000,
0837         .hdmi_ycbcr420_supported = true,
0838         .dp_ycbcr420_supported = true,
0839         .fec_supported = true,
0840         .flags.bits.IS_HBR2_CAPABLE = true,
0841         .flags.bits.IS_HBR3_CAPABLE = true,
0842         .flags.bits.IS_TPS3_CAPABLE = true,
0843         .flags.bits.IS_TPS4_CAPABLE = true
0844 };
0845 
0846 #define link_regs(id, phyid)\
0847         [id] = {\
0848                 LE_DCN3_REG_LIST(id), \
0849                 UNIPHY_DCN2_REG_LIST(phyid), \
0850                 DPCS_DCN2_REG_LIST(id), \
0851                 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
0852         }
0853 
0854 static const struct dcn10_link_enc_registers link_enc_regs[] = {
0855         link_regs(0, A),
0856         link_regs(1, B),
0857         link_regs(2, C),
0858         link_regs(3, D),
0859         link_regs(4, E)
0860 };
0861 
0862 static const struct dcn10_link_enc_shift le_shift = {
0863         LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT),
0864         DPCS_DCN2_MASK_SH_LIST(__SHIFT)
0865 };
0866 
0867 static const struct dcn10_link_enc_mask le_mask = {
0868         LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),
0869         DPCS_DCN2_MASK_SH_LIST(_MASK)
0870 };
0871 
0872 #define aux_regs(id)\
0873         [id] = { DCN2_AUX_REG_LIST(id) }
0874 
0875 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
0876         aux_regs(0),
0877         aux_regs(1),
0878         aux_regs(2),
0879         aux_regs(3),
0880         aux_regs(4)
0881 };
0882 
0883 #define hpd_regs(id)\
0884         [id] = { HPD_REG_LIST(id) }
0885 
0886 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
0887         hpd_regs(0),
0888         hpd_regs(1),
0889         hpd_regs(2),
0890         hpd_regs(3),
0891         hpd_regs(4)
0892 };
0893 
0894 static struct link_encoder *dcn302_link_encoder_create(
0895     struct dc_context *ctx,
0896     const struct encoder_init_data *enc_init_data)
0897 {
0898     struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
0899 
0900     if (!enc20)
0901         return NULL;
0902 
0903     dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature,
0904             &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1],
0905             &link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask);
0906 
0907     return &enc20->enc10.base;
0908 }
0909 
0910 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
0911         { DCN_PANEL_CNTL_REG_LIST() }
0912 };
0913 
0914 static const struct dce_panel_cntl_shift panel_cntl_shift = {
0915         DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
0916 };
0917 
0918 static const struct dce_panel_cntl_mask panel_cntl_mask = {
0919         DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
0920 };
0921 
0922 static struct panel_cntl *dcn302_panel_cntl_create(const struct panel_cntl_init_data *init_data)
0923 {
0924     struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
0925 
0926     if (!panel_cntl)
0927         return NULL;
0928 
0929     dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst],
0930             &panel_cntl_shift, &panel_cntl_mask);
0931 
0932     return &panel_cntl->base;
0933 }
0934 
0935 static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps)
0936 {
0937     generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
0938             FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
0939 }
0940 
0941 static const struct resource_create_funcs res_create_funcs = {
0942         .read_dce_straps = read_dce_straps,
0943         .create_audio = dcn302_create_audio,
0944         .create_stream_encoder = dcn302_stream_encoder_create,
0945         .create_hwseq = dcn302_hwseq_create,
0946 };
0947 
0948 static const struct resource_create_funcs res_create_maximus_funcs = {
0949         .read_dce_straps = NULL,
0950         .create_audio = NULL,
0951         .create_stream_encoder = NULL,
0952         .create_hwseq = dcn302_hwseq_create,
0953 };
0954 
0955 static bool is_soc_bounding_box_valid(struct dc *dc)
0956 {
0957     uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
0958 
0959     if (ASICREV_IS_DIMGREY_CAVEFISH_P(hw_internal_rev))
0960         return true;
0961 
0962     return false;
0963 }
0964 
0965 static bool init_soc_bounding_box(struct dc *dc,  struct resource_pool *pool)
0966 {
0967     struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_02_soc;
0968     struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_02_ip;
0969 
0970     DC_LOGGER_INIT(dc->ctx->logger);
0971 
0972     if (!is_soc_bounding_box_valid(dc)) {
0973         DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__);
0974         return false;
0975     }
0976 
0977     loaded_ip->max_num_otg = pool->pipe_count;
0978     loaded_ip->max_num_dpp = pool->pipe_count;
0979     loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
0980     DC_FP_START();
0981     dcn20_patch_bounding_box(dc, loaded_bb);
0982     DC_FP_END();
0983 
0984     if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
0985         struct bp_soc_bb_info bb_info = { 0 };
0986 
0987         if (dc->ctx->dc_bios->funcs->get_soc_bb_info(
0988                 dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
0989 
0990                 DC_FP_START();
0991                 dcn302_fpu_init_soc_bounding_box(bb_info);
0992                 DC_FP_END();
0993         }
0994     }
0995 
0996     return true;
0997 }
0998 
0999 static void dcn302_resource_destruct(struct resource_pool *pool)
1000 {
1001     unsigned int i;
1002 
1003     for (i = 0; i < pool->stream_enc_count; i++) {
1004         if (pool->stream_enc[i] != NULL) {
1005             if (pool->stream_enc[i]->vpg != NULL) {
1006                 kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg));
1007                 pool->stream_enc[i]->vpg = NULL;
1008             }
1009             if (pool->stream_enc[i]->afmt != NULL) {
1010                 kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt));
1011                 pool->stream_enc[i]->afmt = NULL;
1012             }
1013             kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i]));
1014             pool->stream_enc[i] = NULL;
1015         }
1016     }
1017 
1018     for (i = 0; i < pool->res_cap->num_dsc; i++) {
1019         if (pool->dscs[i] != NULL)
1020             dcn20_dsc_destroy(&pool->dscs[i]);
1021     }
1022 
1023     if (pool->mpc != NULL) {
1024         kfree(TO_DCN20_MPC(pool->mpc));
1025         pool->mpc = NULL;
1026     }
1027 
1028     if (pool->hubbub != NULL) {
1029         kfree(pool->hubbub);
1030         pool->hubbub = NULL;
1031     }
1032 
1033     for (i = 0; i < pool->pipe_count; i++) {
1034         if (pool->dpps[i] != NULL) {
1035             kfree(TO_DCN20_DPP(pool->dpps[i]));
1036             pool->dpps[i] = NULL;
1037         }
1038 
1039         if (pool->hubps[i] != NULL) {
1040             kfree(TO_DCN20_HUBP(pool->hubps[i]));
1041             pool->hubps[i] = NULL;
1042         }
1043 
1044         if (pool->irqs != NULL)
1045             dal_irq_service_destroy(&pool->irqs);
1046     }
1047 
1048     for (i = 0; i < pool->res_cap->num_ddc; i++) {
1049         if (pool->engines[i] != NULL)
1050             dce110_engine_destroy(&pool->engines[i]);
1051         if (pool->hw_i2cs[i] != NULL) {
1052             kfree(pool->hw_i2cs[i]);
1053             pool->hw_i2cs[i] = NULL;
1054         }
1055         if (pool->sw_i2cs[i] != NULL) {
1056             kfree(pool->sw_i2cs[i]);
1057             pool->sw_i2cs[i] = NULL;
1058         }
1059     }
1060 
1061     for (i = 0; i < pool->res_cap->num_opp; i++) {
1062         if (pool->opps[i] != NULL)
1063             pool->opps[i]->funcs->opp_destroy(&pool->opps[i]);
1064     }
1065 
1066     for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1067         if (pool->timing_generators[i] != NULL) {
1068             kfree(DCN10TG_FROM_TG(pool->timing_generators[i]));
1069             pool->timing_generators[i] = NULL;
1070         }
1071     }
1072 
1073     for (i = 0; i < pool->res_cap->num_dwb; i++) {
1074         if (pool->dwbc[i] != NULL) {
1075             kfree(TO_DCN30_DWBC(pool->dwbc[i]));
1076             pool->dwbc[i] = NULL;
1077         }
1078         if (pool->mcif_wb[i] != NULL) {
1079             kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i]));
1080             pool->mcif_wb[i] = NULL;
1081         }
1082     }
1083 
1084     for (i = 0; i < pool->audio_count; i++) {
1085         if (pool->audios[i])
1086             dce_aud_destroy(&pool->audios[i]);
1087     }
1088 
1089     for (i = 0; i < pool->clk_src_count; i++) {
1090         if (pool->clock_sources[i] != NULL)
1091             dcn20_clock_source_destroy(&pool->clock_sources[i]);
1092     }
1093 
1094     if (pool->dp_clock_source != NULL)
1095         dcn20_clock_source_destroy(&pool->dp_clock_source);
1096 
1097     for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1098         if (pool->mpc_lut[i] != NULL) {
1099             dc_3dlut_func_release(pool->mpc_lut[i]);
1100             pool->mpc_lut[i] = NULL;
1101         }
1102         if (pool->mpc_shaper[i] != NULL) {
1103             dc_transfer_func_release(pool->mpc_shaper[i]);
1104             pool->mpc_shaper[i] = NULL;
1105         }
1106     }
1107 
1108     for (i = 0; i < pool->pipe_count; i++) {
1109         if (pool->multiple_abms[i] != NULL)
1110             dce_abm_destroy(&pool->multiple_abms[i]);
1111     }
1112 
1113     if (pool->psr != NULL)
1114         dmub_psr_destroy(&pool->psr);
1115 
1116     if (pool->dccg != NULL)
1117         dcn_dccg_destroy(&pool->dccg);
1118 }
1119 
1120 static void dcn302_destroy_resource_pool(struct resource_pool **pool)
1121 {
1122     dcn302_resource_destruct(*pool);
1123     kfree(*pool);
1124     *pool = NULL;
1125 }
1126 
1127 void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1128 {
1129     DC_FP_START();
1130     dcn302_fpu_update_bw_bounding_box(dc, bw_params);
1131     DC_FP_END();
1132 }
1133 
1134 static struct resource_funcs dcn302_res_pool_funcs = {
1135         .destroy = dcn302_destroy_resource_pool,
1136         .link_enc_create = dcn302_link_encoder_create,
1137         .panel_cntl_create = dcn302_panel_cntl_create,
1138         .validate_bandwidth = dcn30_validate_bandwidth,
1139         .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
1140         .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1141         .populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
1142         .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1143         .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1144         .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1145         .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1146         .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1147         .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1148         .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1149         .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1150         .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1151         .update_bw_bounding_box = dcn302_update_bw_bounding_box,
1152         .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1153 };
1154 
1155 static struct dc_cap_funcs cap_funcs = {
1156         .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1157 };
1158 
1159 static const struct bios_registers bios_regs = {
1160         NBIO_SR(BIOS_SCRATCH_3),
1161         NBIO_SR(BIOS_SCRATCH_6)
1162 };
1163 
1164 static const struct dccg_registers dccg_regs = {
1165         DCCG_REG_LIST_DCN3_02()
1166 };
1167 
1168 static const struct dccg_shift dccg_shift = {
1169         DCCG_MASK_SH_LIST_DCN3_02(__SHIFT)
1170 };
1171 
1172 static const struct dccg_mask dccg_mask = {
1173         DCCG_MASK_SH_LIST_DCN3_02(_MASK)
1174 };
1175 
1176 #define abm_regs(id)\
1177         [id] = { ABM_DCN302_REG_LIST(id) }
1178 
1179 static const struct dce_abm_registers abm_regs[] = {
1180         abm_regs(0),
1181         abm_regs(1),
1182         abm_regs(2),
1183         abm_regs(3),
1184         abm_regs(4)
1185 };
1186 
1187 static const struct dce_abm_shift abm_shift = {
1188         ABM_MASK_SH_LIST_DCN30(__SHIFT)
1189 };
1190 
1191 static const struct dce_abm_mask abm_mask = {
1192         ABM_MASK_SH_LIST_DCN30(_MASK)
1193 };
1194 
1195 static bool dcn302_resource_construct(
1196         uint8_t num_virtual_links,
1197         struct dc *dc,
1198         struct resource_pool *pool)
1199 {
1200     int i;
1201     struct dc_context *ctx = dc->ctx;
1202     struct irq_service_init_data init_data;
1203 
1204     ctx->dc_bios->regs = &bios_regs;
1205 
1206     pool->res_cap = &res_cap_dcn302;
1207 
1208     pool->funcs = &dcn302_res_pool_funcs;
1209 
1210     /*************************************************
1211      *  Resource + asic cap harcoding                *
1212      *************************************************/
1213     pool->underlay_pipe_index = NO_UNDERLAY_PIPE;
1214     pool->pipe_count = pool->res_cap->num_timing_generator;
1215     pool->mpcc_count = pool->res_cap->num_timing_generator;
1216     dc->caps.max_downscale_ratio = 600;
1217     dc->caps.i2c_speed_in_khz = 100;
1218     dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/
1219     dc->caps.max_cursor_size = 256;
1220     dc->caps.min_horizontal_blanking_period = 80;
1221     dc->caps.dmdata_alloc_size = 2048;
1222     dc->caps.mall_size_per_mem_channel = 4;
1223     /* total size = mall per channel * num channels * 1024 * 1024 */
1224     dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;
1225     dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
1226     dc->caps.max_slave_planes = 2;
1227     dc->caps.max_slave_yuv_planes = 2;
1228     dc->caps.max_slave_rgb_planes = 2;
1229     dc->caps.post_blend_color_processing = true;
1230     dc->caps.force_dp_tps4_for_cp2520 = true;
1231     dc->caps.extended_aux_timeout_support = true;
1232     dc->caps.dmcub_support = true;
1233 
1234     /* Color pipeline capabilities */
1235     dc->caps.color.dpp.dcn_arch = 1;
1236     dc->caps.color.dpp.input_lut_shared = 0;
1237     dc->caps.color.dpp.icsc = 1;
1238     dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1239     dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1240     dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1241     dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1242     dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1243     dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1244     dc->caps.color.dpp.post_csc = 1;
1245     dc->caps.color.dpp.gamma_corr = 1;
1246     dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1247 
1248     dc->caps.color.dpp.hw_3d_lut = 1;
1249     dc->caps.color.dpp.ogam_ram = 1;
1250     // no OGAM ROM on DCN3
1251     dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1252     dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1253     dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1254     dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1255     dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1256     dc->caps.color.dpp.ocsc = 0;
1257 
1258     dc->caps.color.mpc.gamut_remap = 1;
1259     dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3
1260     dc->caps.color.mpc.ogam_ram = 1;
1261     dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1262     dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1263     dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1264     dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1265     dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1266     dc->caps.color.mpc.ocsc = 1;
1267 
1268     /* read VBIOS LTTPR caps */
1269     if (ctx->dc_bios->funcs->get_lttpr_caps) {
1270         enum bp_result bp_query_result;
1271         uint8_t is_vbios_lttpr_enable = 0;
1272 
1273         bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1274         dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1275     }
1276 
1277     if (ctx->dc_bios->funcs->get_lttpr_interop) {
1278         enum bp_result bp_query_result;
1279         uint8_t is_vbios_interop_enabled = 0;
1280 
1281         bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios,
1282                 &is_vbios_interop_enabled);
1283         dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
1284     }
1285 
1286     if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1287         dc->debug = debug_defaults_drv;
1288     else
1289         dc->debug = debug_defaults_diags;
1290 
1291     // Init the vm_helper
1292     if (dc->vm_helper)
1293         vm_helper_init(dc->vm_helper, 16);
1294 
1295     /*************************************************
1296      *  Create resources                             *
1297      *************************************************/
1298 
1299     /* Clock Sources for Pixel Clock*/
1300     pool->clock_sources[DCN302_CLK_SRC_PLL0] =
1301             dcn302_clock_source_create(ctx, ctx->dc_bios,
1302                     CLOCK_SOURCE_COMBO_PHY_PLL0,
1303                     &clk_src_regs[0], false);
1304     pool->clock_sources[DCN302_CLK_SRC_PLL1] =
1305             dcn302_clock_source_create(ctx, ctx->dc_bios,
1306                     CLOCK_SOURCE_COMBO_PHY_PLL1,
1307                     &clk_src_regs[1], false);
1308     pool->clock_sources[DCN302_CLK_SRC_PLL2] =
1309             dcn302_clock_source_create(ctx, ctx->dc_bios,
1310                     CLOCK_SOURCE_COMBO_PHY_PLL2,
1311                     &clk_src_regs[2], false);
1312     pool->clock_sources[DCN302_CLK_SRC_PLL3] =
1313             dcn302_clock_source_create(ctx, ctx->dc_bios,
1314                     CLOCK_SOURCE_COMBO_PHY_PLL3,
1315                     &clk_src_regs[3], false);
1316     pool->clock_sources[DCN302_CLK_SRC_PLL4] =
1317             dcn302_clock_source_create(ctx, ctx->dc_bios,
1318                     CLOCK_SOURCE_COMBO_PHY_PLL4,
1319                     &clk_src_regs[4], false);
1320 
1321     pool->clk_src_count = DCN302_CLK_SRC_TOTAL;
1322 
1323     /* todo: not reuse phy_pll registers */
1324     pool->dp_clock_source =
1325             dcn302_clock_source_create(ctx, ctx->dc_bios,
1326                     CLOCK_SOURCE_ID_DP_DTO,
1327                     &clk_src_regs[0], true);
1328 
1329     for (i = 0; i < pool->clk_src_count; i++) {
1330         if (pool->clock_sources[i] == NULL) {
1331             dm_error("DC: failed to create clock sources!\n");
1332             BREAK_TO_DEBUGGER();
1333             goto create_fail;
1334         }
1335     }
1336 
1337     /* DCCG */
1338     pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1339     if (pool->dccg == NULL) {
1340         dm_error("DC: failed to create dccg!\n");
1341         BREAK_TO_DEBUGGER();
1342         goto create_fail;
1343     }
1344 
1345     /* PP Lib and SMU interfaces */
1346     init_soc_bounding_box(dc, pool);
1347 
1348     /* DML */
1349     dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30);
1350 
1351     /* IRQ */
1352     init_data.ctx = dc->ctx;
1353     pool->irqs = dal_irq_service_dcn302_create(&init_data);
1354     if (!pool->irqs)
1355         goto create_fail;
1356 
1357     /* HUBBUB */
1358     pool->hubbub = dcn302_hubbub_create(ctx);
1359     if (pool->hubbub == NULL) {
1360         BREAK_TO_DEBUGGER();
1361         dm_error("DC: failed to create hubbub!\n");
1362         goto create_fail;
1363     }
1364 
1365     /* HUBPs, DPPs, OPPs and TGs */
1366     for (i = 0; i < pool->pipe_count; i++) {
1367         pool->hubps[i] = dcn302_hubp_create(ctx, i);
1368         if (pool->hubps[i] == NULL) {
1369             BREAK_TO_DEBUGGER();
1370             dm_error("DC: failed to create hubps!\n");
1371             goto create_fail;
1372         }
1373 
1374         pool->dpps[i] = dcn302_dpp_create(ctx, i);
1375         if (pool->dpps[i] == NULL) {
1376             BREAK_TO_DEBUGGER();
1377             dm_error("DC: failed to create dpps!\n");
1378             goto create_fail;
1379         }
1380     }
1381 
1382     for (i = 0; i < pool->res_cap->num_opp; i++) {
1383         pool->opps[i] = dcn302_opp_create(ctx, i);
1384         if (pool->opps[i] == NULL) {
1385             BREAK_TO_DEBUGGER();
1386             dm_error("DC: failed to create output pixel processor!\n");
1387             goto create_fail;
1388         }
1389     }
1390 
1391     for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1392         pool->timing_generators[i] = dcn302_timing_generator_create(ctx, i);
1393         if (pool->timing_generators[i] == NULL) {
1394             BREAK_TO_DEBUGGER();
1395             dm_error("DC: failed to create tg!\n");
1396             goto create_fail;
1397         }
1398     }
1399     pool->timing_generator_count = i;
1400 
1401     /* PSR */
1402     pool->psr = dmub_psr_create(ctx);
1403     if (pool->psr == NULL) {
1404         dm_error("DC: failed to create psr!\n");
1405         BREAK_TO_DEBUGGER();
1406         goto create_fail;
1407     }
1408 
1409     /* ABMs */
1410     for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1411         pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask);
1412         if (pool->multiple_abms[i] == NULL) {
1413             dm_error("DC: failed to create abm for pipe %d!\n", i);
1414             BREAK_TO_DEBUGGER();
1415             goto create_fail;
1416         }
1417     }
1418 
1419     /* MPC and DSC */
1420     pool->mpc = dcn302_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut);
1421     if (pool->mpc == NULL) {
1422         BREAK_TO_DEBUGGER();
1423         dm_error("DC: failed to create mpc!\n");
1424         goto create_fail;
1425     }
1426 
1427     for (i = 0; i < pool->res_cap->num_dsc; i++) {
1428         pool->dscs[i] = dcn302_dsc_create(ctx, i);
1429         if (pool->dscs[i] == NULL) {
1430             BREAK_TO_DEBUGGER();
1431             dm_error("DC: failed to create display stream compressor %d!\n", i);
1432             goto create_fail;
1433         }
1434     }
1435 
1436     /* DWB and MMHUBBUB */
1437     if (!dcn302_dwbc_create(ctx, pool)) {
1438         BREAK_TO_DEBUGGER();
1439         dm_error("DC: failed to create dwbc!\n");
1440         goto create_fail;
1441     }
1442 
1443     if (!dcn302_mmhubbub_create(ctx, pool)) {
1444         BREAK_TO_DEBUGGER();
1445         dm_error("DC: failed to create mcif_wb!\n");
1446         goto create_fail;
1447     }
1448 
1449     /* AUX and I2C */
1450     for (i = 0; i < pool->res_cap->num_ddc; i++) {
1451         pool->engines[i] = dcn302_aux_engine_create(ctx, i);
1452         if (pool->engines[i] == NULL) {
1453             BREAK_TO_DEBUGGER();
1454             dm_error("DC:failed to create aux engine!!\n");
1455             goto create_fail;
1456         }
1457         pool->hw_i2cs[i] = dcn302_i2c_hw_create(ctx, i);
1458         if (pool->hw_i2cs[i] == NULL) {
1459             BREAK_TO_DEBUGGER();
1460             dm_error("DC:failed to create hw i2c!!\n");
1461             goto create_fail;
1462         }
1463         pool->sw_i2cs[i] = NULL;
1464     }
1465 
1466     /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
1467     if (!resource_construct(num_virtual_links, dc, pool,
1468             (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
1469                     &res_create_funcs : &res_create_maximus_funcs)))
1470         goto create_fail;
1471 
1472     /* HW Sequencer and Plane caps */
1473     dcn302_hw_sequencer_construct(dc);
1474 
1475     dc->caps.max_planes =  pool->pipe_count;
1476 
1477     for (i = 0; i < dc->caps.max_planes; ++i)
1478         dc->caps.planes[i] = plane_cap;
1479 
1480     dc->cap_funcs = cap_funcs;
1481 
1482     return true;
1483 
1484 create_fail:
1485 
1486     dcn302_resource_destruct(pool);
1487 
1488     return false;
1489 }
1490 
1491 struct resource_pool *dcn302_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc)
1492 {
1493     struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL);
1494 
1495     if (!pool)
1496         return NULL;
1497 
1498     if (dcn302_resource_construct(init_data->num_virtual_links, dc, pool))
1499         return pool;
1500 
1501     BREAK_TO_DEBUGGER();
1502     kfree(pool);
1503     return NULL;
1504 }
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