dc/dcn302/dcn302_hwseq.c

0001 /*
0002  * Copyright 2020 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include "dcn302_hwseq.h"
0027
0028 #include "dce/dce_hwseq.h"
0029
0030 #include "reg_helper.h"
0031 #include "dc.h"
0032
0033 #define DC_LOGGER_INIT(logger)
0034
0035 #define CTX \
0036     hws->ctx
0037 #define REG(reg)\
0038     hws->regs->reg
0039
0040 #undef FN
0041 #define FN(reg_name, field_name) \
0042     hws->shifts->field_name, hws->masks->field_name
0043
0044
0045 void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on)
0046 {
0047     uint32_t power_gate = power_on ? 0 : 1;
0048     uint32_t pwr_status = power_on ? 0 : 2;
0049
0050     if (hws->ctx->dc->debug.disable_dpp_power_gate)
0051         return;
0052     if (REG(DOMAIN1_PG_CONFIG) == 0)
0053         return;
0054
0055     switch (dpp_inst) {
0056     case 0: /* DPP0 */
0057         REG_UPDATE(DOMAIN1_PG_CONFIG,
0058                 DOMAIN1_POWER_GATE, power_gate);
0059
0060         REG_WAIT(DOMAIN1_PG_STATUS,
0061                 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
0062                 1, 1000);
0063         break;
0064     case 1: /* DPP1 */
0065         REG_UPDATE(DOMAIN3_PG_CONFIG,
0066                 DOMAIN3_POWER_GATE, power_gate);
0067
0068         REG_WAIT(DOMAIN3_PG_STATUS,
0069                 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
0070                 1, 1000);
0071         break;
0072     case 2: /* DPP2 */
0073         REG_UPDATE(DOMAIN5_PG_CONFIG,
0074                 DOMAIN5_POWER_GATE, power_gate);
0075
0076         REG_WAIT(DOMAIN5_PG_STATUS,
0077                 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
0078                 1, 1000);
0079         break;
0080     case 3: /* DPP3 */
0081         REG_UPDATE(DOMAIN7_PG_CONFIG,
0082                 DOMAIN7_POWER_GATE, power_gate);
0083
0084         REG_WAIT(DOMAIN7_PG_STATUS,
0085                 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
0086                 1, 1000);
0087         break;
0088     case 4: /* DPP4 */
0089         REG_UPDATE(DOMAIN9_PG_CONFIG,
0090                 DOMAIN9_POWER_GATE, power_gate);
0091
0092         REG_WAIT(DOMAIN9_PG_STATUS,
0093                 DOMAIN9_PGFSM_PWR_STATUS, pwr_status,
0094                 1, 1000);
0095         break;
0096     default:
0097         BREAK_TO_DEBUGGER();
0098         break;
0099     }
0100 }
0101
0102 void dcn302_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)
0103 {
0104     uint32_t power_gate = power_on ? 0 : 1;
0105     uint32_t pwr_status = power_on ? 0 : 2;
0106
0107     if (hws->ctx->dc->debug.disable_hubp_power_gate)
0108         return;
0109     if (REG(DOMAIN0_PG_CONFIG) == 0)
0110         return;
0111
0112     switch (hubp_inst) {
0113     case 0: /* DCHUBP0 */
0114         REG_UPDATE(DOMAIN0_PG_CONFIG,
0115                 DOMAIN0_POWER_GATE, power_gate);
0116
0117         REG_WAIT(DOMAIN0_PG_STATUS,
0118                 DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
0119                 1, 1000);
0120         break;
0121     case 1: /* DCHUBP1 */
0122         REG_UPDATE(DOMAIN2_PG_CONFIG,
0123                 DOMAIN2_POWER_GATE, power_gate);
0124
0125         REG_WAIT(DOMAIN2_PG_STATUS,
0126                 DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
0127                 1, 1000);
0128         break;
0129     case 2: /* DCHUBP2 */
0130         REG_UPDATE(DOMAIN4_PG_CONFIG,
0131                 DOMAIN4_POWER_GATE, power_gate);
0132
0133         REG_WAIT(DOMAIN4_PG_STATUS,
0134                 DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
0135                 1, 1000);
0136         break;
0137     case 3: /* DCHUBP3 */
0138         REG_UPDATE(DOMAIN6_PG_CONFIG,
0139                 DOMAIN6_POWER_GATE, power_gate);
0140
0141         REG_WAIT(DOMAIN6_PG_STATUS,
0142                 DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
0143                 1, 1000);
0144         break;
0145     case 4: /* DCHUBP4 */
0146         REG_UPDATE(DOMAIN8_PG_CONFIG,
0147                 DOMAIN8_POWER_GATE, power_gate);
0148
0149         REG_WAIT(DOMAIN8_PG_STATUS,
0150                 DOMAIN8_PGFSM_PWR_STATUS, pwr_status,
0151                 1, 1000);
0152         break;
0153     default:
0154         BREAK_TO_DEBUGGER();
0155         break;
0156     }
0157 }
0158
0159 void dcn302_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on)
0160 {
0161     uint32_t power_gate = power_on ? 0 : 1;
0162     uint32_t pwr_status = power_on ? 0 : 2;
0163     uint32_t org_ip_request_cntl = 0;
0164
0165     if (hws->ctx->dc->debug.disable_dsc_power_gate)
0166         return;
0167
0168     if (REG(DOMAIN16_PG_CONFIG) == 0)
0169         return;
0170
0171     REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
0172     if (org_ip_request_cntl == 0)
0173         REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
0174
0175     switch (dsc_inst) {
0176     case 0: /* DSC0 */
0177         REG_UPDATE(DOMAIN16_PG_CONFIG,
0178                 DOMAIN16_POWER_GATE, power_gate);
0179
0180         REG_WAIT(DOMAIN16_PG_STATUS,
0181                 DOMAIN16_PGFSM_PWR_STATUS, pwr_status,
0182                 1, 1000);
0183         break;
0184     case 1: /* DSC1 */
0185         REG_UPDATE(DOMAIN17_PG_CONFIG,
0186                 DOMAIN17_POWER_GATE, power_gate);
0187
0188         REG_WAIT(DOMAIN17_PG_STATUS,
0189                 DOMAIN17_PGFSM_PWR_STATUS, pwr_status,
0190                 1, 1000);
0191         break;
0192     case 2: /* DSC2 */
0193         REG_UPDATE(DOMAIN18_PG_CONFIG,
0194                 DOMAIN18_POWER_GATE, power_gate);
0195
0196         REG_WAIT(DOMAIN18_PG_STATUS,
0197                 DOMAIN18_PGFSM_PWR_STATUS, pwr_status,
0198                 1, 1000);
0199         break;
0200     case 3: /* DSC3 */
0201         REG_UPDATE(DOMAIN19_PG_CONFIG,
0202                 DOMAIN19_POWER_GATE, power_gate);
0203
0204         REG_WAIT(DOMAIN19_PG_STATUS,
0205                 DOMAIN19_PGFSM_PWR_STATUS, pwr_status,
0206                 1, 1000);
0207         break;
0208     case 4: /* DSC4 */
0209         REG_UPDATE(DOMAIN20_PG_CONFIG,
0210                 DOMAIN20_POWER_GATE, power_gate);
0211
0212         REG_WAIT(DOMAIN20_PG_STATUS,
0213                 DOMAIN20_PGFSM_PWR_STATUS, pwr_status,
0214                 1, 1000);
0215         break;
0216     default:
0217         BREAK_TO_DEBUGGER();
0218         break;
0219     }
0220
0221     if (org_ip_request_cntl == 0)
0222         REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
0223 }