dc/dcn301/dcn301_panel_cntl.h

0001 /*
0002  * Copyright 2020 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  *  and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef __DC_PANEL_CNTL__DCN301_H__
0027 #define __DC_PANEL_CNTL__DCN301_H__
0028
0029 #include "panel_cntl.h"
0030 #include "dce/dce_panel_cntl.h"
0031
0032
0033 #define DCN301_PANEL_CNTL_REG_LIST(id)\
0034     SRIR(PWRSEQ_CNTL, CNTL, PANEL_PWRSEQ, id), \
0035     SRIR(PWRSEQ_STATE, STATE, PANEL_PWRSEQ, id), \
0036     SRIR(PWRSEQ_REF_DIV, REF_DIV, PANEL_PWRSEQ, id), \
0037     SRIR(BL_PWM_CNTL, CNTL, BL_PWM, id), \
0038     SRIR(BL_PWM_CNTL2, CNTL2, BL_PWM, id), \
0039     SRIR(BL_PWM_PERIOD_CNTL, PERIOD_CNTL, BL_PWM, id), \
0040     SRIR(BL_PWM_GRP1_REG_LOCK, GRP1_REG_LOCK, BL_PWM, id)
0041
0042 #define DCN301_PANEL_CNTL_SF(reg_name, field_name, post_fix)\
0043     .field_name = reg_name ## __ ## field_name ## post_fix
0044
0045 #define DCN301_PANEL_CNTL_MASK_SH_LIST(mask_sh) \
0046     DCN301_PANEL_CNTL_SF(PANEL_PWRSEQ0_CNTL, PANEL_BLON, mask_sh),\
0047     DCN301_PANEL_CNTL_SF(PANEL_PWRSEQ0_CNTL, PANEL_DIGON, mask_sh),\
0048     DCN301_PANEL_CNTL_SF(PANEL_PWRSEQ0_CNTL, PANEL_DIGON_OVRD, mask_sh),\
0049     DCN301_PANEL_CNTL_SF(PANEL_PWRSEQ0_STATE, PANEL_PWRSEQ_TARGET_STATE_R, mask_sh), \
0050     DCN301_PANEL_CNTL_SF(PANEL_PWRSEQ0_REF_DIV, BL_PWM_REF_DIV, mask_sh), \
0051     DCN301_PANEL_CNTL_SF(BL_PWM0_PERIOD_CNTL, BL_PWM_PERIOD, mask_sh), \
0052     DCN301_PANEL_CNTL_SF(BL_PWM0_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, mask_sh), \
0053     DCN301_PANEL_CNTL_SF(BL_PWM0_CNTL, BL_ACTIVE_INT_FRAC_CNT, mask_sh), \
0054     DCN301_PANEL_CNTL_SF(BL_PWM0_CNTL, BL_PWM_FRACTIONAL_EN, mask_sh), \
0055     DCN301_PANEL_CNTL_SF(BL_PWM0_CNTL, BL_PWM_EN, mask_sh), \
0056     DCN301_PANEL_CNTL_SF(BL_PWM0_GRP1_REG_LOCK, BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, mask_sh), \
0057     DCN301_PANEL_CNTL_SF(BL_PWM0_GRP1_REG_LOCK, BL_PWM_GRP1_REG_LOCK, mask_sh), \
0058     DCN301_PANEL_CNTL_SF(BL_PWM0_GRP1_REG_LOCK, BL_PWM_GRP1_REG_UPDATE_PENDING, mask_sh)
0059
0060 #define DCN301_PANEL_CNTL_REG_FIELD_LIST(type) \
0061     type PANEL_BLON;\
0062     type PANEL_DIGON;\
0063     type PANEL_DIGON_OVRD;\
0064     type PANEL_PWRSEQ_TARGET_STATE_R; \
0065     type BL_PWM_EN; \
0066     type BL_ACTIVE_INT_FRAC_CNT; \
0067     type BL_PWM_FRACTIONAL_EN; \
0068     type BL_PWM_PERIOD; \
0069     type BL_PWM_PERIOD_BITCNT; \
0070     type BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN; \
0071     type BL_PWM_GRP1_REG_LOCK; \
0072     type BL_PWM_GRP1_REG_UPDATE_PENDING; \
0073     type BL_PWM_REF_DIV
0074
0075 struct dcn301_panel_cntl_shift {
0076     DCN301_PANEL_CNTL_REG_FIELD_LIST(uint8_t);
0077 };
0078
0079 struct dcn301_panel_cntl_mask {
0080     DCN301_PANEL_CNTL_REG_FIELD_LIST(uint32_t);
0081 };
0082
0083 struct dcn301_panel_cntl {
0084     struct panel_cntl base;
0085     const struct dce_panel_cntl_registers *regs;
0086     const struct dcn301_panel_cntl_shift *shift;
0087     const struct dcn301_panel_cntl_mask *mask;
0088 };
0089
0090 void dcn301_panel_cntl_construct(
0091     struct dcn301_panel_cntl *panel_cntl,
0092     const struct panel_cntl_init_data *init_data,
0093     const struct dce_panel_cntl_registers *regs,
0094     const struct dcn301_panel_cntl_shift *shift,
0095     const struct dcn301_panel_cntl_mask *mask);
0096
0097 #endif /* __DC_PANEL_CNTL__DCN301_H__ */