dc/dcn301/dcn301_dio_link_encoder.c

0001 /*
0002  * Copyright 2020 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include "reg_helper.h"
0027
0028 #include "core_types.h"
0029 #include "link_encoder.h"
0030 #include "dcn301_dio_link_encoder.h"
0031 #include "stream_encoder.h"
0032 #include "i2caux_interface.h"
0033 #include "dc_bios_types.h"
0034 #include "gpio_service_interface.h"
0035
0036 #define CTX \
0037     enc10->base.ctx
0038 #define DC_LOGGER \
0039     enc10->base.ctx->logger
0040
0041 #define REG(reg)\
0042     (enc10->link_regs->reg)
0043
0044 #undef FN
0045 #define FN(reg_name, field_name) \
0046     enc10->link_shift->field_name, enc10->link_mask->field_name
0047
0048 #define IND_REG(index) \
0049     (enc10->link_regs->index)
0050
0051 static const struct link_encoder_funcs dcn301_link_enc_funcs = {
0052     .read_state = link_enc2_read_state,
0053     .validate_output_with_stream = dcn10_link_encoder_validate_output_with_stream,
0054     .hw_init = enc3_hw_init,
0055     .setup = dcn10_link_encoder_setup,
0056     .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
0057     .enable_dp_output = dcn20_link_encoder_enable_dp_output,
0058     .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
0059     .disable_output = dcn10_link_encoder_disable_output,
0060     .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
0061     .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
0062     .update_mst_stream_allocation_table = dcn10_link_encoder_update_mst_stream_allocation_table,
0063     .psr_program_dp_dphy_fast_training = dcn10_psr_program_dp_dphy_fast_training,
0064     .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
0065     .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
0066     .enable_hpd = dcn10_link_encoder_enable_hpd,
0067     .disable_hpd = dcn10_link_encoder_disable_hpd,
0068     .is_dig_enabled = dcn10_is_dig_enabled,
0069     .destroy = dcn10_link_encoder_destroy,
0070     .fec_set_enable = enc2_fec_set_enable,
0071     .fec_set_ready = enc2_fec_set_ready,
0072     .fec_is_active = enc2_fec_is_active,
0073     .get_dig_frontend = dcn10_get_dig_frontend,
0074     .get_dig_mode = dcn10_get_dig_mode,
0075     .is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode,
0076     .get_max_link_cap = dcn20_link_encoder_get_max_link_cap,
0077 };
0078
0079 void dcn301_link_encoder_construct(
0080     struct dcn20_link_encoder *enc20,
0081     const struct encoder_init_data *init_data,
0082     const struct encoder_feature_support *enc_features,
0083     const struct dcn10_link_enc_registers *link_regs,
0084     const struct dcn10_link_enc_aux_registers *aux_regs,
0085     const struct dcn10_link_enc_hpd_registers *hpd_regs,
0086     const struct dcn10_link_enc_shift *link_shift,
0087     const struct dcn10_link_enc_mask *link_mask)
0088 {
0089     struct bp_encoder_cap_info bp_cap_info = {0};
0090     const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
0091     enum bp_result result = BP_RESULT_OK;
0092     struct dcn10_link_encoder *enc10 = &enc20->enc10;
0093
0094     enc10->base.funcs = &dcn301_link_enc_funcs;
0095     enc10->base.ctx = init_data->ctx;
0096     enc10->base.id = init_data->encoder;
0097
0098     enc10->base.hpd_source = init_data->hpd_source;
0099     enc10->base.connector = init_data->connector;
0100
0101     enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
0102
0103     enc10->base.features = *enc_features;
0104
0105     enc10->base.transmitter = init_data->transmitter;
0106
0107     /* set the flag to indicate whether driver poll the I2C data pin
0108      * while doing the DP sink detect
0109      */
0110
0111 /*  if (dal_adapter_service_is_feature_supported(as,
0112         FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
0113         enc10->base.features.flags.bits.
0114             DP_SINK_DETECT_POLL_DATA_PIN = true;*/
0115
0116     enc10->base.output_signals =
0117         SIGNAL_TYPE_DVI_SINGLE_LINK |
0118         SIGNAL_TYPE_DVI_DUAL_LINK |
0119         SIGNAL_TYPE_LVDS |
0120         SIGNAL_TYPE_DISPLAY_PORT |
0121         SIGNAL_TYPE_DISPLAY_PORT_MST |
0122         SIGNAL_TYPE_EDP |
0123         SIGNAL_TYPE_HDMI_TYPE_A;
0124
0125     /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
0126      * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
0127      * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
0128      * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
0129      * Prefer DIG assignment is decided by board design.
0130      * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
0131      * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
0132      * By this, adding DIGG should not hurt DCE 8.0.
0133      * This will let DCE 8.1 share DCE 8.0 as much as possible
0134      */
0135
0136     enc10->link_regs = link_regs;
0137     enc10->aux_regs = aux_regs;
0138     enc10->hpd_regs = hpd_regs;
0139     enc10->link_shift = link_shift;
0140     enc10->link_mask = link_mask;
0141
0142     switch (enc10->base.transmitter) {
0143     case TRANSMITTER_UNIPHY_A:
0144         enc10->base.preferred_engine = ENGINE_ID_DIGA;
0145     break;
0146     case TRANSMITTER_UNIPHY_B:
0147         enc10->base.preferred_engine = ENGINE_ID_DIGB;
0148     break;
0149     case TRANSMITTER_UNIPHY_C:
0150         enc10->base.preferred_engine = ENGINE_ID_DIGC;
0151     break;
0152     case TRANSMITTER_UNIPHY_D:
0153         enc10->base.preferred_engine = ENGINE_ID_DIGD;
0154     break;
0155     case TRANSMITTER_UNIPHY_E:
0156         enc10->base.preferred_engine = ENGINE_ID_DIGE;
0157     break;
0158     case TRANSMITTER_UNIPHY_F:
0159         enc10->base.preferred_engine = ENGINE_ID_DIGF;
0160     break;
0161     case TRANSMITTER_UNIPHY_G:
0162         enc10->base.preferred_engine = ENGINE_ID_DIGG;
0163     break;
0164     default:
0165         ASSERT_CRITICAL(false);
0166         enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
0167     }
0168
0169     /* default to one to mirror Windows behavior */
0170     enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
0171
0172     result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
0173                         enc10->base.id, &bp_cap_info);
0174
0175     /* Override features with DCE-specific values */
0176     if (result == BP_RESULT_OK) {
0177         enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
0178                 bp_cap_info.DP_HBR2_EN;
0179         enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
0180                 bp_cap_info.DP_HBR3_EN;
0181         enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
0182         enc10->base.features.flags.bits.DP_IS_USB_C =
0183                 bp_cap_info.DP_IS_USB_C;
0184     } else {
0185         DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
0186                 __func__,
0187                 result);
0188     }
0189     if (enc10->base.ctx->dc->debug.hdmi20_disable) {
0190         enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
0191     }
0192 }