dc/dcn301/dcn301_dccg.h

0001 /*
0002  * Copyright 2020 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef __DCN301_DCCG_H__
0027 #define __DCN301_DCCG_H__
0028
0029 #include "dcn20/dcn20_dccg.h"
0030
0031 #define DCCG_REG_LIST_DCN301() \
0032     SR(DPPCLK_DTO_CTRL),\
0033     DCCG_SRII(DTO_PARAM, DPPCLK, 0),\
0034     DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
0035     DCCG_SRII(DTO_PARAM, DPPCLK, 2),\
0036     DCCG_SRII(DTO_PARAM, DPPCLK, 3),\
0037     SR(REFCLK_CNTL)
0038
0039 #define DCCG_MASK_SH_LIST_DCN301(mask_sh) \
0040     DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\
0041     DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\
0042     DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 1, mask_sh),\
0043     DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\
0044     DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 2, mask_sh),\
0045     DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 2, mask_sh),\
0046     DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 3, mask_sh),\
0047     DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 3, mask_sh),\
0048     DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\
0049     DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\
0050     DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\
0051     DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh)
0052
0053 struct dccg *dccg301_create(
0054     struct dc_context *ctx,
0055     const struct dccg_registers *regs,
0056     const struct dccg_shift *dccg_shift,
0057     const struct dccg_mask *dccg_mask);
0058
0059 struct dccg *dccg301_create(
0060     struct dc_context *ctx,
0061     const struct dccg_registers *regs,
0062     const struct dccg_shift *dccg_shift,
0063     const struct dccg_mask *dccg_mask);
0064
0065 #endif //__DCN301_DCCG_H__