dc/dcn30/dcn30_vpg.c

0001 /*
0002  * Copyright 2020 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  *  and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026
0027 #include "dc_bios_types.h"
0028 #include "dcn30_vpg.h"
0029 #include "reg_helper.h"
0030
0031 #define DC_LOGGER \
0032         vpg3->base.ctx->logger
0033
0034 #define REG(reg)\
0035     (vpg3->regs->reg)
0036
0037 #undef FN
0038 #define FN(reg_name, field_name) \
0039     vpg3->vpg_shift->field_name, vpg3->vpg_mask->field_name
0040
0041
0042 #define CTX \
0043     vpg3->base.ctx
0044
0045
0046 void vpg3_update_generic_info_packet(
0047     struct vpg *vpg,
0048     uint32_t packet_index,
0049     const struct dc_info_packet *info_packet,
0050     bool immediate_update)
0051 {
0052     struct dcn30_vpg *vpg3 = DCN30_VPG_FROM_VPG(vpg);
0053     uint32_t i;
0054
0055     /* TODOFPGA Figure out a proper number for max_retries polling for lock
0056      * use 50 for now.
0057      */
0058     uint32_t max_retries = 50;
0059
0060     if (packet_index > 14)
0061         ASSERT(0);
0062
0063     /* poll dig_update_lock is not locked -> asic internal signal
0064      * assume otg master lock will unlock it
0065      */
0066     /* REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS,
0067      *      0, 10, max_retries);
0068      */
0069
0070     /* TODO: Check if this is required */
0071     /* check if HW reading GSP memory */
0072     REG_WAIT(VPG_GENERIC_STATUS, VPG_GENERIC_CONFLICT_OCCURED,
0073             0, 10, max_retries);
0074
0075     /* HW does is not reading GSP memory not reading too long ->
0076      * something wrong. clear GPS memory access and notify?
0077      * hw SW is writing to GSP memory
0078      */
0079     REG_UPDATE(VPG_GENERIC_STATUS, VPG_GENERIC_CONFLICT_CLR, 1);
0080
0081     /* choose which generic packet to use */
0082     REG_UPDATE(VPG_GENERIC_PACKET_ACCESS_CTRL,
0083             VPG_GENERIC_DATA_INDEX, packet_index*9);
0084
0085     /* write generic packet header
0086      * (4th byte is for GENERIC0 only)
0087      */
0088     REG_SET_4(VPG_GENERIC_PACKET_DATA, 0,
0089             VPG_GENERIC_DATA_BYTE0, info_packet->hb0,
0090             VPG_GENERIC_DATA_BYTE1, info_packet->hb1,
0091             VPG_GENERIC_DATA_BYTE2, info_packet->hb2,
0092             VPG_GENERIC_DATA_BYTE3, info_packet->hb3);
0093
0094     /* write generic packet contents
0095      * (we never use last 4 bytes)
0096      * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers
0097      */
0098     {
0099         const uint32_t *content =
0100             (const uint32_t *) &info_packet->sb[0];
0101
0102         for (i = 0; i < 8; i++) {
0103             REG_WRITE(VPG_GENERIC_PACKET_DATA, *content++);
0104         }
0105     }
0106
0107     /* atomically update double-buffered GENERIC0 registers in immediate mode
0108      * (update at next block_update when block_update_lock == 0).
0109      */
0110     if (immediate_update) {
0111         switch (packet_index) {
0112         case 0:
0113             REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
0114                     VPG_GENERIC0_IMMEDIATE_UPDATE, 1);
0115             break;
0116         case 1:
0117             REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
0118                     VPG_GENERIC1_IMMEDIATE_UPDATE, 1);
0119             break;
0120         case 2:
0121             REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
0122                     VPG_GENERIC2_IMMEDIATE_UPDATE, 1);
0123             break;
0124         case 3:
0125             REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
0126                     VPG_GENERIC3_IMMEDIATE_UPDATE, 1);
0127             break;
0128         case 4:
0129             REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
0130                     VPG_GENERIC4_IMMEDIATE_UPDATE, 1);
0131             break;
0132         case 5:
0133             REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
0134                     VPG_GENERIC5_IMMEDIATE_UPDATE, 1);
0135             break;
0136         case 6:
0137             REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
0138                     VPG_GENERIC6_IMMEDIATE_UPDATE, 1);
0139             break;
0140         case 7:
0141             REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
0142                     VPG_GENERIC7_IMMEDIATE_UPDATE, 1);
0143             break;
0144         case 8:
0145             REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
0146                     VPG_GENERIC8_IMMEDIATE_UPDATE, 1);
0147             break;
0148         case 9:
0149             REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
0150                     VPG_GENERIC9_IMMEDIATE_UPDATE, 1);
0151             break;
0152         case 10:
0153             REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
0154                     VPG_GENERIC10_IMMEDIATE_UPDATE, 1);
0155             break;
0156         case 11:
0157             REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
0158                     VPG_GENERIC11_IMMEDIATE_UPDATE, 1);
0159             break;
0160         case 12:
0161             REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
0162                     VPG_GENERIC12_IMMEDIATE_UPDATE, 1);
0163             break;
0164         case 13:
0165             REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
0166                     VPG_GENERIC13_IMMEDIATE_UPDATE, 1);
0167             break;
0168         case 14:
0169             REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
0170                     VPG_GENERIC14_IMMEDIATE_UPDATE, 1);
0171             break;
0172         default:
0173             break;
0174         }
0175     } else {
0176         switch (packet_index) {
0177         case 0:
0178             REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
0179                     VPG_GENERIC0_FRAME_UPDATE, 1);
0180             break;
0181         case 1:
0182             REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
0183                     VPG_GENERIC1_FRAME_UPDATE, 1);
0184             break;
0185         case 2:
0186             REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
0187                     VPG_GENERIC2_FRAME_UPDATE, 1);
0188             break;
0189         case 3:
0190             REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
0191                     VPG_GENERIC3_FRAME_UPDATE, 1);
0192             break;
0193         case 4:
0194             REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
0195                     VPG_GENERIC4_FRAME_UPDATE, 1);
0196             break;
0197         case 5:
0198             REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
0199                     VPG_GENERIC5_FRAME_UPDATE, 1);
0200             break;
0201         case 6:
0202             REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
0203                     VPG_GENERIC6_FRAME_UPDATE, 1);
0204             break;
0205         case 7:
0206             REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
0207                     VPG_GENERIC7_FRAME_UPDATE, 1);
0208             break;
0209         case 8:
0210             REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
0211                     VPG_GENERIC8_FRAME_UPDATE, 1);
0212             break;
0213         case 9:
0214             REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
0215                     VPG_GENERIC9_FRAME_UPDATE, 1);
0216             break;
0217         case 10:
0218             REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
0219                     VPG_GENERIC10_FRAME_UPDATE, 1);
0220             break;
0221         case 11:
0222             REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
0223                     VPG_GENERIC11_FRAME_UPDATE, 1);
0224             break;
0225         case 12:
0226             REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
0227                     VPG_GENERIC12_FRAME_UPDATE, 1);
0228             break;
0229         case 13:
0230             REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
0231                     VPG_GENERIC13_FRAME_UPDATE, 1);
0232             break;
0233         case 14:
0234             REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
0235                     VPG_GENERIC14_FRAME_UPDATE, 1);
0236             break;
0237
0238         default:
0239             break;
0240         }
0241
0242     }
0243 }
0244
0245 static struct vpg_funcs dcn30_vpg_funcs = {
0246     .update_generic_info_packet = vpg3_update_generic_info_packet,
0247 };
0248
0249 void vpg3_construct(struct dcn30_vpg *vpg3,
0250     struct dc_context *ctx,
0251     uint32_t inst,
0252     const struct dcn30_vpg_registers *vpg_regs,
0253     const struct dcn30_vpg_shift *vpg_shift,
0254     const struct dcn30_vpg_mask *vpg_mask)
0255 {
0256     vpg3->base.ctx = ctx;
0257
0258     vpg3->base.inst = inst;
0259     vpg3->base.funcs = &dcn30_vpg_funcs;
0260
0261     vpg3->regs = vpg_regs;
0262     vpg3->vpg_shift = vpg_shift;
0263     vpg3->vpg_mask = vpg_mask;
0264 }