dc/dcn30/dcn30_optc.c

0001 /*
0002  * Copyright 2020 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include "reg_helper.h"
0027 #include "dcn30_optc.h"
0028 #include "dc.h"
0029 #include "dcn_calc_math.h"
0030 #include "dc_dmub_srv.h"
0031
0032 #include "dml/dcn30/dcn30_fpu.h"
0033
0034 #define REG(reg)\
0035     optc1->tg_regs->reg
0036
0037 #define CTX \
0038     optc1->base.ctx
0039
0040 #undef FN
0041 #define FN(reg_name, field_name) \
0042     optc1->tg_shift->field_name, optc1->tg_mask->field_name
0043
0044 void optc3_triplebuffer_lock(struct timing_generator *optc)
0045 {
0046     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0047
0048     REG_UPDATE(OTG_GLOBAL_CONTROL2,
0049         OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
0050
0051     REG_SET(OTG_VUPDATE_KEEPOUT, 0,
0052         OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1);
0053
0054     REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
0055         OTG_MASTER_UPDATE_LOCK, 1);
0056
0057     if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
0058         REG_WAIT(OTG_MASTER_UPDATE_LOCK,
0059                 UPDATE_LOCK_STATUS, 1,
0060                 1, 10);
0061 }
0062
0063 void optc3_lock_doublebuffer_enable(struct timing_generator *optc)
0064 {
0065     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0066     uint32_t v_blank_start = 0;
0067     uint32_t v_blank_end = 0;
0068     uint32_t h_blank_start = 0;
0069     uint32_t h_blank_end = 0;
0070
0071     REG_GET_2(OTG_V_BLANK_START_END,
0072         OTG_V_BLANK_START, &v_blank_start,
0073         OTG_V_BLANK_END, &v_blank_end);
0074     REG_GET_2(OTG_H_BLANK_START_END,
0075         OTG_H_BLANK_START, &h_blank_start,
0076         OTG_H_BLANK_END, &h_blank_end);
0077
0078     REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
0079         MASTER_UPDATE_LOCK_DB_START_Y, v_blank_start - 1,
0080         MASTER_UPDATE_LOCK_DB_END_Y, v_blank_start);
0081     REG_UPDATE_2(OTG_GLOBAL_CONTROL4,
0082         DIG_UPDATE_POSITION_X, h_blank_start - 180 - 1,
0083         DIG_UPDATE_POSITION_Y, v_blank_start - 1);
0084     // there is a DIG_UPDATE_VCOUNT_MODE and it is 0.
0085
0086     REG_UPDATE_3(OTG_GLOBAL_CONTROL0,
0087         MASTER_UPDATE_LOCK_DB_START_X, h_blank_start - 200 - 1,
0088         MASTER_UPDATE_LOCK_DB_END_X, h_blank_start - 180,
0089         MASTER_UPDATE_LOCK_DB_EN, 1);
0090     REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1);
0091
0092     REG_SET_3(OTG_VUPDATE_KEEPOUT, 0,
0093         MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, 0,
0094         MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, 100,
0095         OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1);
0096 }
0097
0098 void optc3_lock_doublebuffer_disable(struct timing_generator *optc)
0099 {
0100     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0101
0102     REG_UPDATE_2(OTG_GLOBAL_CONTROL0,
0103         MASTER_UPDATE_LOCK_DB_START_X, 0,
0104         MASTER_UPDATE_LOCK_DB_END_X, 0);
0105     REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
0106         MASTER_UPDATE_LOCK_DB_START_Y, 0,
0107         MASTER_UPDATE_LOCK_DB_END_Y, 0);
0108
0109     REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0);
0110     REG_UPDATE(OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, 0);
0111 }
0112
0113 void optc3_lock(struct timing_generator *optc)
0114 {
0115     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0116
0117     REG_UPDATE(OTG_GLOBAL_CONTROL2,
0118         OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
0119     REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
0120         OTG_MASTER_UPDATE_LOCK, 1);
0121
0122     REG_WAIT(OTG_MASTER_UPDATE_LOCK,
0123             UPDATE_LOCK_STATUS, 1,
0124             1, 10);
0125 }
0126
0127 void optc3_set_out_mux(struct timing_generator *optc, enum otg_out_mux_dest dest)
0128 {
0129     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0130
0131     REG_UPDATE(OTG_CONTROL, OTG_OUT_MUX, dest);
0132 }
0133
0134 void optc3_program_blank_color(struct timing_generator *optc,
0135         const struct tg_color *blank_color)
0136 {
0137     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0138
0139     REG_SET_3(OTG_BLANK_DATA_COLOR, 0,
0140         OTG_BLANK_DATA_COLOR_BLUE_CB, blank_color->color_b_cb,
0141         OTG_BLANK_DATA_COLOR_GREEN_Y, blank_color->color_g_y,
0142         OTG_BLANK_DATA_COLOR_RED_CR, blank_color->color_r_cr);
0143
0144     REG_SET_3(OTG_BLANK_DATA_COLOR_EXT, 0,
0145         OTG_BLANK_DATA_COLOR_BLUE_CB_EXT, blank_color->color_b_cb >> 10,
0146         OTG_BLANK_DATA_COLOR_GREEN_Y_EXT, blank_color->color_g_y >> 10,
0147         OTG_BLANK_DATA_COLOR_RED_CR_EXT, blank_color->color_r_cr >> 10);
0148 }
0149
0150 void optc3_set_drr_trigger_window(struct timing_generator *optc,
0151         uint32_t window_start, uint32_t window_end)
0152 {
0153     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0154
0155     REG_SET_2(OTG_DRR_TRIGGER_WINDOW, 0,
0156         OTG_DRR_TRIGGER_WINDOW_START_X, window_start,
0157         OTG_DRR_TRIGGER_WINDOW_END_X, window_end);
0158 }
0159
0160 void optc3_set_vtotal_change_limit(struct timing_generator *optc,
0161         uint32_t limit)
0162 {
0163     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0164
0165
0166     REG_SET(OTG_DRR_V_TOTAL_CHANGE, 0,
0167         OTG_DRR_V_TOTAL_CHANGE_LIMIT, limit);
0168 }
0169
0170
0171 /* Set DSC-related configuration.
0172  *   dsc_mode: 0 disables DSC, other values enable DSC in specified format
0173  *   sc_bytes_per_pixel: Bytes per pixel in u3.28 format
0174  *   dsc_slice_width: Slice width in pixels
0175  */
0176 void optc3_set_dsc_config(struct timing_generator *optc,
0177         enum optc_dsc_mode dsc_mode,
0178         uint32_t dsc_bytes_per_pixel,
0179         uint32_t dsc_slice_width)
0180 {
0181     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0182
0183     optc2_set_dsc_config(optc, dsc_mode, dsc_bytes_per_pixel, dsc_slice_width);
0184     REG_UPDATE(OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, 0);
0185 }
0186
0187 void optc3_set_odm_bypass(struct timing_generator *optc,
0188         const struct dc_crtc_timing *dc_crtc_timing)
0189 {
0190     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0191     enum h_timing_div_mode h_div = H_TIMING_NO_DIV;
0192
0193     REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
0194             OPTC_NUM_OF_INPUT_SEGMENT, 0,
0195             OPTC_SEG0_SRC_SEL, optc->inst,
0196             OPTC_SEG1_SRC_SEL, 0xf,
0197             OPTC_SEG2_SRC_SEL, 0xf,
0198             OPTC_SEG3_SRC_SEL, 0xf
0199             );
0200
0201     h_div = optc1_is_two_pixels_per_containter(dc_crtc_timing);
0202     REG_SET(OTG_H_TIMING_CNTL, 0,
0203             OTG_H_TIMING_DIV_MODE, h_div);
0204
0205     REG_SET(OPTC_MEMORY_CONFIG, 0,
0206             OPTC_MEM_SEL, 0);
0207     optc1->opp_count = 1;
0208 }
0209
0210 static void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
0211         struct dc_crtc_timing *timing)
0212 {
0213     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0214     int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right)
0215             / opp_cnt;
0216     uint32_t memory_mask = 0;
0217
0218     /* TODO: In pseudocode but does not affect maximus, delete comment if we dont need on asic
0219      * REG_SET(OTG_GLOBAL_CONTROL2, 0, GLOBAL_UPDATE_LOCK_EN, 1);
0220      * Program OTG register MASTER_UPDATE_LOCK_DB_X/Y to the position before DP frame start
0221      * REG_SET_2(OTG_GLOBAL_CONTROL1, 0,
0222      *      MASTER_UPDATE_LOCK_DB_X, 160,
0223      *      MASTER_UPDATE_LOCK_DB_Y, 240);
0224      */
0225
0226     ASSERT(opp_cnt == 2 || opp_cnt == 4);
0227
0228     /* 2 pieces of memory required for up to 5120 displays, 4 for up to 8192,
0229      * however, for ODM combine we can simplify by always using 4.
0230      */
0231     if (opp_cnt == 2) {
0232         /* To make sure there's no memory overlap, each instance "reserves" 2
0233          * memories and they are uniquely combined here.
0234          */
0235         memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
0236     } else if (opp_cnt == 4) {
0237         /* To make sure there's no memory overlap, each instance "reserves" 1
0238          * memory and they are uniquely combined here.
0239          */
0240         memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2) | 0x1 << (opp_id[2] * 2) | 0x1 << (opp_id[3] * 2);
0241     }
0242
0243     if (REG(OPTC_MEMORY_CONFIG))
0244         REG_SET(OPTC_MEMORY_CONFIG, 0,
0245             OPTC_MEM_SEL, memory_mask);
0246
0247     if (opp_cnt == 2) {
0248         REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
0249                 OPTC_NUM_OF_INPUT_SEGMENT, 1,
0250                 OPTC_SEG0_SRC_SEL, opp_id[0],
0251                 OPTC_SEG1_SRC_SEL, opp_id[1]);
0252     } else if (opp_cnt == 4) {
0253         REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
0254                 OPTC_NUM_OF_INPUT_SEGMENT, 3,
0255                 OPTC_SEG0_SRC_SEL, opp_id[0],
0256                 OPTC_SEG1_SRC_SEL, opp_id[1],
0257                 OPTC_SEG2_SRC_SEL, opp_id[2],
0258                 OPTC_SEG3_SRC_SEL, opp_id[3]);
0259     }
0260
0261     REG_UPDATE(OPTC_WIDTH_CONTROL,
0262             OPTC_SEGMENT_WIDTH, mpcc_hactive);
0263
0264     REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
0265     optc1->opp_count = opp_cnt;
0266 }
0267
0268 /**
0269  * optc3_set_timing_double_buffer() - DRR double buffering control
0270  *
0271  * Sets double buffer point for V_TOTAL, H_TOTAL, VTOTAL_MIN,
0272  * VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers.
0273  *
0274  * Options: any time,  start of frame, dp start of frame (range timing)
0275  */
0276 static void optc3_set_timing_double_buffer(struct timing_generator *optc, bool enable)
0277 {
0278     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0279     uint32_t mode = enable ? 2 : 0;
0280
0281     REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
0282            OTG_DRR_TIMING_DBUF_UPDATE_MODE, mode);
0283 }
0284
0285 void optc3_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max)
0286 {
0287     optc1_set_vtotal_min_max(optc, vtotal_min, vtotal_max);
0288 }
0289
0290 void optc3_tg_init(struct timing_generator *optc)
0291 {
0292     optc3_set_timing_double_buffer(optc, true);
0293     optc1_clear_optc_underflow(optc);
0294 }
0295
0296 static struct timing_generator_funcs dcn30_tg_funcs = {
0297         .validate_timing = optc1_validate_timing,
0298         .program_timing = optc1_program_timing,
0299         .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
0300         .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
0301         .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
0302         .program_global_sync = optc1_program_global_sync,
0303         .enable_crtc = optc2_enable_crtc,
0304         .disable_crtc = optc1_disable_crtc,
0305         /* used by enable_timing_synchronization. Not need for FPGA */
0306         .is_counter_moving = optc1_is_counter_moving,
0307         .get_position = optc1_get_position,
0308         .get_frame_count = optc1_get_vblank_counter,
0309         .get_scanoutpos = optc1_get_crtc_scanoutpos,
0310         .get_otg_active_size = optc1_get_otg_active_size,
0311         .set_early_control = optc1_set_early_control,
0312         /* used by enable_timing_synchronization. Not need for FPGA */
0313         .wait_for_state = optc1_wait_for_state,
0314         .set_blank_color = optc3_program_blank_color,
0315         .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
0316         .triplebuffer_lock = optc3_triplebuffer_lock,
0317         .triplebuffer_unlock = optc2_triplebuffer_unlock,
0318         .enable_reset_trigger = optc1_enable_reset_trigger,
0319         .enable_crtc_reset = optc1_enable_crtc_reset,
0320         .disable_reset_trigger = optc1_disable_reset_trigger,
0321         .lock = optc3_lock,
0322         .is_locked = optc1_is_locked,
0323         .unlock = optc1_unlock,
0324         .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
0325         .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
0326         .enable_optc_clock = optc1_enable_optc_clock,
0327         .set_drr = optc1_set_drr,
0328         .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
0329         .set_static_screen_control = optc1_set_static_screen_control,
0330         .program_stereo = optc1_program_stereo,
0331         .is_stereo_left_eye = optc1_is_stereo_left_eye,
0332         .tg_init = optc3_tg_init,
0333         .is_tg_enabled = optc1_is_tg_enabled,
0334         .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
0335         .clear_optc_underflow = optc1_clear_optc_underflow,
0336         .setup_global_swap_lock = NULL,
0337         .get_crc = optc1_get_crc,
0338         .configure_crc = optc2_configure_crc,
0339         .set_dsc_config = optc3_set_dsc_config,
0340         .get_dsc_status = optc2_get_dsc_status,
0341         .set_dwb_source = NULL,
0342         .set_odm_bypass = optc3_set_odm_bypass,
0343         .set_odm_combine = optc3_set_odm_combine,
0344         .get_optc_source = optc2_get_optc_source,
0345         .set_out_mux = optc3_set_out_mux,
0346         .set_drr_trigger_window = optc3_set_drr_trigger_window,
0347         .set_vtotal_change_limit = optc3_set_vtotal_change_limit,
0348         .set_gsl = optc2_set_gsl,
0349         .set_gsl_source_select = optc2_set_gsl_source_select,
0350         .set_vtg_params = optc1_set_vtg_params,
0351         .program_manual_trigger = optc2_program_manual_trigger,
0352         .setup_manual_trigger = optc2_setup_manual_trigger,
0353         .get_hw_timing = optc1_get_hw_timing,
0354 };
0355
0356 void dcn30_timing_generator_init(struct optc *optc1)
0357 {
0358     optc1->base.funcs = &dcn30_tg_funcs;
0359
0360     optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
0361     optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
0362
0363     optc1->min_h_blank = 32;
0364     optc1->min_v_blank = 3;
0365     optc1->min_v_blank_interlace = 5;
0366     optc1->min_h_sync_width = 4;
0367     optc1->min_v_sync_width = 1;
0368 }
0369