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0001 /* Copyright 2020 Advanced Micro Devices, Inc.
0002  *
0003  * Permission is hereby granted, free of charge, to any person obtaining a
0004  * copy of this software and associated documentation files (the "Software"),
0005  * to deal in the Software without restriction, including without limitation
0006  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0007  * and/or sell copies of the Software, and to permit persons to whom the
0008  * Software is furnished to do so, subject to the following conditions:
0009  *
0010  * The above copyright notice and this permission notice shall be included in
0011  * all copies or substantial portions of the Software.
0012  *
0013  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0014  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0015  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0016  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0017  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0018  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0019  * OTHER DEALINGS IN THE SOFTWARE.
0020  *
0021  * Authors: AMD
0022  *
0023  */
0024 
0025 #ifndef __DC_MPCC_DCN30_H__
0026 #define __DC_MPCC_DCN30_H__
0027 
0028 #include "dcn20/dcn20_mpc.h"
0029 
0030 #define MAX_RMU 3
0031 
0032 #define TO_DCN30_MPC(mpc_base) \
0033     container_of(mpc_base, struct dcn30_mpc, base)
0034 
0035 #ifdef SRII_MPC_RMU
0036 #undef SRII_MPC_RMU
0037 
0038 #define SRII_MPC_RMU(reg_name, block, id)\
0039     .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0040                     mm ## block ## id ## _ ## reg_name
0041 
0042 #endif
0043 
0044 
0045 #define MPC_REG_LIST_DCN3_0(inst)\
0046     MPC_COMMON_REG_LIST_DCN1_0(inst),\
0047     SRII(MPCC_TOP_GAIN, MPCC, inst),\
0048     SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\
0049     SRII(MPCC_BOT_GAIN_OUTSIDE, MPCC, inst),\
0050     SRII(MPCC_MEM_PWR_CTRL, MPCC, inst),\
0051     SRII(MPCC_OGAM_LUT_INDEX, MPCC_OGAM, inst),\
0052     SRII(MPCC_OGAM_LUT_DATA, MPCC_OGAM, inst), \
0053     SRII(MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_OGAM, inst),\
0054     SRII(MPCC_GAMUT_REMAP_MODE, MPCC_OGAM, inst),\
0055     SRII(MPC_GAMUT_REMAP_C11_C12_A, MPCC_OGAM, inst),\
0056     SRII(MPC_GAMUT_REMAP_C33_C34_A, MPCC_OGAM, inst),\
0057     SRII(MPC_GAMUT_REMAP_C11_C12_B, MPCC_OGAM, inst),\
0058     SRII(MPC_GAMUT_REMAP_C33_C34_B, MPCC_OGAM, inst),\
0059     SRII(MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM, inst),\
0060     SRII(MPCC_OGAM_RAMA_START_CNTL_G, MPCC_OGAM, inst),\
0061     SRII(MPCC_OGAM_RAMA_START_CNTL_R, MPCC_OGAM, inst),\
0062     SRII(MPCC_OGAM_RAMA_START_SLOPE_CNTL_B, MPCC_OGAM, inst),\
0063     SRII(MPCC_OGAM_RAMA_START_SLOPE_CNTL_G, MPCC_OGAM, inst),\
0064     SRII(MPCC_OGAM_RAMA_START_SLOPE_CNTL_R, MPCC_OGAM, inst),\
0065     SRII(MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM, inst),\
0066     SRII(MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM, inst),\
0067     SRII(MPCC_OGAM_RAMA_END_CNTL1_G, MPCC_OGAM, inst),\
0068     SRII(MPCC_OGAM_RAMA_END_CNTL2_G, MPCC_OGAM, inst),\
0069     SRII(MPCC_OGAM_RAMA_END_CNTL1_R, MPCC_OGAM, inst),\
0070     SRII(MPCC_OGAM_RAMA_END_CNTL2_R, MPCC_OGAM, inst),\
0071     SRII(MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM, inst),\
0072     SRII(MPCC_OGAM_RAMA_REGION_32_33, MPCC_OGAM, inst),\
0073     SRII(MPCC_OGAM_RAMA_OFFSET_B, MPCC_OGAM, inst),\
0074     SRII(MPCC_OGAM_RAMA_OFFSET_G, MPCC_OGAM, inst),\
0075     SRII(MPCC_OGAM_RAMA_OFFSET_R, MPCC_OGAM, inst),\
0076     SRII(MPCC_OGAM_RAMA_START_BASE_CNTL_B, MPCC_OGAM, inst),\
0077     SRII(MPCC_OGAM_RAMA_START_BASE_CNTL_G, MPCC_OGAM, inst),\
0078     SRII(MPCC_OGAM_RAMA_START_BASE_CNTL_R, MPCC_OGAM, inst),\
0079     SRII(MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM, inst),\
0080     SRII(MPCC_OGAM_RAMB_START_CNTL_G, MPCC_OGAM, inst),\
0081     SRII(MPCC_OGAM_RAMB_START_CNTL_R, MPCC_OGAM, inst),\
0082     SRII(MPCC_OGAM_RAMB_START_SLOPE_CNTL_B, MPCC_OGAM, inst),\
0083     SRII(MPCC_OGAM_RAMB_START_SLOPE_CNTL_G, MPCC_OGAM, inst),\
0084     SRII(MPCC_OGAM_RAMB_START_SLOPE_CNTL_R, MPCC_OGAM, inst),\
0085     SRII(MPCC_OGAM_RAMB_END_CNTL1_B, MPCC_OGAM, inst),\
0086     SRII(MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM, inst),\
0087     SRII(MPCC_OGAM_RAMB_END_CNTL1_G, MPCC_OGAM, inst),\
0088     SRII(MPCC_OGAM_RAMB_END_CNTL2_G, MPCC_OGAM, inst),\
0089     SRII(MPCC_OGAM_RAMB_END_CNTL1_R, MPCC_OGAM, inst),\
0090     SRII(MPCC_OGAM_RAMB_END_CNTL2_R, MPCC_OGAM, inst),\
0091     SRII(MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM, inst),\
0092     SRII(MPCC_OGAM_RAMB_REGION_32_33, MPCC_OGAM, inst),\
0093     SRII(MPCC_OGAM_RAMB_OFFSET_B, MPCC_OGAM, inst),\
0094     SRII(MPCC_OGAM_RAMB_OFFSET_G, MPCC_OGAM, inst),\
0095     SRII(MPCC_OGAM_RAMB_OFFSET_R, MPCC_OGAM, inst),\
0096     SRII(MPCC_OGAM_RAMB_START_BASE_CNTL_B, MPCC_OGAM, inst),\
0097     SRII(MPCC_OGAM_RAMB_START_BASE_CNTL_G, MPCC_OGAM, inst),\
0098     SRII(MPCC_OGAM_RAMB_START_BASE_CNTL_R, MPCC_OGAM, inst),\
0099     SRII(MPCC_OGAM_CONTROL, MPCC_OGAM, inst),\
0100     SRII(MPCC_OGAM_LUT_CONTROL, MPCC_OGAM, inst)
0101 
0102 #define MPC_OUT_MUX_REG_LIST_DCN3_0(inst) \
0103     MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(inst),\
0104     SRII(CSC_MODE, MPC_OUT, inst),\
0105     SRII(CSC_C11_C12_A, MPC_OUT, inst),\
0106     SRII(CSC_C33_C34_A, MPC_OUT, inst),\
0107     SRII(CSC_C11_C12_B, MPC_OUT, inst),\
0108     SRII(CSC_C33_C34_B, MPC_OUT, inst),\
0109     SRII(DENORM_CONTROL, MPC_OUT, inst),\
0110     SRII(DENORM_CLAMP_G_Y, MPC_OUT, inst),\
0111     SRII(DENORM_CLAMP_B_CB, MPC_OUT, inst), \
0112     SR(MPC_OUT_CSC_COEF_FORMAT)
0113 
0114 #define MPC_RMU_GLOBAL_REG_LIST_DCN3AG \
0115     SR(MPC_RMU_CONTROL),\
0116     SR(MPC_RMU_MEM_PWR_CTRL)
0117 
0118 #define MPC_RMU_REG_LIST_DCN3AG(inst) \
0119     SRII(SHAPER_CONTROL, MPC_RMU, inst),\
0120     SRII(SHAPER_OFFSET_R, MPC_RMU, inst),\
0121     SRII(SHAPER_OFFSET_G, MPC_RMU, inst),\
0122     SRII(SHAPER_OFFSET_B, MPC_RMU, inst),\
0123     SRII(SHAPER_SCALE_R, MPC_RMU, inst),\
0124     SRII(SHAPER_SCALE_G_B, MPC_RMU, inst),\
0125     SRII(SHAPER_LUT_INDEX, MPC_RMU, inst),\
0126     SRII(SHAPER_LUT_DATA, MPC_RMU, inst),\
0127     SRII(SHAPER_LUT_WRITE_EN_MASK, MPC_RMU, inst),\
0128     SRII(SHAPER_RAMA_START_CNTL_B, MPC_RMU, inst),\
0129     SRII(SHAPER_RAMA_START_CNTL_G, MPC_RMU, inst),\
0130     SRII(SHAPER_RAMA_START_CNTL_R, MPC_RMU, inst),\
0131     SRII(SHAPER_RAMA_END_CNTL_B, MPC_RMU, inst),\
0132     SRII(SHAPER_RAMA_END_CNTL_G, MPC_RMU, inst),\
0133     SRII(SHAPER_RAMA_END_CNTL_R, MPC_RMU, inst),\
0134     SRII(SHAPER_RAMA_REGION_0_1, MPC_RMU, inst),\
0135     SRII(SHAPER_RAMA_REGION_2_3, MPC_RMU, inst),\
0136     SRII(SHAPER_RAMA_REGION_4_5, MPC_RMU, inst),\
0137     SRII(SHAPER_RAMA_REGION_6_7, MPC_RMU, inst),\
0138     SRII(SHAPER_RAMA_REGION_8_9, MPC_RMU, inst),\
0139     SRII(SHAPER_RAMA_REGION_10_11, MPC_RMU, inst),\
0140     SRII(SHAPER_RAMA_REGION_12_13, MPC_RMU, inst),\
0141     SRII(SHAPER_RAMA_REGION_14_15, MPC_RMU, inst),\
0142     SRII(SHAPER_RAMA_REGION_16_17, MPC_RMU, inst),\
0143     SRII(SHAPER_RAMA_REGION_18_19, MPC_RMU, inst),\
0144     SRII(SHAPER_RAMA_REGION_20_21, MPC_RMU, inst),\
0145     SRII(SHAPER_RAMA_REGION_22_23, MPC_RMU, inst),\
0146     SRII(SHAPER_RAMA_REGION_24_25, MPC_RMU, inst),\
0147     SRII(SHAPER_RAMA_REGION_26_27, MPC_RMU, inst),\
0148     SRII(SHAPER_RAMA_REGION_28_29, MPC_RMU, inst),\
0149     SRII(SHAPER_RAMA_REGION_30_31, MPC_RMU, inst),\
0150     SRII(SHAPER_RAMA_REGION_32_33, MPC_RMU, inst),\
0151     SRII(SHAPER_RAMB_START_CNTL_B, MPC_RMU, inst),\
0152     SRII(SHAPER_RAMB_START_CNTL_G, MPC_RMU, inst),\
0153     SRII(SHAPER_RAMB_START_CNTL_R, MPC_RMU, inst),\
0154     SRII(SHAPER_RAMB_END_CNTL_B, MPC_RMU, inst),\
0155     SRII(SHAPER_RAMB_END_CNTL_G, MPC_RMU, inst),\
0156     SRII(SHAPER_RAMB_END_CNTL_R, MPC_RMU, inst),\
0157     SRII(SHAPER_RAMB_REGION_0_1, MPC_RMU, inst),\
0158     SRII(SHAPER_RAMB_REGION_2_3, MPC_RMU, inst),\
0159     SRII(SHAPER_RAMB_REGION_4_5, MPC_RMU, inst),\
0160     SRII(SHAPER_RAMB_REGION_6_7, MPC_RMU, inst),\
0161     SRII(SHAPER_RAMB_REGION_8_9, MPC_RMU, inst),\
0162     SRII(SHAPER_RAMB_REGION_10_11, MPC_RMU, inst),\
0163     SRII(SHAPER_RAMB_REGION_12_13, MPC_RMU, inst),\
0164     SRII(SHAPER_RAMB_REGION_14_15, MPC_RMU, inst),\
0165     SRII(SHAPER_RAMB_REGION_16_17, MPC_RMU, inst),\
0166     SRII(SHAPER_RAMB_REGION_18_19, MPC_RMU, inst),\
0167     SRII(SHAPER_RAMB_REGION_20_21, MPC_RMU, inst),\
0168     SRII(SHAPER_RAMB_REGION_22_23, MPC_RMU, inst),\
0169     SRII(SHAPER_RAMB_REGION_24_25, MPC_RMU, inst),\
0170     SRII(SHAPER_RAMB_REGION_26_27, MPC_RMU, inst),\
0171     SRII(SHAPER_RAMB_REGION_28_29, MPC_RMU, inst),\
0172     SRII(SHAPER_RAMB_REGION_30_31, MPC_RMU, inst),\
0173     SRII(SHAPER_RAMB_REGION_32_33, MPC_RMU, inst),\
0174     SRII_MPC_RMU(3DLUT_MODE, MPC_RMU, inst),\
0175     SRII_MPC_RMU(3DLUT_INDEX, MPC_RMU, inst),\
0176     SRII_MPC_RMU(3DLUT_DATA, MPC_RMU, inst),\
0177     SRII_MPC_RMU(3DLUT_DATA_30BIT, MPC_RMU, inst),\
0178     SRII_MPC_RMU(3DLUT_READ_WRITE_CONTROL, MPC_RMU, inst),\
0179     SRII_MPC_RMU(3DLUT_OUT_NORM_FACTOR, MPC_RMU, inst),\
0180     SRII_MPC_RMU(3DLUT_OUT_OFFSET_R, MPC_RMU, inst),\
0181     SRII_MPC_RMU(3DLUT_OUT_OFFSET_G, MPC_RMU, inst),\
0182     SRII_MPC_RMU(3DLUT_OUT_OFFSET_B, MPC_RMU, inst)
0183 
0184 
0185 #define MPC_DWB_MUX_REG_LIST_DCN3_0(inst) \
0186     SRII_DWB(DWB_MUX, MUX, MPC_DWB, inst)
0187 
0188 #define MPC_REG_VARIABLE_LIST_DCN3_0 \
0189     MPC_REG_VARIABLE_LIST_DCN2_0 \
0190     uint32_t DWB_MUX[MAX_DWB]; \
0191     uint32_t MPCC_GAMUT_REMAP_COEF_FORMAT[MAX_MPCC]; \
0192     uint32_t MPCC_GAMUT_REMAP_MODE[MAX_MPCC]; \
0193     uint32_t MPC_GAMUT_REMAP_C11_C12_A[MAX_MPCC]; \
0194     uint32_t MPC_GAMUT_REMAP_C33_C34_A[MAX_MPCC]; \
0195     uint32_t MPC_GAMUT_REMAP_C11_C12_B[MAX_MPCC]; \
0196     uint32_t MPC_GAMUT_REMAP_C33_C34_B[MAX_MPCC]; \
0197     uint32_t MPC_RMU_CONTROL; \
0198     uint32_t MPC_RMU_MEM_PWR_CTRL; \
0199     uint32_t SHAPER_CONTROL[MAX_RMU]; \
0200     uint32_t SHAPER_OFFSET_R[MAX_RMU]; \
0201     uint32_t SHAPER_OFFSET_G[MAX_RMU]; \
0202     uint32_t SHAPER_OFFSET_B[MAX_RMU]; \
0203     uint32_t SHAPER_SCALE_R[MAX_RMU]; \
0204     uint32_t SHAPER_SCALE_G_B[MAX_RMU]; \
0205     uint32_t SHAPER_LUT_INDEX[MAX_RMU]; \
0206     uint32_t SHAPER_LUT_DATA[MAX_RMU]; \
0207     uint32_t SHAPER_LUT_WRITE_EN_MASK[MAX_RMU]; \
0208     uint32_t SHAPER_RAMA_START_CNTL_B[MAX_RMU]; \
0209     uint32_t SHAPER_RAMA_START_CNTL_G[MAX_RMU]; \
0210     uint32_t SHAPER_RAMA_START_CNTL_R[MAX_RMU]; \
0211     uint32_t SHAPER_RAMA_END_CNTL_B[MAX_RMU]; \
0212     uint32_t SHAPER_RAMA_END_CNTL_G[MAX_RMU]; \
0213     uint32_t SHAPER_RAMA_END_CNTL_R[MAX_RMU]; \
0214     uint32_t SHAPER_RAMA_REGION_0_1[MAX_RMU]; \
0215     uint32_t SHAPER_RAMA_REGION_2_3[MAX_RMU]; \
0216     uint32_t SHAPER_RAMA_REGION_4_5[MAX_RMU]; \
0217     uint32_t SHAPER_RAMA_REGION_6_7[MAX_RMU]; \
0218     uint32_t SHAPER_RAMA_REGION_8_9[MAX_RMU]; \
0219     uint32_t SHAPER_RAMA_REGION_10_11[MAX_RMU]; \
0220     uint32_t SHAPER_RAMA_REGION_12_13[MAX_RMU]; \
0221     uint32_t SHAPER_RAMA_REGION_14_15[MAX_RMU]; \
0222     uint32_t SHAPER_RAMA_REGION_16_17[MAX_RMU]; \
0223     uint32_t SHAPER_RAMA_REGION_18_19[MAX_RMU]; \
0224     uint32_t SHAPER_RAMA_REGION_20_21[MAX_RMU]; \
0225     uint32_t SHAPER_RAMA_REGION_22_23[MAX_RMU]; \
0226     uint32_t SHAPER_RAMA_REGION_24_25[MAX_RMU]; \
0227     uint32_t SHAPER_RAMA_REGION_26_27[MAX_RMU]; \
0228     uint32_t SHAPER_RAMA_REGION_28_29[MAX_RMU]; \
0229     uint32_t SHAPER_RAMA_REGION_30_31[MAX_RMU]; \
0230     uint32_t SHAPER_RAMA_REGION_32_33[MAX_RMU]; \
0231     uint32_t MPCC_OGAM_RAMA_START_SLOPE_CNTL_B[MAX_MPCC]; \
0232     uint32_t MPCC_OGAM_RAMA_START_SLOPE_CNTL_G[MAX_MPCC]; \
0233     uint32_t MPCC_OGAM_RAMA_START_SLOPE_CNTL_R[MAX_MPCC]; \
0234     uint32_t MPCC_OGAM_RAMA_OFFSET_B[MAX_MPCC]; \
0235     uint32_t MPCC_OGAM_RAMA_OFFSET_G[MAX_MPCC]; \
0236     uint32_t MPCC_OGAM_RAMA_OFFSET_R[MAX_MPCC]; \
0237     uint32_t MPCC_OGAM_RAMA_START_BASE_CNTL_B[MAX_MPCC]; \
0238     uint32_t MPCC_OGAM_RAMA_START_BASE_CNTL_G[MAX_MPCC]; \
0239     uint32_t MPCC_OGAM_RAMA_START_BASE_CNTL_R[MAX_MPCC];\
0240     uint32_t SHAPER_RAMB_START_CNTL_B[MAX_RMU]; \
0241     uint32_t SHAPER_RAMB_START_CNTL_G[MAX_RMU]; \
0242     uint32_t SHAPER_RAMB_START_CNTL_R[MAX_RMU]; \
0243     uint32_t SHAPER_RAMB_END_CNTL_B[MAX_RMU]; \
0244     uint32_t SHAPER_RAMB_END_CNTL_G[MAX_RMU]; \
0245     uint32_t SHAPER_RAMB_END_CNTL_R[MAX_RMU]; \
0246     uint32_t SHAPER_RAMB_REGION_0_1[MAX_RMU]; \
0247     uint32_t SHAPER_RAMB_REGION_2_3[MAX_RMU]; \
0248     uint32_t SHAPER_RAMB_REGION_4_5[MAX_RMU]; \
0249     uint32_t SHAPER_RAMB_REGION_6_7[MAX_RMU]; \
0250     uint32_t SHAPER_RAMB_REGION_8_9[MAX_RMU]; \
0251     uint32_t SHAPER_RAMB_REGION_10_11[MAX_RMU]; \
0252     uint32_t SHAPER_RAMB_REGION_12_13[MAX_RMU]; \
0253     uint32_t SHAPER_RAMB_REGION_14_15[MAX_RMU]; \
0254     uint32_t SHAPER_RAMB_REGION_16_17[MAX_RMU]; \
0255     uint32_t SHAPER_RAMB_REGION_18_19[MAX_RMU]; \
0256     uint32_t SHAPER_RAMB_REGION_20_21[MAX_RMU]; \
0257     uint32_t SHAPER_RAMB_REGION_22_23[MAX_RMU]; \
0258     uint32_t SHAPER_RAMB_REGION_24_25[MAX_RMU]; \
0259     uint32_t SHAPER_RAMB_REGION_26_27[MAX_RMU]; \
0260     uint32_t SHAPER_RAMB_REGION_28_29[MAX_RMU]; \
0261     uint32_t SHAPER_RAMB_REGION_30_31[MAX_RMU]; \
0262     uint32_t SHAPER_RAMB_REGION_32_33[MAX_RMU]; \
0263     uint32_t RMU_3DLUT_MODE[MAX_RMU]; \
0264     uint32_t RMU_3DLUT_INDEX[MAX_RMU]; \
0265     uint32_t RMU_3DLUT_DATA[MAX_RMU]; \
0266     uint32_t RMU_3DLUT_DATA_30BIT[MAX_RMU]; \
0267     uint32_t RMU_3DLUT_READ_WRITE_CONTROL[MAX_RMU]; \
0268     uint32_t RMU_3DLUT_OUT_NORM_FACTOR[MAX_RMU]; \
0269     uint32_t RMU_3DLUT_OUT_OFFSET_R[MAX_RMU]; \
0270     uint32_t RMU_3DLUT_OUT_OFFSET_G[MAX_RMU]; \
0271     uint32_t RMU_3DLUT_OUT_OFFSET_B[MAX_RMU]; \
0272     uint32_t MPCC_OGAM_RAMB_START_SLOPE_CNTL_B[MAX_MPCC]; \
0273     uint32_t MPCC_OGAM_RAMB_START_SLOPE_CNTL_G[MAX_MPCC]; \
0274     uint32_t MPCC_OGAM_RAMB_START_SLOPE_CNTL_R[MAX_MPCC]; \
0275     uint32_t MPCC_OGAM_CONTROL[MAX_MPCC]; \
0276     uint32_t MPCC_OGAM_LUT_CONTROL[MAX_MPCC]; \
0277     uint32_t MPCC_OGAM_RAMB_OFFSET_B[MAX_MPCC]; \
0278     uint32_t MPCC_OGAM_RAMB_OFFSET_G[MAX_MPCC]; \
0279     uint32_t MPCC_OGAM_RAMB_OFFSET_R[MAX_MPCC]; \
0280     uint32_t MPCC_OGAM_RAMB_START_BASE_CNTL_B[MAX_MPCC]; \
0281     uint32_t MPCC_OGAM_RAMB_START_BASE_CNTL_G[MAX_MPCC]; \
0282     uint32_t MPCC_OGAM_RAMB_START_BASE_CNTL_R[MAX_MPCC]; \
0283     uint32_t MPC_OUT_CSC_COEF_FORMAT
0284 
0285 #define MPC_REG_VARIABLE_LIST_DCN32 \
0286     uint32_t MPCC_MOVABLE_CM_LOCATION_CONTROL[MAX_MPCC]; \
0287     uint32_t MPCC_MCM_SHAPER_CONTROL[MAX_MPCC]; \
0288     uint32_t MPCC_MCM_SHAPER_OFFSET_R[MAX_MPCC]; \
0289     uint32_t MPCC_MCM_SHAPER_OFFSET_G[MAX_MPCC]; \
0290     uint32_t MPCC_MCM_SHAPER_OFFSET_B[MAX_MPCC]; \
0291     uint32_t MPCC_MCM_SHAPER_SCALE_R[MAX_MPCC]; \
0292     uint32_t MPCC_MCM_SHAPER_SCALE_G_B[MAX_MPCC]; \
0293     uint32_t MPCC_MCM_SHAPER_LUT_INDEX[MAX_MPCC]; \
0294     uint32_t MPCC_MCM_SHAPER_LUT_DATA[MAX_MPCC]; \
0295     uint32_t MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK[MAX_MPCC]; \
0296     uint32_t MPCC_MCM_SHAPER_RAMA_START_CNTL_B[MAX_MPCC]; \
0297     uint32_t MPCC_MCM_SHAPER_RAMA_START_CNTL_G[MAX_MPCC]; \
0298     uint32_t MPCC_MCM_SHAPER_RAMA_START_CNTL_R[MAX_MPCC]; \
0299     uint32_t MPCC_MCM_SHAPER_RAMA_END_CNTL_B[MAX_MPCC]; \
0300     uint32_t MPCC_MCM_SHAPER_RAMA_END_CNTL_G[MAX_MPCC]; \
0301     uint32_t MPCC_MCM_SHAPER_RAMA_END_CNTL_R[MAX_MPCC]; \
0302     uint32_t MPCC_MCM_SHAPER_RAMA_REGION_0_1[MAX_MPCC]; \
0303     uint32_t MPCC_MCM_SHAPER_RAMA_REGION_2_3[MAX_MPCC]; \
0304     uint32_t MPCC_MCM_SHAPER_RAMA_REGION_4_5[MAX_MPCC]; \
0305     uint32_t MPCC_MCM_SHAPER_RAMA_REGION_6_7[MAX_MPCC]; \
0306     uint32_t MPCC_MCM_SHAPER_RAMA_REGION_8_9[MAX_MPCC]; \
0307     uint32_t MPCC_MCM_SHAPER_RAMA_REGION_10_11[MAX_MPCC]; \
0308     uint32_t MPCC_MCM_SHAPER_RAMA_REGION_12_13[MAX_MPCC]; \
0309     uint32_t MPCC_MCM_SHAPER_RAMA_REGION_14_15[MAX_MPCC]; \
0310     uint32_t MPCC_MCM_SHAPER_RAMA_REGION_16_17[MAX_MPCC]; \
0311     uint32_t MPCC_MCM_SHAPER_RAMA_REGION_18_19[MAX_MPCC]; \
0312     uint32_t MPCC_MCM_SHAPER_RAMA_REGION_20_21[MAX_MPCC]; \
0313     uint32_t MPCC_MCM_SHAPER_RAMA_REGION_22_23[MAX_MPCC]; \
0314     uint32_t MPCC_MCM_SHAPER_RAMA_REGION_24_25[MAX_MPCC]; \
0315     uint32_t MPCC_MCM_SHAPER_RAMA_REGION_26_27[MAX_MPCC]; \
0316     uint32_t MPCC_MCM_SHAPER_RAMA_REGION_28_29[MAX_MPCC]; \
0317     uint32_t MPCC_MCM_SHAPER_RAMA_REGION_30_31[MAX_MPCC]; \
0318     uint32_t MPCC_MCM_SHAPER_RAMA_REGION_32_33[MAX_MPCC]; \
0319     uint32_t MPCC_MCM_SHAPER_RAMB_START_CNTL_B[MAX_MPCC]; \
0320     uint32_t MPCC_MCM_SHAPER_RAMB_START_CNTL_G[MAX_MPCC]; \
0321     uint32_t MPCC_MCM_SHAPER_RAMB_START_CNTL_R[MAX_MPCC]; \
0322     uint32_t MPCC_MCM_SHAPER_RAMB_END_CNTL_B[MAX_MPCC]; \
0323     uint32_t MPCC_MCM_SHAPER_RAMB_END_CNTL_G[MAX_MPCC]; \
0324     uint32_t MPCC_MCM_SHAPER_RAMB_END_CNTL_R[MAX_MPCC]; \
0325     uint32_t MPCC_MCM_SHAPER_RAMB_REGION_0_1[MAX_MPCC]; \
0326     uint32_t MPCC_MCM_SHAPER_RAMB_REGION_2_3[MAX_MPCC]; \
0327     uint32_t MPCC_MCM_SHAPER_RAMB_REGION_4_5[MAX_MPCC]; \
0328     uint32_t MPCC_MCM_SHAPER_RAMB_REGION_6_7[MAX_MPCC]; \
0329     uint32_t MPCC_MCM_SHAPER_RAMB_REGION_8_9[MAX_MPCC]; \
0330     uint32_t MPCC_MCM_SHAPER_RAMB_REGION_10_11[MAX_MPCC]; \
0331     uint32_t MPCC_MCM_SHAPER_RAMB_REGION_12_13[MAX_MPCC]; \
0332     uint32_t MPCC_MCM_SHAPER_RAMB_REGION_14_15[MAX_MPCC]; \
0333     uint32_t MPCC_MCM_SHAPER_RAMB_REGION_16_17[MAX_MPCC]; \
0334     uint32_t MPCC_MCM_SHAPER_RAMB_REGION_18_19[MAX_MPCC]; \
0335     uint32_t MPCC_MCM_SHAPER_RAMB_REGION_20_21[MAX_MPCC]; \
0336     uint32_t MPCC_MCM_SHAPER_RAMB_REGION_22_23[MAX_MPCC]; \
0337     uint32_t MPCC_MCM_SHAPER_RAMB_REGION_24_25[MAX_MPCC]; \
0338     uint32_t MPCC_MCM_SHAPER_RAMB_REGION_26_27[MAX_MPCC]; \
0339     uint32_t MPCC_MCM_SHAPER_RAMB_REGION_28_29[MAX_MPCC]; \
0340     uint32_t MPCC_MCM_SHAPER_RAMB_REGION_30_31[MAX_MPCC]; \
0341     uint32_t MPCC_MCM_SHAPER_RAMB_REGION_32_33[MAX_MPCC]; \
0342     uint32_t MPCC_MCM_3DLUT_MODE[MAX_MPCC]; \
0343     uint32_t MPCC_MCM_3DLUT_INDEX[MAX_MPCC]; \
0344     uint32_t MPCC_MCM_3DLUT_DATA[MAX_MPCC]; \
0345     uint32_t MPCC_MCM_3DLUT_DATA_30BIT[MAX_MPCC]; \
0346     uint32_t MPCC_MCM_3DLUT_READ_WRITE_CONTROL[MAX_MPCC]; \
0347     uint32_t MPCC_MCM_3DLUT_OUT_NORM_FACTOR[MAX_MPCC]; \
0348     uint32_t MPCC_MCM_3DLUT_OUT_OFFSET_R[MAX_MPCC]; \
0349     uint32_t MPCC_MCM_3DLUT_OUT_OFFSET_G[MAX_MPCC]; \
0350     uint32_t MPCC_MCM_3DLUT_OUT_OFFSET_B[MAX_MPCC]; \
0351     uint32_t MPCC_MCM_1DLUT_CONTROL[MAX_MPCC]; \
0352     uint32_t MPCC_MCM_1DLUT_LUT_INDEX[MAX_MPCC]; \
0353     uint32_t MPCC_MCM_1DLUT_LUT_DATA[MAX_MPCC]; \
0354     uint32_t MPCC_MCM_1DLUT_LUT_CONTROL[MAX_MPCC]; \
0355     uint32_t MPCC_MCM_1DLUT_RAMA_START_CNTL_B[MAX_MPCC]; \
0356     uint32_t MPCC_MCM_1DLUT_RAMA_START_CNTL_G[MAX_MPCC]; \
0357     uint32_t MPCC_MCM_1DLUT_RAMA_START_CNTL_R[MAX_MPCC]; \
0358     uint32_t MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B[MAX_MPCC]; \
0359     uint32_t MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G[MAX_MPCC]; \
0360     uint32_t MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R[MAX_MPCC]; \
0361     uint32_t MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B[MAX_MPCC]; \
0362     uint32_t MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G[MAX_MPCC]; \
0363     uint32_t MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R[MAX_MPCC]; \
0364     uint32_t MPCC_MCM_1DLUT_RAMA_END_CNTL1_B[MAX_MPCC]; \
0365     uint32_t MPCC_MCM_1DLUT_RAMA_END_CNTL2_B[MAX_MPCC]; \
0366     uint32_t MPCC_MCM_1DLUT_RAMA_END_CNTL1_G[MAX_MPCC]; \
0367     uint32_t MPCC_MCM_1DLUT_RAMA_END_CNTL2_G[MAX_MPCC]; \
0368     uint32_t MPCC_MCM_1DLUT_RAMA_END_CNTL1_R[MAX_MPCC]; \
0369     uint32_t MPCC_MCM_1DLUT_RAMA_END_CNTL2_R[MAX_MPCC]; \
0370     uint32_t MPCC_MCM_1DLUT_RAMA_OFFSET_B[MAX_MPCC]; \
0371     uint32_t MPCC_MCM_1DLUT_RAMA_OFFSET_G[MAX_MPCC]; \
0372     uint32_t MPCC_MCM_1DLUT_RAMA_OFFSET_R[MAX_MPCC]; \
0373     uint32_t MPCC_MCM_1DLUT_RAMA_REGION_0_1[MAX_MPCC]; \
0374     uint32_t MPCC_MCM_1DLUT_RAMA_REGION_2_3[MAX_MPCC]; \
0375     uint32_t MPCC_MCM_1DLUT_RAMA_REGION_4_5[MAX_MPCC]; \
0376     uint32_t MPCC_MCM_1DLUT_RAMA_REGION_6_7[MAX_MPCC]; \
0377     uint32_t MPCC_MCM_1DLUT_RAMA_REGION_8_9[MAX_MPCC]; \
0378     uint32_t MPCC_MCM_1DLUT_RAMA_REGION_10_11[MAX_MPCC]; \
0379     uint32_t MPCC_MCM_1DLUT_RAMA_REGION_12_13[MAX_MPCC]; \
0380     uint32_t MPCC_MCM_1DLUT_RAMA_REGION_14_15[MAX_MPCC]; \
0381     uint32_t MPCC_MCM_1DLUT_RAMA_REGION_16_17[MAX_MPCC]; \
0382     uint32_t MPCC_MCM_1DLUT_RAMA_REGION_18_19[MAX_MPCC]; \
0383     uint32_t MPCC_MCM_1DLUT_RAMA_REGION_20_21[MAX_MPCC]; \
0384     uint32_t MPCC_MCM_1DLUT_RAMA_REGION_22_23[MAX_MPCC]; \
0385     uint32_t MPCC_MCM_1DLUT_RAMA_REGION_24_25[MAX_MPCC]; \
0386     uint32_t MPCC_MCM_1DLUT_RAMA_REGION_26_27[MAX_MPCC]; \
0387     uint32_t MPCC_MCM_1DLUT_RAMA_REGION_28_29[MAX_MPCC]; \
0388     uint32_t MPCC_MCM_1DLUT_RAMA_REGION_30_31[MAX_MPCC]; \
0389     uint32_t MPCC_MCM_1DLUT_RAMA_REGION_32_33[MAX_MPCC]; \
0390     uint32_t MPCC_MCM_1DLUT_RAMB_START_CNTL_B[MAX_MPCC]; \
0391     uint32_t MPCC_MCM_1DLUT_RAMB_START_CNTL_G[MAX_MPCC]; \
0392     uint32_t MPCC_MCM_1DLUT_RAMB_START_CNTL_R[MAX_MPCC]; \
0393     uint32_t MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B[MAX_MPCC]; \
0394     uint32_t MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G[MAX_MPCC]; \
0395     uint32_t MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R[MAX_MPCC]; \
0396     uint32_t MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B[MAX_MPCC]; \
0397     uint32_t MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G[MAX_MPCC]; \
0398     uint32_t MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R[MAX_MPCC]; \
0399     uint32_t MPCC_MCM_1DLUT_RAMB_END_CNTL1_B[MAX_MPCC]; \
0400     uint32_t MPCC_MCM_1DLUT_RAMB_END_CNTL2_B[MAX_MPCC]; \
0401     uint32_t MPCC_MCM_1DLUT_RAMB_END_CNTL1_G[MAX_MPCC]; \
0402     uint32_t MPCC_MCM_1DLUT_RAMB_END_CNTL2_G[MAX_MPCC]; \
0403     uint32_t MPCC_MCM_1DLUT_RAMB_END_CNTL1_R[MAX_MPCC]; \
0404     uint32_t MPCC_MCM_1DLUT_RAMB_END_CNTL2_R[MAX_MPCC]; \
0405     uint32_t MPCC_MCM_1DLUT_RAMB_OFFSET_B[MAX_MPCC]; \
0406     uint32_t MPCC_MCM_1DLUT_RAMB_OFFSET_G[MAX_MPCC]; \
0407     uint32_t MPCC_MCM_1DLUT_RAMB_OFFSET_R[MAX_MPCC]; \
0408     uint32_t MPCC_MCM_1DLUT_RAMB_REGION_0_1[MAX_MPCC]; \
0409     uint32_t MPCC_MCM_1DLUT_RAMB_REGION_2_3[MAX_MPCC]; \
0410     uint32_t MPCC_MCM_1DLUT_RAMB_REGION_4_5[MAX_MPCC]; \
0411     uint32_t MPCC_MCM_1DLUT_RAMB_REGION_6_7[MAX_MPCC]; \
0412     uint32_t MPCC_MCM_1DLUT_RAMB_REGION_8_9[MAX_MPCC]; \
0413     uint32_t MPCC_MCM_1DLUT_RAMB_REGION_10_11[MAX_MPCC]; \
0414     uint32_t MPCC_MCM_1DLUT_RAMB_REGION_12_13[MAX_MPCC]; \
0415     uint32_t MPCC_MCM_1DLUT_RAMB_REGION_14_15[MAX_MPCC]; \
0416     uint32_t MPCC_MCM_1DLUT_RAMB_REGION_16_17[MAX_MPCC]; \
0417     uint32_t MPCC_MCM_1DLUT_RAMB_REGION_18_19[MAX_MPCC]; \
0418     uint32_t MPCC_MCM_1DLUT_RAMB_REGION_20_21[MAX_MPCC]; \
0419     uint32_t MPCC_MCM_1DLUT_RAMB_REGION_22_23[MAX_MPCC]; \
0420     uint32_t MPCC_MCM_1DLUT_RAMB_REGION_24_25[MAX_MPCC]; \
0421     uint32_t MPCC_MCM_1DLUT_RAMB_REGION_26_27[MAX_MPCC]; \
0422     uint32_t MPCC_MCM_1DLUT_RAMB_REGION_28_29[MAX_MPCC]; \
0423     uint32_t MPCC_MCM_1DLUT_RAMB_REGION_30_31[MAX_MPCC]; \
0424     uint32_t MPCC_MCM_1DLUT_RAMB_REGION_32_33[MAX_MPCC]; \
0425     uint32_t MPCC_MCM_MEM_PWR_CTRL[MAX_MPCC]
0426 
0427 #define MPC_COMMON_MASK_SH_LIST_DCN3_0(mask_sh) \
0428     MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh),\
0429     SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
0430     SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\
0431     SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\
0432     SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\
0433     SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\
0434     SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
0435     SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\
0436     SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\
0437     SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\
0438     SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\
0439     SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\
0440     SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_STATE, mask_sh),\
0441     SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_MODE, mask_sh),\
0442     SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MAX_R_CR, mask_sh),\
0443     SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MIN_R_CR, mask_sh),\
0444     SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MAX_G_Y, mask_sh),\
0445     SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MIN_G_Y, mask_sh),\
0446     SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\
0447     SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh),\
0448     SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE, mask_sh),\
0449     SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE_CURRENT, mask_sh),\
0450     SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_GAMUT_REMAP_COEF_FORMAT, mask_sh),\
0451     SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C11_A, mask_sh),\
0452     SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C12_A, mask_sh),\
0453     SF(MPC_DWB0_MUX, MPC_DWB0_MUX, mask_sh),\
0454     SF(MPC_DWB0_MUX, MPC_DWB0_MUX_STATUS, mask_sh),\
0455     SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL, mask_sh),\
0456     SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL_DISABLE, mask_sh),\
0457     SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_MODE, mask_sh),\
0458     SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT, mask_sh), \
0459     SF(MPC_RMU_CONTROL, MPC_RMU0_MUX, mask_sh), \
0460     SF(MPC_RMU_CONTROL, MPC_RMU1_MUX, mask_sh), \
0461     SF(MPC_RMU_CONTROL, MPC_RMU0_MUX_STATUS, mask_sh), \
0462     SF(MPC_RMU_CONTROL, MPC_RMU1_MUX_STATUS, mask_sh), \
0463     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\
0464     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
0465     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\
0466     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
0467     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\
0468     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_B, mask_sh),\
0469     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh),\
0470     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B, mask_sh),\
0471     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B, mask_sh),\
0472     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_B, mask_sh),\
0473     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\
0474     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B, MPCC_OGAM_RAMA_OFFSET_B, mask_sh),\
0475     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G, MPCC_OGAM_RAMA_OFFSET_G, mask_sh),\
0476     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R, MPCC_OGAM_RAMA_OFFSET_R, mask_sh),\
0477     SF(MPCC_OGAM0_MPCC_OGAM_LUT_INDEX, MPCC_OGAM_LUT_INDEX, mask_sh),\
0478     SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE, mask_sh),\
0479     SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT, mask_sh),\
0480     SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_PWL_DISABLE, mask_sh),\
0481     SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE_CURRENT, mask_sh),\
0482     SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT_CURRENT, mask_sh),\
0483     SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_WRITE_COLOR_MASK, mask_sh),\
0484     SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_COLOR_SEL, mask_sh),\
0485     SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_DBG, mask_sh),\
0486     SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_HOST_SEL, mask_sh),\
0487     SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_CONFIG_MODE, mask_sh),\
0488     SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_STATUS, mask_sh),\
0489     SF(MPCC_OGAM0_MPCC_OGAM_LUT_DATA, MPCC_OGAM_LUT_DATA, mask_sh),\
0490     SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_MODE, mask_sh),\
0491     SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_SIZE, mask_sh),\
0492     SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_MODE_CURRENT, mask_sh),\
0493     SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_WRITE_EN_MASK, mask_sh),\
0494     SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_RAM_SEL, mask_sh),\
0495     SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_30BIT_EN, mask_sh),\
0496     SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_CONFIG_STATUS, mask_sh),\
0497     SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_READ_SEL, mask_sh),\
0498     SF(MPC_RMU0_3DLUT_INDEX, MPC_RMU_3DLUT_INDEX, mask_sh),\
0499     SF(MPC_RMU0_3DLUT_DATA, MPC_RMU_3DLUT_DATA0, mask_sh),\
0500     SF(MPC_RMU0_3DLUT_DATA, MPC_RMU_3DLUT_DATA1, mask_sh),\
0501     SF(MPC_RMU0_3DLUT_DATA_30BIT, MPC_RMU_3DLUT_DATA_30BIT, mask_sh),\
0502     SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_LUT_MODE, mask_sh),\
0503     SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_LUT_MODE_CURRENT, mask_sh),\
0504     SF(MPC_RMU0_SHAPER_OFFSET_R, MPC_RMU_SHAPER_OFFSET_R, mask_sh),\
0505     SF(MPC_RMU0_SHAPER_OFFSET_G, MPC_RMU_SHAPER_OFFSET_G, mask_sh),\
0506     SF(MPC_RMU0_SHAPER_OFFSET_B, MPC_RMU_SHAPER_OFFSET_B, mask_sh),\
0507     SF(MPC_RMU0_SHAPER_SCALE_R, MPC_RMU_SHAPER_SCALE_R, mask_sh),\
0508     SF(MPC_RMU0_SHAPER_SCALE_G_B, MPC_RMU_SHAPER_SCALE_G, mask_sh),\
0509     SF(MPC_RMU0_SHAPER_SCALE_G_B, MPC_RMU_SHAPER_SCALE_B, mask_sh),\
0510     SF(MPC_RMU0_SHAPER_LUT_INDEX, MPC_RMU_SHAPER_LUT_INDEX, mask_sh),\
0511     SF(MPC_RMU0_SHAPER_LUT_DATA, MPC_RMU_SHAPER_LUT_DATA, mask_sh),\
0512     SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_LUT_WRITE_EN_MASK, mask_sh),\
0513     SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_LUT_WRITE_SEL, mask_sh),\
0514     SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_CONFIG_STATUS, mask_sh),\
0515     SF(MPC_RMU0_SHAPER_RAMA_START_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B, mask_sh),\
0516     SF(MPC_RMU0_SHAPER_RAMA_START_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\
0517     SF(MPC_RMU0_SHAPER_RAMA_END_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B, mask_sh),\
0518     SF(MPC_RMU0_SHAPER_RAMA_END_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B, mask_sh),\
0519     SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\
0520     SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
0521     SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\
0522     SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
0523     SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_PWR_FORCE, mask_sh),\
0524     SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_PWR_DIS, mask_sh),\
0525     SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_SHAPER_MEM_PWR_STATE, mask_sh),\
0526     SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_3DLUT_MEM_PWR_STATE, mask_sh),\
0527     SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_MEM_PWR_FORCE, mask_sh),\
0528     SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_MEM_PWR_DIS, mask_sh),\
0529     SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_SHAPER_MEM_PWR_STATE, mask_sh),\
0530     SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_3DLUT_MEM_PWR_STATE, mask_sh),\
0531     SF(CUR_VUPDATE_LOCK_SET0, CUR_VUPDATE_LOCK_SET, mask_sh)
0532 
0533 
0534 #define MPC_COMMON_MASK_SH_LIST_DCN30(mask_sh) \
0535     MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh),\
0536     SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
0537     SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\
0538     SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\
0539     SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\
0540     SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\
0541     SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
0542     SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\
0543     SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\
0544     SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\
0545     SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\
0546     SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\
0547     SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_LOW_PWR_MODE, mask_sh),\
0548     SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_STATE, mask_sh),\
0549     SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_MODE, mask_sh),\
0550     SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MAX_R_CR, mask_sh),\
0551     SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MIN_R_CR, mask_sh),\
0552     SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MAX_G_Y, mask_sh),\
0553     SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MIN_G_Y, mask_sh),\
0554     SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\
0555     SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh),\
0556     SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE, mask_sh),\
0557     SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE_CURRENT, mask_sh),\
0558     SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_GAMUT_REMAP_COEF_FORMAT, mask_sh),\
0559     SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C11_A, mask_sh),\
0560     SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C12_A, mask_sh),\
0561     SF(MPC_DWB0_MUX, MPC_DWB0_MUX, mask_sh),\
0562     SF(MPC_DWB0_MUX, MPC_DWB0_MUX_STATUS, mask_sh),\
0563     SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL, mask_sh),\
0564     SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL_DISABLE, mask_sh),\
0565     SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_MODE, mask_sh),\
0566     SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT, mask_sh), \
0567     SF(MPC_RMU_CONTROL, MPC_RMU0_MUX, mask_sh), \
0568     SF(MPC_RMU_CONTROL, MPC_RMU1_MUX, mask_sh), \
0569     SF(MPC_RMU_CONTROL, MPC_RMU0_MUX_STATUS, mask_sh), \
0570     SF(MPC_RMU_CONTROL, MPC_RMU1_MUX_STATUS, mask_sh), \
0571     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\
0572     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
0573     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\
0574     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
0575     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\
0576     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_B, mask_sh),\
0577     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh),\
0578     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B, mask_sh),\
0579     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B, mask_sh),\
0580     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_B, mask_sh),\
0581     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\
0582     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B, MPCC_OGAM_RAMA_OFFSET_B, mask_sh),\
0583     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G, MPCC_OGAM_RAMA_OFFSET_G, mask_sh),\
0584     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R, MPCC_OGAM_RAMA_OFFSET_R, mask_sh),\
0585     SF(MPCC_OGAM0_MPCC_OGAM_LUT_INDEX, MPCC_OGAM_LUT_INDEX, mask_sh),\
0586     SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE, mask_sh),\
0587     SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT, mask_sh),\
0588     SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_PWL_DISABLE, mask_sh),\
0589     SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE_CURRENT, mask_sh),\
0590     SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT_CURRENT, mask_sh),\
0591     SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_WRITE_COLOR_MASK, mask_sh),\
0592     SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_COLOR_SEL, mask_sh),\
0593     SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_DBG, mask_sh),\
0594     SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_HOST_SEL, mask_sh),\
0595     SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_CONFIG_MODE, mask_sh),\
0596     /*SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_STATUS, mask_sh),*/\
0597     SF(MPCC_OGAM0_MPCC_OGAM_LUT_DATA, MPCC_OGAM_LUT_DATA, mask_sh),\
0598     SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_MODE, mask_sh),\
0599     SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_SIZE, mask_sh),\
0600     /*SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_MODE_CURRENT, mask_sh),*/\
0601     SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_WRITE_EN_MASK, mask_sh),\
0602     SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_RAM_SEL, mask_sh),\
0603     SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_30BIT_EN, mask_sh),\
0604     /*SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_CONFIG_STATUS, mask_sh),*/\
0605     SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_READ_SEL, mask_sh),\
0606     SF(MPC_RMU0_3DLUT_INDEX, MPC_RMU_3DLUT_INDEX, mask_sh),\
0607     SF(MPC_RMU0_3DLUT_DATA, MPC_RMU_3DLUT_DATA0, mask_sh),\
0608     SF(MPC_RMU0_3DLUT_DATA, MPC_RMU_3DLUT_DATA1, mask_sh),\
0609     SF(MPC_RMU0_3DLUT_DATA_30BIT, MPC_RMU_3DLUT_DATA_30BIT, mask_sh),\
0610     SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_LUT_MODE, mask_sh),\
0611     /*SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_LUT_MODE_CURRENT, mask_sh),*/\
0612     SF(MPC_RMU0_SHAPER_OFFSET_R, MPC_RMU_SHAPER_OFFSET_R, mask_sh),\
0613     SF(MPC_RMU0_SHAPER_OFFSET_G, MPC_RMU_SHAPER_OFFSET_G, mask_sh),\
0614     SF(MPC_RMU0_SHAPER_OFFSET_B, MPC_RMU_SHAPER_OFFSET_B, mask_sh),\
0615     SF(MPC_RMU0_SHAPER_SCALE_R, MPC_RMU_SHAPER_SCALE_R, mask_sh),\
0616     SF(MPC_RMU0_SHAPER_SCALE_G_B, MPC_RMU_SHAPER_SCALE_G, mask_sh),\
0617     SF(MPC_RMU0_SHAPER_SCALE_G_B, MPC_RMU_SHAPER_SCALE_B, mask_sh),\
0618     SF(MPC_RMU0_SHAPER_LUT_INDEX, MPC_RMU_SHAPER_LUT_INDEX, mask_sh),\
0619     SF(MPC_RMU0_SHAPER_LUT_DATA, MPC_RMU_SHAPER_LUT_DATA, mask_sh),\
0620     SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_LUT_WRITE_EN_MASK, mask_sh),\
0621     SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_LUT_WRITE_SEL, mask_sh),\
0622     /*SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_CONFIG_STATUS, mask_sh),*/\
0623     SF(MPC_RMU0_SHAPER_RAMA_START_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B, mask_sh),\
0624     SF(MPC_RMU0_SHAPER_RAMA_START_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\
0625     SF(MPC_RMU0_SHAPER_RAMA_END_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B, mask_sh),\
0626     SF(MPC_RMU0_SHAPER_RAMA_END_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B, mask_sh),\
0627     SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\
0628     SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
0629     SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\
0630     SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
0631     SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_PWR_FORCE, mask_sh),\
0632     SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_PWR_DIS, mask_sh),\
0633     SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_SHAPER_MEM_PWR_STATE, mask_sh),\
0634     SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_3DLUT_MEM_PWR_STATE, mask_sh),\
0635     SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_LOW_PWR_MODE, mask_sh),\
0636     SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_MEM_PWR_FORCE, mask_sh),\
0637     SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_MEM_PWR_DIS, mask_sh),\
0638     SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_SHAPER_MEM_PWR_STATE, mask_sh),\
0639     SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_3DLUT_MEM_PWR_STATE, mask_sh),\
0640     SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_MEM_LOW_PWR_MODE, mask_sh),\
0641     SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_MODE_CURRENT, mask_sh),\
0642     SF(CUR_VUPDATE_LOCK_SET0, CUR_VUPDATE_LOCK_SET, mask_sh)
0643 
0644 
0645 #define MPC_REG_FIELD_LIST_DCN3_0(type) \
0646     MPC_REG_FIELD_LIST_DCN2_0(type) \
0647     type MPC_DWB0_MUX;\
0648     type MPC_DWB0_MUX_STATUS;\
0649     type MPC_OUT_RATE_CONTROL;\
0650     type MPC_OUT_RATE_CONTROL_DISABLE;\
0651     type MPC_OUT_FLOW_CONTROL_MODE;\
0652     type MPC_OUT_FLOW_CONTROL_COUNT; \
0653     type MPCC_GAMUT_REMAP_MODE; \
0654     type MPCC_GAMUT_REMAP_MODE_CURRENT;\
0655     type MPCC_GAMUT_REMAP_COEF_FORMAT; \
0656     type MPCC_GAMUT_REMAP_C11_A; \
0657     type MPCC_GAMUT_REMAP_C12_A; \
0658     type MPC_RMU0_MUX; \
0659     type MPC_RMU1_MUX; \
0660     type MPC_RMU0_MUX_STATUS; \
0661     type MPC_RMU1_MUX_STATUS; \
0662     type MPC_RMU0_MEM_PWR_FORCE;\
0663     type MPC_RMU0_MEM_PWR_DIS;\
0664     type MPC_RMU0_MEM_LOW_PWR_MODE;\
0665     type MPC_RMU0_SHAPER_MEM_PWR_STATE;\
0666     type MPC_RMU0_3DLUT_MEM_PWR_STATE;\
0667     type MPC_RMU1_MEM_PWR_FORCE;\
0668     type MPC_RMU1_MEM_PWR_DIS;\
0669     type MPC_RMU1_MEM_LOW_PWR_MODE;\
0670     type MPC_RMU1_SHAPER_MEM_PWR_STATE;\
0671     type MPC_RMU1_3DLUT_MEM_PWR_STATE;\
0672     type MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B; \
0673     type MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B;\
0674     type MPCC_OGAM_RAMA_OFFSET_B;\
0675     type MPCC_OGAM_RAMA_OFFSET_G;\
0676     type MPCC_OGAM_RAMA_OFFSET_R;\
0677     type MPCC_OGAM_SELECT; \
0678     type MPCC_OGAM_PWL_DISABLE; \
0679     type MPCC_OGAM_MODE_CURRENT; \
0680     type MPCC_OGAM_SELECT_CURRENT; \
0681     type MPCC_OGAM_LUT_WRITE_COLOR_MASK; \
0682     type MPCC_OGAM_LUT_READ_COLOR_SEL; \
0683     type MPCC_OGAM_LUT_READ_DBG; \
0684     type MPCC_OGAM_LUT_HOST_SEL; \
0685     type MPCC_OGAM_LUT_CONFIG_MODE; \
0686     type MPCC_OGAM_LUT_STATUS; \
0687     type MPCC_OGAM_RAMA_START_BASE_CNTL_B;\
0688     type MPCC_OGAM_MEM_LOW_PWR_MODE;\
0689     type MPCC_OGAM_MEM_PWR_STATE;\
0690     type MPC_RMU_3DLUT_MODE; \
0691     type MPC_RMU_3DLUT_SIZE; \
0692     type MPC_RMU_3DLUT_MODE_CURRENT; \
0693     type MPC_RMU_3DLUT_WRITE_EN_MASK;\
0694     type MPC_RMU_3DLUT_RAM_SEL;\
0695     type MPC_RMU_3DLUT_30BIT_EN;\
0696     type MPC_RMU_3DLUT_CONFIG_STATUS;\
0697     type MPC_RMU_3DLUT_READ_SEL;\
0698     type MPC_RMU_3DLUT_INDEX;\
0699     type MPC_RMU_3DLUT_DATA0;\
0700     type MPC_RMU_3DLUT_DATA1;\
0701     type MPC_RMU_3DLUT_DATA_30BIT;\
0702     type MPC_RMU_SHAPER_LUT_MODE;\
0703     type MPC_RMU_SHAPER_LUT_MODE_CURRENT;\
0704     type MPC_RMU_SHAPER_OFFSET_R;\
0705     type MPC_RMU_SHAPER_OFFSET_G;\
0706     type MPC_RMU_SHAPER_OFFSET_B;\
0707     type MPC_RMU_SHAPER_SCALE_R;\
0708     type MPC_RMU_SHAPER_SCALE_G;\
0709     type MPC_RMU_SHAPER_SCALE_B;\
0710     type MPC_RMU_SHAPER_LUT_INDEX;\
0711     type MPC_RMU_SHAPER_LUT_DATA;\
0712     type MPC_RMU_SHAPER_LUT_WRITE_EN_MASK;\
0713     type MPC_RMU_SHAPER_LUT_WRITE_SEL;\
0714     type MPC_RMU_SHAPER_CONFIG_STATUS;\
0715     type MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B;\
0716     type MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B;\
0717     type MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B;\
0718     type MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B;\
0719     type MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET;\
0720     type MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS;\
0721     type MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET;\
0722     type MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS;\
0723     type MPC_RMU_SHAPER_MODE_CURRENT
0724 
0725 #define MPC_REG_FIELD_LIST_DCN32(type) \
0726     type MPCC_MOVABLE_CM_LOCATION_CNTL;\
0727     type MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT;\
0728     type MPCC_MCM_SHAPER_MEM_PWR_FORCE;\
0729     type MPCC_MCM_SHAPER_MEM_PWR_DIS;\
0730     type MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE;\
0731     type MPCC_MCM_3DLUT_MEM_PWR_FORCE;\
0732     type MPCC_MCM_3DLUT_MEM_PWR_DIS;\
0733     type MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE;\
0734     type MPCC_MCM_1DLUT_MEM_PWR_FORCE;\
0735     type MPCC_MCM_1DLUT_MEM_PWR_DIS;\
0736     type MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE;\
0737     type MPCC_MCM_SHAPER_MEM_PWR_STATE;\
0738     type MPCC_MCM_3DLUT_MEM_PWR_STATE;\
0739     type MPCC_MCM_1DLUT_MEM_PWR_STATE;\
0740     type MPCC_MCM_3DLUT_MODE; \
0741     type MPCC_MCM_3DLUT_SIZE; \
0742     type MPCC_MCM_3DLUT_MODE_CURRENT; \
0743     type MPCC_MCM_3DLUT_WRITE_EN_MASK;\
0744     type MPCC_MCM_3DLUT_RAM_SEL;\
0745     type MPCC_MCM_3DLUT_30BIT_EN;\
0746     type MPCC_MCM_3DLUT_CONFIG_STATUS;\
0747     type MPCC_MCM_3DLUT_READ_SEL;\
0748     type MPCC_MCM_3DLUT_INDEX;\
0749     type MPCC_MCM_3DLUT_DATA0;\
0750     type MPCC_MCM_3DLUT_DATA1;\
0751     type MPCC_MCM_3DLUT_DATA_30BIT;\
0752     type MPCC_MCM_SHAPER_LUT_MODE;\
0753     type MPCC_MCM_SHAPER_MODE_CURRENT;\
0754     type MPCC_MCM_SHAPER_OFFSET_R;\
0755     type MPCC_MCM_SHAPER_OFFSET_G;\
0756     type MPCC_MCM_SHAPER_OFFSET_B;\
0757     type MPCC_MCM_SHAPER_SCALE_R;\
0758     type MPCC_MCM_SHAPER_SCALE_G;\
0759     type MPCC_MCM_SHAPER_SCALE_B;\
0760     type MPCC_MCM_SHAPER_LUT_INDEX;\
0761     type MPCC_MCM_SHAPER_LUT_DATA;\
0762     type MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK;\
0763     type MPCC_MCM_SHAPER_LUT_WRITE_SEL;\
0764     type MPCC_MCM_SHAPER_CONFIG_STATUS;\
0765     type MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B;\
0766     type MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B;\
0767     type MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B;\
0768     type MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B;\
0769     type MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET;\
0770     type MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS;\
0771     type MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET;\
0772     type MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS; \
0773     type MPCC_MCM_1DLUT_MODE;\
0774     type MPCC_MCM_1DLUT_SELECT;\
0775     type MPCC_MCM_1DLUT_PWL_DISABLE;\
0776     type MPCC_MCM_1DLUT_MODE_CURRENT;\
0777     type MPCC_MCM_1DLUT_SELECT_CURRENT;\
0778     type MPCC_MCM_1DLUT_LUT_INDEX;\
0779     type MPCC_MCM_1DLUT_LUT_DATA;\
0780     type MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK;\
0781     type MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL;\
0782     type MPCC_MCM_1DLUT_LUT_READ_DBG;\
0783     type MPCC_MCM_1DLUT_LUT_HOST_SEL;\
0784     type MPCC_MCM_1DLUT_LUT_CONFIG_MODE;\
0785     type MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B;\
0786     type MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B;\
0787     type MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B;\
0788     type MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B;\
0789     type MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B;\
0790     type MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B;\
0791     type MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B;\
0792     type MPCC_MCM_1DLUT_RAMA_OFFSET_B;\
0793     type MPCC_MCM_1DLUT_RAMA_OFFSET_G;\
0794     type MPCC_MCM_1DLUT_RAMA_OFFSET_R;\
0795     type MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET;\
0796     type MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS;\
0797     type MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET;\
0798     type MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS
0799 
0800 
0801 #define MPC_COMMON_MASK_SH_LIST_DCN303(mask_sh) \
0802     MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh),\
0803     SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
0804     SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\
0805     SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\
0806     SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\
0807     SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\
0808     SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
0809     SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\
0810     SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\
0811     SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\
0812     SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\
0813     SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\
0814     SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_LOW_PWR_MODE, mask_sh),\
0815     SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_STATE, mask_sh),\
0816     SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_MODE, mask_sh),\
0817     SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MAX_R_CR, mask_sh),\
0818     SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MIN_R_CR, mask_sh),\
0819     SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MAX_G_Y, mask_sh),\
0820     SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MIN_G_Y, mask_sh),\
0821     SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\
0822     SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh),\
0823     SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE, mask_sh),\
0824     SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE_CURRENT, mask_sh),\
0825     SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_GAMUT_REMAP_COEF_FORMAT, mask_sh),\
0826     SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C11_A, mask_sh),\
0827     SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C12_A, mask_sh),\
0828     SF(MPC_DWB0_MUX, MPC_DWB0_MUX, mask_sh),\
0829     SF(MPC_DWB0_MUX, MPC_DWB0_MUX_STATUS, mask_sh),\
0830     SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL, mask_sh),\
0831     SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL_DISABLE, mask_sh),\
0832     SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_MODE, mask_sh),\
0833     SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT, mask_sh), \
0834     SF(MPC_RMU_CONTROL, MPC_RMU0_MUX, mask_sh), \
0835     SF(MPC_RMU_CONTROL, MPC_RMU0_MUX_STATUS, mask_sh), \
0836     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\
0837     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
0838     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\
0839     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
0840     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\
0841     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_B, mask_sh),\
0842     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh),\
0843     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B, mask_sh),\
0844     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B, mask_sh),\
0845     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_B, mask_sh),\
0846     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\
0847     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B, MPCC_OGAM_RAMA_OFFSET_B, mask_sh),\
0848     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G, MPCC_OGAM_RAMA_OFFSET_G, mask_sh),\
0849     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R, MPCC_OGAM_RAMA_OFFSET_R, mask_sh),\
0850     SF(MPCC_OGAM0_MPCC_OGAM_LUT_INDEX, MPCC_OGAM_LUT_INDEX, mask_sh),\
0851     SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE, mask_sh),\
0852     SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT, mask_sh),\
0853     SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_PWL_DISABLE, mask_sh),\
0854     SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE_CURRENT, mask_sh),\
0855     SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT_CURRENT, mask_sh),\
0856     SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_WRITE_COLOR_MASK, mask_sh),\
0857     SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_COLOR_SEL, mask_sh),\
0858     SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_DBG, mask_sh),\
0859     SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_HOST_SEL, mask_sh),\
0860     SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_CONFIG_MODE, mask_sh),\
0861     /*SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_STATUS, mask_sh),*/\
0862     SF(MPCC_OGAM0_MPCC_OGAM_LUT_DATA, MPCC_OGAM_LUT_DATA, mask_sh),\
0863     SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_MODE, mask_sh),\
0864     SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_SIZE, mask_sh),\
0865     /*SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_MODE_CURRENT, mask_sh),*/\
0866     SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_WRITE_EN_MASK, mask_sh),\
0867     SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_RAM_SEL, mask_sh),\
0868     SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_30BIT_EN, mask_sh),\
0869     /*SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_CONFIG_STATUS, mask_sh),*/\
0870     SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_READ_SEL, mask_sh),\
0871     SF(MPC_RMU0_3DLUT_INDEX, MPC_RMU_3DLUT_INDEX, mask_sh),\
0872     SF(MPC_RMU0_3DLUT_DATA, MPC_RMU_3DLUT_DATA0, mask_sh),\
0873     SF(MPC_RMU0_3DLUT_DATA, MPC_RMU_3DLUT_DATA1, mask_sh),\
0874     SF(MPC_RMU0_3DLUT_DATA_30BIT, MPC_RMU_3DLUT_DATA_30BIT, mask_sh),\
0875     SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_LUT_MODE, mask_sh),\
0876     /*SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_LUT_MODE_CURRENT, mask_sh),*/\
0877     SF(MPC_RMU0_SHAPER_OFFSET_R, MPC_RMU_SHAPER_OFFSET_R, mask_sh),\
0878     SF(MPC_RMU0_SHAPER_OFFSET_G, MPC_RMU_SHAPER_OFFSET_G, mask_sh),\
0879     SF(MPC_RMU0_SHAPER_OFFSET_B, MPC_RMU_SHAPER_OFFSET_B, mask_sh),\
0880     SF(MPC_RMU0_SHAPER_SCALE_R, MPC_RMU_SHAPER_SCALE_R, mask_sh),\
0881     SF(MPC_RMU0_SHAPER_SCALE_G_B, MPC_RMU_SHAPER_SCALE_G, mask_sh),\
0882     SF(MPC_RMU0_SHAPER_SCALE_G_B, MPC_RMU_SHAPER_SCALE_B, mask_sh),\
0883     SF(MPC_RMU0_SHAPER_LUT_INDEX, MPC_RMU_SHAPER_LUT_INDEX, mask_sh),\
0884     SF(MPC_RMU0_SHAPER_LUT_DATA, MPC_RMU_SHAPER_LUT_DATA, mask_sh),\
0885     SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_LUT_WRITE_EN_MASK, mask_sh),\
0886     SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_LUT_WRITE_SEL, mask_sh),\
0887     /*SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_CONFIG_STATUS, mask_sh),*/\
0888     SF(MPC_RMU0_SHAPER_RAMA_START_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B, mask_sh),\
0889     SF(MPC_RMU0_SHAPER_RAMA_START_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\
0890     SF(MPC_RMU0_SHAPER_RAMA_END_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B, mask_sh),\
0891     SF(MPC_RMU0_SHAPER_RAMA_END_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B, mask_sh),\
0892     SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\
0893     SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
0894     SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\
0895     SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
0896     SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_PWR_FORCE, mask_sh),\
0897     SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_PWR_DIS, mask_sh),\
0898     SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_SHAPER_MEM_PWR_STATE, mask_sh),\
0899     SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_3DLUT_MEM_PWR_STATE, mask_sh),\
0900     SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_LOW_PWR_MODE, mask_sh),\
0901     SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_MODE_CURRENT, mask_sh),\
0902     SF(CUR_VUPDATE_LOCK_SET0, CUR_VUPDATE_LOCK_SET, mask_sh)
0903 
0904 #define MPC_REG_FIELD_LIST_DCN3_03(type) \
0905     MPC_REG_FIELD_LIST_DCN2_0(type) \
0906     type MPC_DWB0_MUX;\
0907     type MPC_DWB0_MUX_STATUS;\
0908     type MPC_OUT_RATE_CONTROL;\
0909     type MPC_OUT_RATE_CONTROL_DISABLE;\
0910     type MPC_OUT_FLOW_CONTROL_MODE;\
0911     type MPC_OUT_FLOW_CONTROL_COUNT; \
0912     type MPCC_GAMUT_REMAP_MODE; \
0913     type MPCC_GAMUT_REMAP_MODE_CURRENT;\
0914     type MPCC_GAMUT_REMAP_COEF_FORMAT; \
0915     type MPCC_GAMUT_REMAP_C11_A; \
0916     type MPCC_GAMUT_REMAP_C12_A; \
0917     type MPC_RMU0_MUX; \
0918     type MPC_RMU0_MUX_STATUS; \
0919     type MPC_RMU0_MEM_PWR_FORCE;\
0920     type MPC_RMU0_MEM_PWR_DIS;\
0921     type MPC_RMU0_MEM_LOW_PWR_MODE;\
0922     type MPC_RMU0_SHAPER_MEM_PWR_STATE;\
0923     type MPC_RMU0_3DLUT_MEM_PWR_STATE;\
0924     type MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B; \
0925     type MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B;\
0926     type MPCC_OGAM_RAMA_OFFSET_B;\
0927     type MPCC_OGAM_RAMA_OFFSET_G;\
0928     type MPCC_OGAM_RAMA_OFFSET_R;\
0929     type MPCC_OGAM_SELECT; \
0930     type MPCC_OGAM_PWL_DISABLE; \
0931     type MPCC_OGAM_MODE_CURRENT; \
0932     type MPCC_OGAM_SELECT_CURRENT; \
0933     type MPCC_OGAM_LUT_WRITE_COLOR_MASK; \
0934     type MPCC_OGAM_LUT_READ_COLOR_SEL; \
0935     type MPCC_OGAM_LUT_READ_DBG; \
0936     type MPCC_OGAM_LUT_HOST_SEL; \
0937     type MPCC_OGAM_LUT_CONFIG_MODE; \
0938     type MPCC_OGAM_LUT_STATUS; \
0939     type MPCC_OGAM_RAMA_START_BASE_CNTL_B;\
0940     type MPCC_OGAM_MEM_LOW_PWR_MODE;\
0941     type MPCC_OGAM_MEM_PWR_STATE;\
0942     type MPC_RMU_3DLUT_MODE; \
0943     type MPC_RMU_3DLUT_SIZE; \
0944     type MPC_RMU_3DLUT_MODE_CURRENT; \
0945     type MPC_RMU_3DLUT_WRITE_EN_MASK;\
0946     type MPC_RMU_3DLUT_RAM_SEL;\
0947     type MPC_RMU_3DLUT_30BIT_EN;\
0948     type MPC_RMU_3DLUT_CONFIG_STATUS;\
0949     type MPC_RMU_3DLUT_READ_SEL;\
0950     type MPC_RMU_3DLUT_INDEX;\
0951     type MPC_RMU_3DLUT_DATA0;\
0952     type MPC_RMU_3DLUT_DATA1;\
0953     type MPC_RMU_3DLUT_DATA_30BIT;\
0954     type MPC_RMU_SHAPER_LUT_MODE;\
0955     type MPC_RMU_SHAPER_LUT_MODE_CURRENT;\
0956     type MPC_RMU_SHAPER_OFFSET_R;\
0957     type MPC_RMU_SHAPER_OFFSET_G;\
0958     type MPC_RMU_SHAPER_OFFSET_B;\
0959     type MPC_RMU_SHAPER_SCALE_R;\
0960     type MPC_RMU_SHAPER_SCALE_G;\
0961     type MPC_RMU_SHAPER_SCALE_B;\
0962     type MPC_RMU_SHAPER_LUT_INDEX;\
0963     type MPC_RMU_SHAPER_LUT_DATA;\
0964     type MPC_RMU_SHAPER_LUT_WRITE_EN_MASK;\
0965     type MPC_RMU_SHAPER_LUT_WRITE_SEL;\
0966     type MPC_RMU_SHAPER_CONFIG_STATUS;\
0967     type MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B;\
0968     type MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B;\
0969     type MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B;\
0970     type MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B;\
0971     type MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET;\
0972     type MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS;\
0973     type MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET;\
0974     type MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS;\
0975     type MPC_RMU_SHAPER_MODE_CURRENT
0976 
0977 struct dcn30_mpc_registers {
0978     MPC_REG_VARIABLE_LIST_DCN3_0;
0979     MPC_REG_VARIABLE_LIST_DCN32;
0980 };
0981 
0982 struct dcn30_mpc_shift {
0983     MPC_REG_FIELD_LIST_DCN3_0(uint8_t);
0984     MPC_REG_FIELD_LIST_DCN32(uint8_t);
0985 };
0986 
0987 struct dcn30_mpc_mask {
0988     MPC_REG_FIELD_LIST_DCN3_0(uint32_t);
0989     MPC_REG_FIELD_LIST_DCN32(uint32_t);
0990 };
0991 
0992 struct dcn30_mpc {
0993     struct mpc base;
0994 
0995     int mpcc_in_use_mask;
0996     int num_mpcc;
0997     const struct dcn30_mpc_registers *mpc_regs;
0998     const struct dcn30_mpc_shift *mpc_shift;
0999     const struct dcn30_mpc_mask *mpc_mask;
1000     int num_rmu;
1001 };
1002 
1003 void dcn30_mpc_construct(struct dcn30_mpc *mpc30,
1004     struct dc_context *ctx,
1005     const struct dcn30_mpc_registers *mpc_regs,
1006     const struct dcn30_mpc_shift *mpc_shift,
1007     const struct dcn30_mpc_mask *mpc_mask,
1008     int num_mpcc,
1009     int num_rmu);
1010 
1011 bool mpc3_program_shaper(
1012         struct mpc *mpc,
1013         const struct pwl_params *params,
1014         uint32_t rmu_idx);
1015 
1016 bool mpc3_program_3dlut(
1017         struct mpc *mpc,
1018         const struct tetrahedral_params *params,
1019         int rmu_idx);
1020 
1021 uint32_t mpcc3_acquire_rmu(struct mpc *mpc,
1022         int mpcc_id, int rmu_idx);
1023 
1024 void mpc3_set_denorm(
1025     struct mpc *mpc,
1026     int opp_id,
1027     enum dc_color_depth output_depth);
1028 
1029 void mpc3_set_denorm_clamp(
1030     struct mpc *mpc,
1031     int opp_id,
1032     struct mpc_denorm_clamp denorm_clamp);
1033 
1034 void mpc3_set_output_csc(
1035     struct mpc *mpc,
1036     int opp_id,
1037     const uint16_t *regval,
1038     enum mpc_output_csc_mode ocsc_mode);
1039 
1040 void mpc3_set_ocsc_default(
1041     struct mpc *mpc,
1042     int opp_id,
1043     enum dc_color_space color_space,
1044     enum mpc_output_csc_mode ocsc_mode);
1045 
1046 void mpc3_set_output_gamma(
1047     struct mpc *mpc,
1048     int mpcc_id,
1049     const struct pwl_params *params);
1050 
1051 uint32_t mpc3_get_rmu_mux_status(
1052     struct mpc *mpc,
1053     int rmu_idx);
1054 
1055 void mpc3_set_gamut_remap(
1056     struct mpc *mpc,
1057     int mpcc_id,
1058     const struct mpc_grph_gamut_adjustment *adjust);
1059 
1060 void mpc3_set_rmu_mux(
1061     struct mpc *mpc,
1062     int rmu_idx,
1063     int value);
1064 
1065 void mpc3_set_dwb_mux(
1066     struct mpc *mpc,
1067     int dwb_id,
1068     int mpcc_id);
1069 
1070 void mpc3_disable_dwb_mux(
1071     struct mpc *mpc,
1072     int dwb_id);
1073 
1074 bool mpc3_is_dwb_idle(
1075     struct mpc *mpc,
1076     int dwb_id);
1077 
1078 void mpc3_set_out_rate_control(
1079     struct mpc *mpc,
1080     int opp_id,
1081     bool enable,
1082     bool rate_2x_mode,
1083     struct mpc_dwb_flow_control *flow_control);
1084 
1085 void mpc3_power_on_ogam_lut(
1086     struct mpc *mpc, int mpcc_id,
1087     bool power_on);
1088 
1089 void mpc3_init_mpcc(struct mpcc *mpcc, int mpcc_inst);
1090 
1091 enum dc_lut_mode mpc3_get_ogam_current(
1092     struct mpc *mpc,
1093     int mpcc_id);
1094 
1095 #endif
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