dc/dcn30/dcn30_hubp.c

0001 /*
0002  * Copyright 2020 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include "dcn30_hubp.h"
0027
0028 #include "dm_services.h"
0029 #include "dce_calcs.h"
0030 #include "reg_helper.h"
0031 #include "basics/conversion.h"
0032 #include "dcn20/dcn20_hubp.h"
0033 #include "dcn21/dcn21_hubp.h"
0034
0035 #define REG(reg)\
0036     hubp2->hubp_regs->reg
0037
0038 #define CTX \
0039     hubp2->base.ctx
0040
0041 #undef FN
0042 #define FN(reg_name, field_name) \
0043     hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name
0044
0045 void hubp3_set_vm_system_aperture_settings(struct hubp *hubp,
0046         struct vm_system_aperture_param *apt)
0047 {
0048     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
0049
0050     PHYSICAL_ADDRESS_LOC mc_vm_apt_default;
0051     PHYSICAL_ADDRESS_LOC mc_vm_apt_low;
0052     PHYSICAL_ADDRESS_LOC mc_vm_apt_high;
0053
0054     // The format of default addr is 48:12 of the 48 bit addr
0055     mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12;
0056
0057     // The format of high/low are 48:18 of the 48 bit addr
0058     mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18;
0059     mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18;
0060
0061     REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0,
0062             MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part);
0063
0064     REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0,
0065             MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part);
0066
0067     REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
0068             ENABLE_L1_TLB, 1,
0069             SYSTEM_ACCESS_MODE, 0x3);
0070 }
0071
0072 bool hubp3_program_surface_flip_and_addr(
0073     struct hubp *hubp,
0074     const struct dc_plane_address *address,
0075     bool flip_immediate)
0076 {
0077     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
0078
0079     //program flip type
0080     REG_UPDATE(DCSURF_FLIP_CONTROL,
0081             SURFACE_FLIP_TYPE, flip_immediate);
0082
0083     // Program VMID reg
0084     if (flip_immediate == 0)
0085         REG_UPDATE(VMID_SETTINGS_0,
0086             VMID, address->vmid);
0087
0088     if (address->type == PLN_ADDR_TYPE_GRPH_STEREO) {
0089         REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0);
0090         REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1);
0091
0092     } else {
0093         // turn off stereo if not in stereo
0094         REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0);
0095         REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0);
0096     }
0097
0098     /* HW automatically latch rest of address register on write to
0099      * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used
0100      *
0101      * program high first and then the low addr, order matters!
0102      */
0103     switch (address->type) {
0104     case PLN_ADDR_TYPE_GRAPHICS:
0105         /* DCN1.0 does not support const color
0106          * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1
0107          * base on address->grph.dcc_const_color
0108          * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma
0109          * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma
0110          */
0111
0112         if (address->grph.addr.quad_part == 0)
0113             break;
0114
0115         REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
0116                 PRIMARY_SURFACE_TMZ, address->tmz_surface,
0117                 PRIMARY_META_SURFACE_TMZ, address->tmz_surface);
0118
0119         if (address->grph.meta_addr.quad_part != 0) {
0120             REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
0121                     PRIMARY_META_SURFACE_ADDRESS_HIGH,
0122                     address->grph.meta_addr.high_part);
0123
0124             REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
0125                     PRIMARY_META_SURFACE_ADDRESS,
0126                     address->grph.meta_addr.low_part);
0127         }
0128
0129         REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
0130                 PRIMARY_SURFACE_ADDRESS_HIGH,
0131                 address->grph.addr.high_part);
0132
0133         REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
0134                 PRIMARY_SURFACE_ADDRESS,
0135                 address->grph.addr.low_part);
0136         break;
0137     case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
0138         if (address->video_progressive.luma_addr.quad_part == 0
0139                 || address->video_progressive.chroma_addr.quad_part == 0)
0140             break;
0141
0142         REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
0143                 PRIMARY_SURFACE_TMZ, address->tmz_surface,
0144                 PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
0145                 PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
0146                 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface);
0147
0148         if (address->video_progressive.luma_meta_addr.quad_part != 0) {
0149             REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
0150                     PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
0151                     address->video_progressive.chroma_meta_addr.high_part);
0152
0153             REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
0154                     PRIMARY_META_SURFACE_ADDRESS_C,
0155                     address->video_progressive.chroma_meta_addr.low_part);
0156
0157             REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
0158                     PRIMARY_META_SURFACE_ADDRESS_HIGH,
0159                     address->video_progressive.luma_meta_addr.high_part);
0160
0161             REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
0162                     PRIMARY_META_SURFACE_ADDRESS,
0163                     address->video_progressive.luma_meta_addr.low_part);
0164         }
0165
0166         REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
0167                 PRIMARY_SURFACE_ADDRESS_HIGH_C,
0168                 address->video_progressive.chroma_addr.high_part);
0169
0170         REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
0171                 PRIMARY_SURFACE_ADDRESS_C,
0172                 address->video_progressive.chroma_addr.low_part);
0173
0174         REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
0175                 PRIMARY_SURFACE_ADDRESS_HIGH,
0176                 address->video_progressive.luma_addr.high_part);
0177
0178         REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
0179                 PRIMARY_SURFACE_ADDRESS,
0180                 address->video_progressive.luma_addr.low_part);
0181         break;
0182     case PLN_ADDR_TYPE_GRPH_STEREO:
0183         if (address->grph_stereo.left_addr.quad_part == 0)
0184             break;
0185         if (address->grph_stereo.right_addr.quad_part == 0)
0186             break;
0187
0188         REG_UPDATE_8(DCSURF_SURFACE_CONTROL,
0189                 PRIMARY_SURFACE_TMZ, address->tmz_surface,
0190                 PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
0191                 PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
0192                 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface,
0193                 SECONDARY_SURFACE_TMZ, address->tmz_surface,
0194                 SECONDARY_SURFACE_TMZ_C, address->tmz_surface,
0195                 SECONDARY_META_SURFACE_TMZ, address->tmz_surface,
0196                 SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface);
0197
0198         if (address->grph_stereo.right_meta_addr.quad_part != 0) {
0199
0200             REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, 0,
0201                 SECONDARY_META_SURFACE_ADDRESS_HIGH_C,
0202                 address->grph_stereo.right_alpha_meta_addr.high_part);
0203
0204             REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, 0,
0205                 SECONDARY_META_SURFACE_ADDRESS_C,
0206                 address->grph_stereo.right_alpha_meta_addr.low_part);
0207
0208             REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0,
0209                     SECONDARY_META_SURFACE_ADDRESS_HIGH,
0210                     address->grph_stereo.right_meta_addr.high_part);
0211
0212             REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0,
0213                     SECONDARY_META_SURFACE_ADDRESS,
0214                     address->grph_stereo.right_meta_addr.low_part);
0215         }
0216         if (address->grph_stereo.left_meta_addr.quad_part != 0) {
0217
0218             REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
0219                 PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
0220                 address->grph_stereo.left_alpha_meta_addr.high_part);
0221
0222             REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
0223                 PRIMARY_META_SURFACE_ADDRESS_C,
0224                 address->grph_stereo.left_alpha_meta_addr.low_part);
0225
0226             REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
0227                     PRIMARY_META_SURFACE_ADDRESS_HIGH,
0228                     address->grph_stereo.left_meta_addr.high_part);
0229
0230             REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
0231                     PRIMARY_META_SURFACE_ADDRESS,
0232                     address->grph_stereo.left_meta_addr.low_part);
0233         }
0234
0235         REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, 0,
0236                 SECONDARY_SURFACE_ADDRESS_HIGH_C,
0237                 address->grph_stereo.right_alpha_addr.high_part);
0238
0239         REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_C, 0,
0240                 SECONDARY_SURFACE_ADDRESS_C,
0241                 address->grph_stereo.right_alpha_addr.low_part);
0242
0243         REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0,
0244                 SECONDARY_SURFACE_ADDRESS_HIGH,
0245                 address->grph_stereo.right_addr.high_part);
0246
0247         REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0,
0248                 SECONDARY_SURFACE_ADDRESS,
0249                 address->grph_stereo.right_addr.low_part);
0250
0251         REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
0252                 PRIMARY_SURFACE_ADDRESS_HIGH_C,
0253                 address->grph_stereo.left_alpha_addr.high_part);
0254
0255         REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
0256                 PRIMARY_SURFACE_ADDRESS_C,
0257                 address->grph_stereo.left_alpha_addr.low_part);
0258
0259         REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
0260                 PRIMARY_SURFACE_ADDRESS_HIGH,
0261                 address->grph_stereo.left_addr.high_part);
0262
0263         REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
0264                 PRIMARY_SURFACE_ADDRESS,
0265                 address->grph_stereo.left_addr.low_part);
0266         break;
0267     case PLN_ADDR_TYPE_RGBEA:
0268         if (address->rgbea.addr.quad_part == 0
0269                 || address->rgbea.alpha_addr.quad_part == 0)
0270             break;
0271
0272         REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
0273                 PRIMARY_SURFACE_TMZ, address->tmz_surface,
0274                 PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
0275                 PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
0276                 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface);
0277
0278         if (address->rgbea.meta_addr.quad_part != 0) {
0279
0280             REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
0281                     PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
0282                     address->rgbea.alpha_meta_addr.high_part);
0283
0284             REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
0285                     PRIMARY_META_SURFACE_ADDRESS_C,
0286                     address->rgbea.alpha_meta_addr.low_part);
0287
0288             REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
0289                     PRIMARY_META_SURFACE_ADDRESS_HIGH,
0290                     address->rgbea.meta_addr.high_part);
0291
0292             REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
0293                     PRIMARY_META_SURFACE_ADDRESS,
0294                     address->rgbea.meta_addr.low_part);
0295         }
0296
0297         REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
0298                 PRIMARY_SURFACE_ADDRESS_HIGH_C,
0299                 address->rgbea.alpha_addr.high_part);
0300
0301         REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
0302                 PRIMARY_SURFACE_ADDRESS_C,
0303                 address->rgbea.alpha_addr.low_part);
0304
0305         REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
0306                 PRIMARY_SURFACE_ADDRESS_HIGH,
0307                 address->rgbea.addr.high_part);
0308
0309         REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
0310                 PRIMARY_SURFACE_ADDRESS,
0311                 address->rgbea.addr.low_part);
0312         break;
0313     default:
0314         BREAK_TO_DEBUGGER();
0315         break;
0316     }
0317
0318     hubp->request_address = *address;
0319
0320     return true;
0321 }
0322
0323 static void hubp3_program_tiling(
0324     struct dcn20_hubp *hubp2,
0325     const union dc_tiling_info *info,
0326     const enum surface_pixel_format pixel_format)
0327 {
0328     REG_UPDATE_4(DCSURF_ADDR_CONFIG,
0329         NUM_PIPES, log_2(info->gfx9.num_pipes),
0330         PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
0331         MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags),
0332         NUM_PKRS, log_2(info->gfx9.num_pkrs));
0333
0334     REG_UPDATE_3(DCSURF_TILING_CONFIG,
0335             SW_MODE, info->gfx9.swizzle,
0336             META_LINEAR, info->gfx9.meta_linear,
0337             PIPE_ALIGNED, info->gfx9.pipe_aligned);
0338
0339 }
0340
0341 void hubp3_dcc_control(struct hubp *hubp, bool enable,
0342         enum hubp_ind_block_size blk_size)
0343 {
0344     uint32_t dcc_en = enable ? 1 : 0;
0345     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
0346
0347     REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
0348             PRIMARY_SURFACE_DCC_EN, dcc_en,
0349             PRIMARY_SURFACE_DCC_IND_BLK, blk_size,
0350             SECONDARY_SURFACE_DCC_EN, dcc_en,
0351             SECONDARY_SURFACE_DCC_IND_BLK, blk_size);
0352 }
0353
0354 void hubp3_dcc_control_sienna_cichlid(struct hubp *hubp,
0355         struct dc_plane_dcc_param *dcc)
0356 {
0357     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
0358
0359     REG_UPDATE_6(DCSURF_SURFACE_CONTROL,
0360         PRIMARY_SURFACE_DCC_EN, dcc->enable,
0361         PRIMARY_SURFACE_DCC_IND_BLK, dcc->dcc_ind_blk,
0362         PRIMARY_SURFACE_DCC_IND_BLK_C, dcc->dcc_ind_blk_c,
0363         SECONDARY_SURFACE_DCC_EN, dcc->enable,
0364         SECONDARY_SURFACE_DCC_IND_BLK, dcc->dcc_ind_blk,
0365         SECONDARY_SURFACE_DCC_IND_BLK_C, dcc->dcc_ind_blk_c);
0366 }
0367
0368 void hubp3_dmdata_set_attributes(
0369         struct hubp *hubp,
0370         const struct dc_dmdata_attributes *attr)
0371 {
0372     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
0373
0374     /*always HW mode */
0375     REG_UPDATE(DMDATA_CNTL,
0376             DMDATA_MODE, 1);
0377
0378     /* for DMDATA flip, need to use SURFACE_UPDATE_LOCK */
0379     REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 1);
0380
0381     /* toggle DMDATA_UPDATED and set repeat and size */
0382     REG_UPDATE(DMDATA_CNTL,
0383             DMDATA_UPDATED, 0);
0384     REG_UPDATE_3(DMDATA_CNTL,
0385             DMDATA_UPDATED, 1,
0386             DMDATA_REPEAT, attr->dmdata_repeat,
0387             DMDATA_SIZE, attr->dmdata_size);
0388
0389     /* set DMDATA address */
0390     REG_WRITE(DMDATA_ADDRESS_LOW, attr->address.low_part);
0391     REG_UPDATE(DMDATA_ADDRESS_HIGH,
0392             DMDATA_ADDRESS_HIGH, attr->address.high_part);
0393
0394     REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 0);
0395
0396 }
0397
0398
0399 void hubp3_program_surface_config(
0400     struct hubp *hubp,
0401     enum surface_pixel_format format,
0402     union dc_tiling_info *tiling_info,
0403     struct plane_size *plane_size,
0404     enum dc_rotation_angle rotation,
0405     struct dc_plane_dcc_param *dcc,
0406     bool horizontal_mirror,
0407     unsigned int compat_level)
0408 {
0409     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
0410
0411     hubp3_dcc_control_sienna_cichlid(hubp, dcc);
0412     hubp3_program_tiling(hubp2, tiling_info, format);
0413     hubp2_program_size(hubp, format, plane_size, dcc);
0414     hubp2_program_rotation(hubp, rotation, horizontal_mirror);
0415     hubp2_program_pixel_format(hubp, format);
0416 }
0417
0418 static void hubp3_program_deadline(
0419         struct hubp *hubp,
0420         struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
0421         struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
0422 {
0423     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
0424
0425     hubp2_program_deadline(hubp, dlg_attr, ttu_attr);
0426     REG_UPDATE(DCN_DMDATA_VM_CNTL,
0427             REFCYC_PER_VM_DMDATA, dlg_attr->refcyc_per_vm_dmdata);
0428 }
0429
0430 void hubp3_read_state(struct hubp *hubp)
0431 {
0432     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
0433     struct dcn_hubp_state *s = &hubp2->state;
0434     struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
0435
0436     hubp2_read_state_common(hubp);
0437
0438     REG_GET_7(DCHUBP_REQ_SIZE_CONFIG,
0439         CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,
0440         MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size,
0441         META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size,
0442         MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size,
0443         DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size,
0444         SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height,
0445         PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);
0446
0447     REG_GET_7(DCHUBP_REQ_SIZE_CONFIG_C,
0448         CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size,
0449         MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size,
0450         META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size,
0451         MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size,
0452         DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size,
0453         SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height,
0454         PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear);
0455
0456 }
0457
0458 void hubp3_setup(
0459         struct hubp *hubp,
0460         struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
0461         struct _vcs_dpi_display_ttu_regs_st *ttu_attr,
0462         struct _vcs_dpi_display_rq_regs_st *rq_regs,
0463         struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
0464 {
0465     /* otg is locked when this func is called. Register are double buffered.
0466      * disable the requestors is not needed
0467      */
0468     hubp2_vready_at_or_After_vsync(hubp, pipe_dest);
0469     hubp21_program_requestor(hubp, rq_regs);
0470     hubp3_program_deadline(hubp, dlg_attr, ttu_attr);
0471 }
0472
0473 void hubp3_init(struct hubp *hubp)
0474 {
0475     // DEDCN21-133: Inconsistent row starting line for flip between DPTE and Meta
0476     // This is a chicken bit to enable the ECO fix.
0477
0478     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
0479     //hubp[i].HUBPREQ_DEBUG.HUBPREQ_DEBUG[26] = 1;
0480     REG_WRITE(HUBPREQ_DEBUG, 1 << 26);
0481 }
0482
0483 static struct hubp_funcs dcn30_hubp_funcs = {
0484     .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
0485     .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
0486     .hubp_program_surface_flip_and_addr = hubp3_program_surface_flip_and_addr,
0487     .hubp_program_surface_config = hubp3_program_surface_config,
0488     .hubp_is_flip_pending = hubp2_is_flip_pending,
0489     .hubp_setup = hubp3_setup,
0490     .hubp_setup_interdependent = hubp2_setup_interdependent,
0491     .hubp_set_vm_system_aperture_settings = hubp3_set_vm_system_aperture_settings,
0492     .set_blank = hubp2_set_blank,
0493     .set_blank_regs = hubp2_set_blank_regs,
0494     .dcc_control = hubp3_dcc_control,
0495     .mem_program_viewport = min_set_viewport,
0496     .set_cursor_attributes  = hubp2_cursor_set_attributes,
0497     .set_cursor_position    = hubp2_cursor_set_position,
0498     .hubp_clk_cntl = hubp2_clk_cntl,
0499     .hubp_vtg_sel = hubp2_vtg_sel,
0500     .dmdata_set_attributes = hubp3_dmdata_set_attributes,
0501     .dmdata_load = hubp2_dmdata_load,
0502     .dmdata_status_done = hubp2_dmdata_status_done,
0503     .hubp_read_state = hubp3_read_state,
0504     .hubp_clear_underflow = hubp2_clear_underflow,
0505     .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
0506     .hubp_init = hubp3_init,
0507     .hubp_in_blank = hubp1_in_blank,
0508     .hubp_soft_reset = hubp1_soft_reset,
0509     .hubp_set_flip_int = hubp1_set_flip_int,
0510 };
0511
0512 bool hubp3_construct(
0513     struct dcn20_hubp *hubp2,
0514     struct dc_context *ctx,
0515     uint32_t inst,
0516     const struct dcn_hubp2_registers *hubp_regs,
0517     const struct dcn_hubp2_shift *hubp_shift,
0518     const struct dcn_hubp2_mask *hubp_mask)
0519 {
0520     hubp2->base.funcs = &dcn30_hubp_funcs;
0521     hubp2->base.ctx = ctx;
0522     hubp2->hubp_regs = hubp_regs;
0523     hubp2->hubp_shift = hubp_shift;
0524     hubp2->hubp_mask = hubp_mask;
0525     hubp2->base.inst = inst;
0526     hubp2->base.opp_id = OPP_ID_INVALID;
0527     hubp2->base.mpcc_id = 0xf;
0528
0529     return true;
0530 }