dc/dcn30/dcn30_dwb_cm.c

0001 /*
0002  * Copyright 2020 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include "reg_helper.h"
0027 #include "fixed31_32.h"
0028 #include "resource.h"
0029 #include "basics/conversion.h"
0030 #include "dwb.h"
0031 #include "dcn30_dwb.h"
0032 #include "dcn30_cm_common.h"
0033 #include "dcn10/dcn10_cm_common.h"
0034
0035
0036 #define REG(reg)\
0037     dwbc30->dwbc_regs->reg
0038
0039 #define CTX \
0040     dwbc30->base.ctx
0041
0042 #undef FN
0043 #define FN(reg_name, field_name) \
0044     dwbc30->dwbc_shift->field_name, dwbc30->dwbc_mask->field_name
0045
0046 #define TO_DCN30_DWBC(dwbc_base) \
0047     container_of(dwbc_base, struct dcn30_dwbc, base)
0048
0049 static void dwb3_get_reg_field_ogam(struct dcn30_dwbc *dwbc30,
0050     struct dcn3_xfer_func_reg *reg)
0051 {
0052     reg->shifts.field_region_start_base = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_START_BASE_B;
0053     reg->masks.field_region_start_base = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_START_BASE_B;
0054     reg->shifts.field_offset = dwbc30->dwbc_shift->DWB_OGAM_RAMA_OFFSET_B;
0055     reg->masks.field_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_OFFSET_B;
0056
0057     reg->shifts.exp_region0_lut_offset = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;
0058     reg->masks.exp_region0_lut_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;
0059     reg->shifts.exp_region0_num_segments = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
0060     reg->masks.exp_region0_num_segments = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
0061     reg->shifts.exp_region1_lut_offset = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;
0062     reg->masks.exp_region1_lut_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;
0063     reg->shifts.exp_region1_num_segments = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
0064     reg->masks.exp_region1_num_segments = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
0065
0066     reg->shifts.field_region_end = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_END_B;
0067     reg->masks.field_region_end = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_B;
0068     reg->shifts.field_region_end_slope = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B;
0069     reg->masks.field_region_end_slope = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B;
0070     reg->shifts.field_region_end_base = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_END_BASE_B;
0071     reg->masks.field_region_end_base = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_BASE_B;
0072     reg->shifts.field_region_linear_slope = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B;
0073     reg->masks.field_region_linear_slope = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B;
0074     reg->shifts.exp_region_start = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_START_B;
0075     reg->masks.exp_region_start = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_START_B;
0076     reg->shifts.exp_resion_start_segment = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;
0077     reg->masks.exp_resion_start_segment = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;
0078 }
0079
0080 /*program dwb ogam RAM A*/
0081 static void dwb3_program_ogam_luta_settings(
0082     struct dcn30_dwbc *dwbc30,
0083     const struct pwl_params *params)
0084 {
0085     struct dcn3_xfer_func_reg gam_regs;
0086
0087     dwb3_get_reg_field_ogam(dwbc30, &gam_regs);
0088
0089     gam_regs.start_cntl_b = REG(DWB_OGAM_RAMA_START_CNTL_B);
0090     gam_regs.start_cntl_g = REG(DWB_OGAM_RAMA_START_CNTL_G);
0091     gam_regs.start_cntl_r = REG(DWB_OGAM_RAMA_START_CNTL_R);
0092     gam_regs.start_base_cntl_b = REG(DWB_OGAM_RAMA_START_BASE_CNTL_B);
0093     gam_regs.start_base_cntl_g = REG(DWB_OGAM_RAMA_START_BASE_CNTL_G);
0094     gam_regs.start_base_cntl_r = REG(DWB_OGAM_RAMA_START_BASE_CNTL_R);
0095     gam_regs.start_slope_cntl_b = REG(DWB_OGAM_RAMA_START_SLOPE_CNTL_B);
0096     gam_regs.start_slope_cntl_g = REG(DWB_OGAM_RAMA_START_SLOPE_CNTL_G);
0097     gam_regs.start_slope_cntl_r = REG(DWB_OGAM_RAMA_START_SLOPE_CNTL_R);
0098     gam_regs.start_end_cntl1_b = REG(DWB_OGAM_RAMA_END_CNTL1_B);
0099     gam_regs.start_end_cntl2_b = REG(DWB_OGAM_RAMA_END_CNTL2_B);
0100     gam_regs.start_end_cntl1_g = REG(DWB_OGAM_RAMA_END_CNTL1_G);
0101     gam_regs.start_end_cntl2_g = REG(DWB_OGAM_RAMA_END_CNTL2_G);
0102     gam_regs.start_end_cntl1_r = REG(DWB_OGAM_RAMA_END_CNTL1_R);
0103     gam_regs.start_end_cntl2_r = REG(DWB_OGAM_RAMA_END_CNTL2_R);
0104     gam_regs.offset_b = REG(DWB_OGAM_RAMA_OFFSET_B);
0105     gam_regs.offset_g = REG(DWB_OGAM_RAMA_OFFSET_G);
0106     gam_regs.offset_r = REG(DWB_OGAM_RAMA_OFFSET_R);
0107     gam_regs.region_start = REG(DWB_OGAM_RAMA_REGION_0_1);
0108     gam_regs.region_end = REG(DWB_OGAM_RAMA_REGION_32_33);
0109     /*todo*/
0110     cm_helper_program_gamcor_xfer_func(dwbc30->base.ctx, params, &gam_regs);
0111 }
0112
0113 /*program dwb ogam RAM B*/
0114 static void dwb3_program_ogam_lutb_settings(
0115     struct dcn30_dwbc *dwbc30,
0116     const struct pwl_params *params)
0117 {
0118     struct dcn3_xfer_func_reg gam_regs;
0119
0120     dwb3_get_reg_field_ogam(dwbc30, &gam_regs);
0121
0122     gam_regs.start_cntl_b = REG(DWB_OGAM_RAMB_START_CNTL_B);
0123     gam_regs.start_cntl_g = REG(DWB_OGAM_RAMB_START_CNTL_G);
0124     gam_regs.start_cntl_r = REG(DWB_OGAM_RAMB_START_CNTL_R);
0125     gam_regs.start_base_cntl_b = REG(DWB_OGAM_RAMB_START_BASE_CNTL_B);
0126     gam_regs.start_base_cntl_g = REG(DWB_OGAM_RAMB_START_BASE_CNTL_G);
0127     gam_regs.start_base_cntl_r = REG(DWB_OGAM_RAMB_START_BASE_CNTL_R);
0128     gam_regs.start_slope_cntl_b = REG(DWB_OGAM_RAMB_START_SLOPE_CNTL_B);
0129     gam_regs.start_slope_cntl_g = REG(DWB_OGAM_RAMB_START_SLOPE_CNTL_G);
0130     gam_regs.start_slope_cntl_r = REG(DWB_OGAM_RAMB_START_SLOPE_CNTL_R);
0131     gam_regs.start_end_cntl1_b = REG(DWB_OGAM_RAMB_END_CNTL1_B);
0132     gam_regs.start_end_cntl2_b = REG(DWB_OGAM_RAMB_END_CNTL2_B);
0133     gam_regs.start_end_cntl1_g = REG(DWB_OGAM_RAMB_END_CNTL1_G);
0134     gam_regs.start_end_cntl2_g = REG(DWB_OGAM_RAMB_END_CNTL2_G);
0135     gam_regs.start_end_cntl1_r = REG(DWB_OGAM_RAMB_END_CNTL1_R);
0136     gam_regs.start_end_cntl2_r = REG(DWB_OGAM_RAMB_END_CNTL2_R);
0137     gam_regs.offset_b = REG(DWB_OGAM_RAMB_OFFSET_B);
0138     gam_regs.offset_g = REG(DWB_OGAM_RAMB_OFFSET_G);
0139     gam_regs.offset_r = REG(DWB_OGAM_RAMB_OFFSET_R);
0140     gam_regs.region_start = REG(DWB_OGAM_RAMB_REGION_0_1);
0141     gam_regs.region_end = REG(DWB_OGAM_RAMB_REGION_32_33);
0142
0143     cm_helper_program_gamcor_xfer_func(dwbc30->base.ctx, params, &gam_regs);
0144 }
0145
0146 static enum dc_lut_mode dwb3_get_ogam_current(
0147     struct dcn30_dwbc *dwbc30)
0148 {
0149     enum dc_lut_mode mode;
0150     uint32_t state_mode;
0151     uint32_t ram_select;
0152
0153     REG_GET_2(DWB_OGAM_CONTROL,
0154         DWB_OGAM_MODE_CURRENT, &state_mode,
0155         DWB_OGAM_SELECT_CURRENT, &ram_select);
0156
0157     if (state_mode == 0) {
0158         mode = LUT_BYPASS;
0159     } else if (state_mode == 2) {
0160         if (ram_select == 0)
0161             mode = LUT_RAM_A;
0162         else if (ram_select == 1)
0163             mode = LUT_RAM_B;
0164         else
0165             mode = LUT_BYPASS;
0166     } else {
0167         // Reserved value
0168         mode = LUT_BYPASS;
0169         BREAK_TO_DEBUGGER();
0170         return mode;
0171     }
0172     return mode;
0173 }
0174
0175 static void dwb3_configure_ogam_lut(
0176     struct dcn30_dwbc *dwbc30,
0177     bool is_ram_a)
0178 {
0179     REG_UPDATE_2(DWB_OGAM_LUT_CONTROL,
0180         DWB_OGAM_LUT_WRITE_COLOR_MASK, 7,
0181         DWB_OGAM_LUT_HOST_SEL, (is_ram_a == true) ? 0 : 1);
0182
0183     REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0);
0184 }
0185
0186 static void dwb3_program_ogam_pwl(struct dcn30_dwbc *dwbc30,
0187     const struct pwl_result_data *rgb,
0188     uint32_t num)
0189 {
0190     uint32_t i;
0191
0192     uint32_t last_base_value_red = rgb[num-1].red_reg + rgb[num-1].delta_red_reg;
0193     uint32_t last_base_value_green = rgb[num-1].green_reg + rgb[num-1].delta_green_reg;
0194     uint32_t last_base_value_blue = rgb[num-1].blue_reg + rgb[num-1].delta_blue_reg;
0195
0196     if (is_rgb_equal(rgb,  num)) {
0197         for (i = 0 ; i < num; i++)
0198             REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].red_reg);
0199
0200         REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, last_base_value_red);
0201
0202     } else {
0203
0204         REG_UPDATE(DWB_OGAM_LUT_CONTROL,
0205                 DWB_OGAM_LUT_WRITE_COLOR_MASK, 4);
0206
0207         for (i = 0 ; i < num; i++)
0208             REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].red_reg);
0209
0210         REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, last_base_value_red);
0211
0212         REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0);
0213
0214         REG_UPDATE(DWB_OGAM_LUT_CONTROL,
0215                 DWB_OGAM_LUT_WRITE_COLOR_MASK, 2);
0216
0217         for (i = 0 ; i < num; i++)
0218             REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].green_reg);
0219
0220         REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, last_base_value_green);
0221
0222         REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0);
0223
0224         REG_UPDATE(DWB_OGAM_LUT_CONTROL,
0225                 DWB_OGAM_LUT_WRITE_COLOR_MASK, 1);
0226
0227         for (i = 0 ; i < num; i++)
0228             REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].blue_reg);
0229
0230         REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, last_base_value_blue);
0231     }
0232 }
0233
0234 static bool dwb3_program_ogam_lut(
0235     struct dcn30_dwbc *dwbc30,
0236     const struct pwl_params *params)
0237 {
0238     enum dc_lut_mode current_mode;
0239     enum dc_lut_mode next_mode;
0240
0241     if (params == NULL) {
0242         REG_SET(DWB_OGAM_CONTROL, 0, DWB_OGAM_MODE, 0);
0243         return false;
0244     }
0245
0246     REG_SET(DWB_OGAM_CONTROL, 0, DWB_OGAM_MODE, 2);
0247
0248     current_mode = dwb3_get_ogam_current(dwbc30);
0249     if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
0250         next_mode = LUT_RAM_B;
0251     else
0252         next_mode = LUT_RAM_A;
0253
0254     dwb3_configure_ogam_lut(dwbc30, next_mode == LUT_RAM_A);
0255
0256     if (next_mode == LUT_RAM_A)
0257         dwb3_program_ogam_luta_settings(dwbc30, params);
0258     else
0259         dwb3_program_ogam_lutb_settings(dwbc30, params);
0260
0261     dwb3_program_ogam_pwl(
0262         dwbc30, params->rgb_resulted, params->hw_points_num);
0263
0264     REG_UPDATE(DWB_OGAM_CONTROL, DWB_OGAM_SELECT, next_mode == LUT_RAM_A ? 0 : 1);
0265
0266     return true;
0267 }
0268
0269 bool dwb3_ogam_set_input_transfer_func(
0270     struct dwbc *dwbc,
0271     const struct dc_transfer_func *in_transfer_func_dwb_ogam)
0272 {
0273     struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);
0274     bool result = false;
0275     struct pwl_params *dwb_ogam_lut = NULL;
0276
0277     if (in_transfer_func_dwb_ogam == NULL)
0278         return result;
0279
0280     dwb_ogam_lut = kzalloc(sizeof(*dwb_ogam_lut), GFP_KERNEL);
0281
0282     if (dwb_ogam_lut) {
0283         cm_helper_translate_curve_to_hw_format(
0284             in_transfer_func_dwb_ogam,
0285             dwb_ogam_lut, false);
0286
0287         result = dwb3_program_ogam_lut(
0288             dwbc30,
0289             dwb_ogam_lut);
0290         kfree(dwb_ogam_lut);
0291         dwb_ogam_lut = NULL;
0292     }
0293
0294     return result;
0295 }
0296
0297 static void dwb3_program_gamut_remap(
0298         struct dwbc *dwbc,
0299         const uint16_t *regval,
0300         enum cm_gamut_coef_format coef_format,
0301         enum cm_gamut_remap_select select)
0302 {
0303     struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);
0304
0305     struct color_matrices_reg gam_regs;
0306
0307     if (regval == NULL || select == CM_GAMUT_REMAP_MODE_BYPASS) {
0308         REG_SET(DWB_GAMUT_REMAP_MODE, 0,
0309                 DWB_GAMUT_REMAP_MODE, 0);
0310         return;
0311     }
0312
0313     REG_UPDATE(DWB_GAMUT_REMAP_COEF_FORMAT, DWB_GAMUT_REMAP_COEF_FORMAT, coef_format);
0314
0315     gam_regs.shifts.csc_c11 = dwbc30->dwbc_shift->DWB_GAMUT_REMAPA_C11;
0316     gam_regs.masks.csc_c11  = dwbc30->dwbc_mask->DWB_GAMUT_REMAPA_C11;
0317     gam_regs.shifts.csc_c12 = dwbc30->dwbc_shift->DWB_GAMUT_REMAPA_C12;
0318     gam_regs.masks.csc_c12 = dwbc30->dwbc_mask->DWB_GAMUT_REMAPA_C12;
0319
0320     switch (select) {
0321     case CM_GAMUT_REMAP_MODE_RAMA_COEFF:
0322         gam_regs.csc_c11_c12 = REG(DWB_GAMUT_REMAPA_C11_C12);
0323         gam_regs.csc_c33_c34 = REG(DWB_GAMUT_REMAPA_C33_C34);
0324
0325         cm_helper_program_color_matrices(
0326                 dwbc30->base.ctx,
0327                 regval,
0328                 &gam_regs);
0329         break;
0330     case CM_GAMUT_REMAP_MODE_RAMB_COEFF:
0331         gam_regs.csc_c11_c12 = REG(DWB_GAMUT_REMAPB_C11_C12);
0332         gam_regs.csc_c33_c34 = REG(DWB_GAMUT_REMAPB_C33_C34);
0333
0334         cm_helper_program_color_matrices(
0335                 dwbc30->base.ctx,
0336                 regval,
0337                 &gam_regs);
0338         break;
0339     case CM_GAMUT_REMAP_MODE_RESERVED:
0340         /* should never happen, bug */
0341         BREAK_TO_DEBUGGER();
0342         return;
0343     default:
0344         break;
0345     }
0346
0347     REG_SET(DWB_GAMUT_REMAP_MODE, 0,
0348             DWB_GAMUT_REMAP_MODE, select);
0349
0350 }
0351
0352 void dwb3_set_gamut_remap(
0353     struct dwbc *dwbc,
0354     const struct dc_dwb_params *params)
0355 {
0356     struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);
0357     struct cm_grph_csc_adjustment adjust = params->csc_params;
0358     int i = 0;
0359
0360     if (adjust.gamut_adjust_type != CM_GAMUT_ADJUST_TYPE_SW) {
0361         /* Bypass if type is bypass or hw */
0362         dwb3_program_gamut_remap(dwbc, NULL, adjust.gamut_coef_format, CM_GAMUT_REMAP_MODE_BYPASS);
0363     } else {
0364         struct fixed31_32 arr_matrix[12];
0365         uint16_t arr_reg_val[12];
0366         unsigned int current_mode;
0367
0368         for (i = 0; i < 12; i++)
0369             arr_matrix[i] = adjust.temperature_matrix[i];
0370
0371         convert_float_matrix(arr_reg_val, arr_matrix, 12);
0372
0373         REG_GET(DWB_GAMUT_REMAP_MODE, DWB_GAMUT_REMAP_MODE_CURRENT, &current_mode);
0374
0375         if (current_mode == CM_GAMUT_REMAP_MODE_RAMA_COEFF) {
0376             dwb3_program_gamut_remap(dwbc, arr_reg_val,
0377                     adjust.gamut_coef_format, CM_GAMUT_REMAP_MODE_RAMB_COEFF);
0378         } else {
0379             dwb3_program_gamut_remap(dwbc, arr_reg_val,
0380                     adjust.gamut_coef_format, CM_GAMUT_REMAP_MODE_RAMA_COEFF);
0381         }
0382     }
0383 }
0384
0385 void dwb3_program_hdr_mult(
0386     struct dwbc *dwbc,
0387     const struct dc_dwb_params *params)
0388 {
0389     struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);
0390
0391     REG_UPDATE(DWB_HDR_MULT_COEF, DWB_HDR_MULT_COEF, params->hdr_mult);
0392 }