dc/dcn30/dcn30_dwb.h

0001 /* Copyright 2020 Advanced Micro Devices, Inc.
0002  *
0003  * Permission is hereby granted, free of charge, to any person obtaining a
0004  * copy of this software and associated documentation files (the "Software"),
0005  * to deal in the Software without restriction, including without limitation
0006  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0007  * and/or sell copies of the Software, and to permit persons to whom the
0008  * Software is furnished to do so, subject to the following conditions:
0009  *
0010  * The above copyright notice and this permission notice shall be included in
0011  * all copies or substantial portions of the Software.
0012  *
0013  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0014  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0015  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0016  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0017  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0018  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0019  * OTHER DEALINGS IN THE SOFTWARE.
0020  *
0021  * Authors: AMD
0022  *
0023  */
0024 #ifndef __DC_DWBC_DCN30_H__
0025 #define __DC_DWBC_DCN30_H__
0026
0027 #define TO_DCN30_DWBC(dwbc_base) \
0028     container_of(dwbc_base, struct dcn30_dwbc, base)
0029
0030 /* DCN */
0031 #define BASE_INNER(seg) \
0032     DCE_BASE__INST0_SEG ## seg
0033
0034 #define BASE(seg) \
0035     BASE_INNER(seg)
0036
0037 #define SF_DWB(reg_name, block, id, field_name, post_fix)\
0038     .field_name = block ## id ## _ ## reg_name ## __ ## field_name ## post_fix
0039
0040  /* set field name */
0041 #define SF_DWB2(reg_name, block, id, field_name, post_fix)\
0042     .field_name = reg_name ## __ ## field_name ## post_fix
0043
0044
0045 #define DWBC_COMMON_REG_LIST_DCN30(inst) \
0046     SR(DWB_ENABLE_CLK_CTRL),\
0047     SR(DWB_MEM_PWR_CTRL),\
0048     SR(FC_MODE_CTRL),\
0049     SR(FC_FLOW_CTRL),\
0050     SR(FC_WINDOW_START),\
0051     SR(FC_WINDOW_SIZE),\
0052     SR(FC_SOURCE_SIZE),\
0053     SR(DWB_UPDATE_CTRL),\
0054     SR(DWB_CRC_CTRL),\
0055     SR(DWB_CRC_MASK_R_G),\
0056     SR(DWB_CRC_MASK_B_A),\
0057     SR(DWB_CRC_VAL_R_G),\
0058     SR(DWB_CRC_VAL_B_A),\
0059     SR(DWB_OUT_CTRL),\
0060     SR(DWB_MMHUBBUB_BACKPRESSURE_CNT_EN),\
0061     SR(DWB_MMHUBBUB_BACKPRESSURE_CNT),\
0062     SR(DWB_HOST_READ_CONTROL),\
0063     SR(DWB_SOFT_RESET),\
0064     SR(DWB_HDR_MULT_COEF),\
0065     SR(DWB_GAMUT_REMAP_MODE),\
0066     SR(DWB_GAMUT_REMAP_COEF_FORMAT),\
0067     SR(DWB_GAMUT_REMAPA_C11_C12),\
0068     SR(DWB_GAMUT_REMAPA_C13_C14),\
0069     SR(DWB_GAMUT_REMAPA_C21_C22),\
0070     SR(DWB_GAMUT_REMAPA_C23_C24),\
0071     SR(DWB_GAMUT_REMAPA_C31_C32),\
0072     SR(DWB_GAMUT_REMAPA_C33_C34),\
0073     SR(DWB_GAMUT_REMAPB_C11_C12),\
0074     SR(DWB_GAMUT_REMAPB_C13_C14),\
0075     SR(DWB_GAMUT_REMAPB_C21_C22),\
0076     SR(DWB_GAMUT_REMAPB_C23_C24),\
0077     SR(DWB_GAMUT_REMAPB_C31_C32),\
0078     SR(DWB_GAMUT_REMAPB_C33_C34),\
0079     SR(DWB_OGAM_CONTROL),\
0080     SR(DWB_OGAM_LUT_INDEX),\
0081     SR(DWB_OGAM_LUT_DATA),\
0082     SR(DWB_OGAM_LUT_CONTROL),\
0083     SR(DWB_OGAM_RAMA_START_CNTL_B),\
0084     SR(DWB_OGAM_RAMA_START_CNTL_G),\
0085     SR(DWB_OGAM_RAMA_START_CNTL_R),\
0086     SR(DWB_OGAM_RAMA_START_BASE_CNTL_B),\
0087     SR(DWB_OGAM_RAMA_START_SLOPE_CNTL_B),\
0088     SR(DWB_OGAM_RAMA_START_BASE_CNTL_G),\
0089     SR(DWB_OGAM_RAMA_START_SLOPE_CNTL_G),\
0090     SR(DWB_OGAM_RAMA_START_BASE_CNTL_R),\
0091     SR(DWB_OGAM_RAMA_START_SLOPE_CNTL_R),\
0092     SR(DWB_OGAM_RAMA_END_CNTL1_B),\
0093     SR(DWB_OGAM_RAMA_END_CNTL2_B),\
0094     SR(DWB_OGAM_RAMA_END_CNTL1_G),\
0095     SR(DWB_OGAM_RAMA_END_CNTL2_G),\
0096     SR(DWB_OGAM_RAMA_END_CNTL1_R),\
0097     SR(DWB_OGAM_RAMA_END_CNTL2_R),\
0098     SR(DWB_OGAM_RAMA_OFFSET_B),\
0099     SR(DWB_OGAM_RAMA_OFFSET_G),\
0100     SR(DWB_OGAM_RAMA_OFFSET_R),\
0101     SR(DWB_OGAM_RAMA_REGION_0_1),\
0102     SR(DWB_OGAM_RAMA_REGION_2_3),\
0103     SR(DWB_OGAM_RAMA_REGION_4_5),\
0104     SR(DWB_OGAM_RAMA_REGION_6_7),\
0105     SR(DWB_OGAM_RAMA_REGION_8_9),\
0106     SR(DWB_OGAM_RAMA_REGION_10_11),\
0107     SR(DWB_OGAM_RAMA_REGION_12_13),\
0108     SR(DWB_OGAM_RAMA_REGION_14_15),\
0109     SR(DWB_OGAM_RAMA_REGION_16_17),\
0110     SR(DWB_OGAM_RAMA_REGION_18_19),\
0111     SR(DWB_OGAM_RAMA_REGION_20_21),\
0112     SR(DWB_OGAM_RAMA_REGION_22_23),\
0113     SR(DWB_OGAM_RAMA_REGION_24_25),\
0114     SR(DWB_OGAM_RAMA_REGION_26_27),\
0115     SR(DWB_OGAM_RAMA_REGION_28_29),\
0116     SR(DWB_OGAM_RAMA_REGION_30_31),\
0117     SR(DWB_OGAM_RAMA_REGION_32_33),\
0118     SR(DWB_OGAM_RAMB_START_CNTL_B),\
0119     SR(DWB_OGAM_RAMB_START_CNTL_G),\
0120     SR(DWB_OGAM_RAMB_START_CNTL_R),\
0121     SR(DWB_OGAM_RAMB_START_BASE_CNTL_B),\
0122     SR(DWB_OGAM_RAMB_START_SLOPE_CNTL_B),\
0123     SR(DWB_OGAM_RAMB_START_BASE_CNTL_G),\
0124     SR(DWB_OGAM_RAMB_START_SLOPE_CNTL_G),\
0125     SR(DWB_OGAM_RAMB_START_BASE_CNTL_R),\
0126     SR(DWB_OGAM_RAMB_START_SLOPE_CNTL_R),\
0127     SR(DWB_OGAM_RAMB_END_CNTL1_B),\
0128     SR(DWB_OGAM_RAMB_END_CNTL2_B),\
0129     SR(DWB_OGAM_RAMB_END_CNTL1_G),\
0130     SR(DWB_OGAM_RAMB_END_CNTL2_G),\
0131     SR(DWB_OGAM_RAMB_END_CNTL1_R),\
0132     SR(DWB_OGAM_RAMB_END_CNTL2_R),\
0133     SR(DWB_OGAM_RAMB_OFFSET_B),\
0134     SR(DWB_OGAM_RAMB_OFFSET_G),\
0135     SR(DWB_OGAM_RAMB_OFFSET_R),\
0136     SR(DWB_OGAM_RAMB_REGION_0_1),\
0137     SR(DWB_OGAM_RAMB_REGION_2_3),\
0138     SR(DWB_OGAM_RAMB_REGION_4_5),\
0139     SR(DWB_OGAM_RAMB_REGION_6_7),\
0140     SR(DWB_OGAM_RAMB_REGION_8_9),\
0141     SR(DWB_OGAM_RAMB_REGION_10_11),\
0142     SR(DWB_OGAM_RAMB_REGION_12_13),\
0143     SR(DWB_OGAM_RAMB_REGION_14_15),\
0144     SR(DWB_OGAM_RAMB_REGION_16_17),\
0145     SR(DWB_OGAM_RAMB_REGION_18_19),\
0146     SR(DWB_OGAM_RAMB_REGION_20_21),\
0147     SR(DWB_OGAM_RAMB_REGION_22_23),\
0148     SR(DWB_OGAM_RAMB_REGION_24_25),\
0149     SR(DWB_OGAM_RAMB_REGION_26_27),\
0150     SR(DWB_OGAM_RAMB_REGION_28_29),\
0151     SR(DWB_OGAM_RAMB_REGION_30_31),\
0152     SR(DWB_OGAM_RAMB_REGION_32_33)
0153
0154
0155 #define DWBC_COMMON_MASK_SH_LIST_DCN30(mask_sh) \
0156     SF_DWB2(DWB_ENABLE_CLK_CTRL, DWB_TOP, 0, DWB_ENABLE, mask_sh),\
0157     SF_DWB2(DWB_ENABLE_CLK_CTRL, DWB_TOP, 0, DISPCLK_R_DWB_GATE_DIS, mask_sh),\
0158     SF_DWB2(DWB_ENABLE_CLK_CTRL, DWB_TOP, 0, DISPCLK_G_DWB_GATE_DIS, mask_sh),\
0159     SF_DWB2(DWB_ENABLE_CLK_CTRL, DWB_TOP, 0, DWB_TEST_CLK_SEL, mask_sh),\
0160     SF_DWB2(DWB_MEM_PWR_CTRL, DWB_TOP, 0, DWB_OGAM_LUT_MEM_PWR_FORCE, mask_sh),\
0161     SF_DWB2(DWB_MEM_PWR_CTRL, DWB_TOP, 0, DWB_OGAM_LUT_MEM_PWR_DIS, mask_sh),\
0162     SF_DWB2(DWB_MEM_PWR_CTRL, DWB_TOP, 0, DWB_OGAM_LUT_MEM_PWR_STATE, mask_sh),\
0163     SF_DWB2(FC_MODE_CTRL, DWB_TOP, 0, FC_FRAME_CAPTURE_EN, mask_sh),\
0164     SF_DWB2(FC_MODE_CTRL, DWB_TOP, 0, FC_FRAME_CAPTURE_RATE, mask_sh),\
0165     SF_DWB2(FC_MODE_CTRL, DWB_TOP, 0, FC_WINDOW_CROP_EN, mask_sh),\
0166     SF_DWB2(FC_MODE_CTRL, DWB_TOP, 0, FC_EYE_SELECTION, mask_sh),\
0167     SF_DWB2(FC_MODE_CTRL, DWB_TOP, 0, FC_STEREO_EYE_POLARITY, mask_sh),\
0168     SF_DWB2(FC_MODE_CTRL, DWB_TOP, 0, FC_NEW_CONTENT, mask_sh),\
0169     SF_DWB2(FC_MODE_CTRL, DWB_TOP, 0, FC_FRAME_CAPTURE_EN_CURRENT, mask_sh),\
0170     SF_DWB2(FC_FLOW_CTRL, DWB_TOP, 0, FC_FIRST_PIXEL_DELAY_COUNT, mask_sh),\
0171     SF_DWB2(FC_WINDOW_START, DWB_TOP, 0, FC_WINDOW_START_X, mask_sh),\
0172     SF_DWB2(FC_WINDOW_START, DWB_TOP, 0, FC_WINDOW_START_Y, mask_sh),\
0173     SF_DWB2(FC_WINDOW_SIZE, DWB_TOP, 0, FC_WINDOW_WIDTH, mask_sh),\
0174     SF_DWB2(FC_WINDOW_SIZE, DWB_TOP, 0, FC_WINDOW_HEIGHT, mask_sh),\
0175     SF_DWB2(FC_SOURCE_SIZE, DWB_TOP, 0, FC_SOURCE_WIDTH, mask_sh),\
0176     SF_DWB2(FC_SOURCE_SIZE, DWB_TOP, 0, FC_SOURCE_HEIGHT, mask_sh),\
0177     SF_DWB2(DWB_UPDATE_CTRL, DWB_TOP, 0, DWB_UPDATE_LOCK, mask_sh),\
0178     SF_DWB2(DWB_UPDATE_CTRL, DWB_TOP, 0, DWB_UPDATE_PENDING, mask_sh),\
0179     SF_DWB2(DWB_CRC_CTRL, DWB_TOP, 0, DWB_CRC_EN, mask_sh),\
0180     SF_DWB2(DWB_CRC_CTRL, DWB_TOP, 0, DWB_CRC_CONT_EN, mask_sh),\
0181     SF_DWB2(DWB_CRC_CTRL, DWB_TOP, 0, DWB_CRC_SRC_SEL, mask_sh),\
0182     SF_DWB2(DWB_CRC_MASK_R_G, DWB_TOP, 0, DWB_CRC_RED_MASK, mask_sh),\
0183     SF_DWB2(DWB_CRC_MASK_R_G, DWB_TOP, 0, DWB_CRC_GREEN_MASK, mask_sh),\
0184     SF_DWB2(DWB_CRC_MASK_B_A, DWB_TOP, 0, DWB_CRC_BLUE_MASK, mask_sh),\
0185     SF_DWB2(DWB_CRC_MASK_B_A, DWB_TOP, 0, DWB_CRC_A_MASK, mask_sh),\
0186     SF_DWB2(DWB_CRC_VAL_R_G, DWB_TOP, 0, DWB_CRC_SIG_RED, mask_sh),\
0187     SF_DWB2(DWB_CRC_VAL_R_G, DWB_TOP, 0, DWB_CRC_SIG_GREEN, mask_sh),\
0188     SF_DWB2(DWB_CRC_VAL_B_A, DWB_TOP, 0, DWB_CRC_SIG_BLUE, mask_sh),\
0189     SF_DWB2(DWB_CRC_VAL_B_A, DWB_TOP, 0, DWB_CRC_SIG_A, mask_sh),\
0190     SF_DWB2(DWB_OUT_CTRL, DWB_TOP, 0, OUT_FORMAT, mask_sh),\
0191     SF_DWB2(DWB_OUT_CTRL, DWB_TOP, 0, OUT_DENORM, mask_sh),\
0192     SF_DWB2(DWB_OUT_CTRL, DWB_TOP, 0, OUT_MAX, mask_sh),\
0193     SF_DWB2(DWB_OUT_CTRL, DWB_TOP, 0, OUT_MIN, mask_sh),\
0194     SF_DWB2(DWB_MMHUBBUB_BACKPRESSURE_CNT_EN, DWB_TOP, 0, DWB_MMHUBBUB_BACKPRESSURE_CNT_EN, mask_sh),\
0195     SF_DWB2(DWB_MMHUBBUB_BACKPRESSURE_CNT, DWB_TOP, 0, DWB_MMHUBBUB_MAX_BACKPRESSURE, mask_sh),\
0196     SF_DWB2(DWB_HOST_READ_CONTROL, DWB_TOP, 0, DWB_HOST_READ_RATE_CONTROL, mask_sh),\
0197     SF_DWB2(DWB_SOFT_RESET, DWB_TOP, 0, DWB_SOFT_RESET, mask_sh),\
0198     SF_DWB2(DWB_HDR_MULT_COEF, DWBCP, 0, DWB_HDR_MULT_COEF, mask_sh),\
0199     SF_DWB2(DWB_GAMUT_REMAP_MODE, DWBCP, 0, DWB_GAMUT_REMAP_MODE, mask_sh),\
0200     SF_DWB2(DWB_GAMUT_REMAP_MODE, DWBCP, 0, DWB_GAMUT_REMAP_MODE_CURRENT, mask_sh),\
0201     SF_DWB2(DWB_GAMUT_REMAP_COEF_FORMAT, DWBCP, 0, DWB_GAMUT_REMAP_COEF_FORMAT, mask_sh),\
0202     SF_DWB2(DWB_GAMUT_REMAPA_C11_C12, DWBCP, 0, DWB_GAMUT_REMAPA_C11, mask_sh),\
0203     SF_DWB2(DWB_GAMUT_REMAPA_C11_C12, DWBCP, 0, DWB_GAMUT_REMAPA_C12, mask_sh),\
0204     SF_DWB2(DWB_GAMUT_REMAPA_C13_C14, DWBCP, 0, DWB_GAMUT_REMAPA_C13, mask_sh),\
0205     SF_DWB2(DWB_GAMUT_REMAPA_C13_C14, DWBCP, 0, DWB_GAMUT_REMAPA_C14, mask_sh),\
0206     SF_DWB2(DWB_GAMUT_REMAPA_C21_C22, DWBCP, 0, DWB_GAMUT_REMAPA_C21, mask_sh),\
0207     SF_DWB2(DWB_GAMUT_REMAPA_C21_C22, DWBCP, 0, DWB_GAMUT_REMAPA_C22, mask_sh),\
0208     SF_DWB2(DWB_GAMUT_REMAPA_C23_C24, DWBCP, 0, DWB_GAMUT_REMAPA_C23, mask_sh),\
0209     SF_DWB2(DWB_GAMUT_REMAPA_C23_C24, DWBCP, 0, DWB_GAMUT_REMAPA_C24, mask_sh),\
0210     SF_DWB2(DWB_GAMUT_REMAPA_C31_C32, DWBCP, 0, DWB_GAMUT_REMAPA_C31, mask_sh),\
0211     SF_DWB2(DWB_GAMUT_REMAPA_C31_C32, DWBCP, 0, DWB_GAMUT_REMAPA_C32, mask_sh),\
0212     SF_DWB2(DWB_GAMUT_REMAPA_C33_C34, DWBCP, 0, DWB_GAMUT_REMAPA_C33, mask_sh),\
0213     SF_DWB2(DWB_GAMUT_REMAPA_C33_C34, DWBCP, 0, DWB_GAMUT_REMAPA_C34, mask_sh),\
0214     SF_DWB2(DWB_GAMUT_REMAPB_C11_C12, DWBCP, 0, DWB_GAMUT_REMAPB_C11, mask_sh),\
0215     SF_DWB2(DWB_GAMUT_REMAPB_C11_C12, DWBCP, 0, DWB_GAMUT_REMAPB_C12, mask_sh),\
0216     SF_DWB2(DWB_GAMUT_REMAPB_C13_C14, DWBCP, 0, DWB_GAMUT_REMAPB_C13, mask_sh),\
0217     SF_DWB2(DWB_GAMUT_REMAPB_C13_C14, DWBCP, 0, DWB_GAMUT_REMAPB_C14, mask_sh),\
0218     SF_DWB2(DWB_GAMUT_REMAPB_C21_C22, DWBCP, 0, DWB_GAMUT_REMAPB_C21, mask_sh),\
0219     SF_DWB2(DWB_GAMUT_REMAPB_C21_C22, DWBCP, 0, DWB_GAMUT_REMAPB_C22, mask_sh),\
0220     SF_DWB2(DWB_GAMUT_REMAPB_C23_C24, DWBCP, 0, DWB_GAMUT_REMAPB_C23, mask_sh),\
0221     SF_DWB2(DWB_GAMUT_REMAPB_C23_C24, DWBCP, 0, DWB_GAMUT_REMAPB_C24, mask_sh),\
0222     SF_DWB2(DWB_GAMUT_REMAPB_C31_C32, DWBCP, 0, DWB_GAMUT_REMAPB_C31, mask_sh),\
0223     SF_DWB2(DWB_GAMUT_REMAPB_C31_C32, DWBCP, 0, DWB_GAMUT_REMAPB_C32, mask_sh),\
0224     SF_DWB2(DWB_GAMUT_REMAPB_C33_C34, DWBCP, 0, DWB_GAMUT_REMAPB_C33, mask_sh),\
0225     SF_DWB2(DWB_GAMUT_REMAPB_C33_C34, DWBCP, 0, DWB_GAMUT_REMAPB_C34, mask_sh),\
0226     SF_DWB2(DWB_OGAM_CONTROL, DWBCP, 0, DWB_OGAM_MODE, mask_sh),\
0227     SF_DWB2(DWB_OGAM_CONTROL, DWBCP, 0, DWB_OGAM_SELECT, mask_sh),\
0228     SF_DWB2(DWB_OGAM_CONTROL, DWBCP, 0, DWB_OGAM_PWL_DISABLE, mask_sh),\
0229     SF_DWB2(DWB_OGAM_CONTROL, DWBCP, 0, DWB_OGAM_MODE_CURRENT, mask_sh),\
0230     SF_DWB2(DWB_OGAM_CONTROL, DWBCP, 0, DWB_OGAM_SELECT_CURRENT, mask_sh),\
0231     SF_DWB2(DWB_OGAM_LUT_INDEX, DWBCP, 0, DWB_OGAM_LUT_INDEX, mask_sh),\
0232     SF_DWB2(DWB_OGAM_LUT_DATA, DWBCP, 0, DWB_OGAM_LUT_DATA, mask_sh),\
0233     SF_DWB2(DWB_OGAM_LUT_CONTROL, DWBCP, 0, DWB_OGAM_LUT_WRITE_COLOR_MASK, mask_sh),\
0234     SF_DWB2(DWB_OGAM_LUT_CONTROL, DWBCP, 0, DWB_OGAM_LUT_READ_COLOR_SEL, mask_sh),\
0235     SF_DWB2(DWB_OGAM_LUT_CONTROL, DWBCP, 0, DWB_OGAM_LUT_READ_DBG, mask_sh),\
0236     SF_DWB2(DWB_OGAM_LUT_CONTROL, DWBCP, 0, DWB_OGAM_LUT_HOST_SEL, mask_sh),\
0237     SF_DWB2(DWB_OGAM_LUT_CONTROL, DWBCP, 0, DWB_OGAM_LUT_CONFIG_MODE, mask_sh),\
0238     SF_DWB2(DWB_OGAM_RAMA_START_CNTL_B, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_B, mask_sh),\
0239     SF_DWB2(DWB_OGAM_RAMA_START_CNTL_B, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\
0240     SF_DWB2(DWB_OGAM_RAMA_START_CNTL_G, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_G, mask_sh),\
0241     SF_DWB2(DWB_OGAM_RAMA_START_CNTL_G, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh),\
0242     SF_DWB2(DWB_OGAM_RAMA_START_CNTL_R, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_R, mask_sh),\
0243     SF_DWB2(DWB_OGAM_RAMA_START_CNTL_R, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh),\
0244     SF_DWB2(DWB_OGAM_RAMA_START_BASE_CNTL_B, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_BASE_B, mask_sh),\
0245     SF_DWB2(DWB_OGAM_RAMA_START_SLOPE_CNTL_B, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B, mask_sh),\
0246     SF_DWB2(DWB_OGAM_RAMA_START_BASE_CNTL_G, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_BASE_G, mask_sh),\
0247     SF_DWB2(DWB_OGAM_RAMA_START_SLOPE_CNTL_G, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G, mask_sh),\
0248     SF_DWB2(DWB_OGAM_RAMA_START_BASE_CNTL_R, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_BASE_R, mask_sh),\
0249     SF_DWB2(DWB_OGAM_RAMA_START_SLOPE_CNTL_R, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R, mask_sh),\
0250     SF_DWB2(DWB_OGAM_RAMA_END_CNTL1_B, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh),\
0251     SF_DWB2(DWB_OGAM_RAMA_END_CNTL2_B, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_END_B, mask_sh),\
0252     SF_DWB2(DWB_OGAM_RAMA_END_CNTL2_B, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\
0253     SF_DWB2(DWB_OGAM_RAMA_END_CNTL1_G, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh),\
0254     SF_DWB2(DWB_OGAM_RAMA_END_CNTL2_G, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_END_G, mask_sh),\
0255     SF_DWB2(DWB_OGAM_RAMA_END_CNTL2_G, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh),\
0256     SF_DWB2(DWB_OGAM_RAMA_END_CNTL1_R, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh),\
0257     SF_DWB2(DWB_OGAM_RAMA_END_CNTL2_R, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_END_R, mask_sh),\
0258     SF_DWB2(DWB_OGAM_RAMA_END_CNTL2_R, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh),\
0259     SF_DWB2(DWB_OGAM_RAMA_OFFSET_B, DWBCP, 0, DWB_OGAM_RAMA_OFFSET_B, mask_sh),\
0260     SF_DWB2(DWB_OGAM_RAMA_OFFSET_G, DWBCP, 0, DWB_OGAM_RAMA_OFFSET_G, mask_sh),\
0261     SF_DWB2(DWB_OGAM_RAMA_OFFSET_R, DWBCP, 0, DWB_OGAM_RAMA_OFFSET_R, mask_sh),\
0262     SF_DWB2(DWB_OGAM_RAMA_REGION_0_1, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\
0263     SF_DWB2(DWB_OGAM_RAMA_REGION_0_1, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
0264     SF_DWB2(DWB_OGAM_RAMA_REGION_0_1, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\
0265     SF_DWB2(DWB_OGAM_RAMA_REGION_0_1, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
0266     SF_DWB2(DWB_OGAM_RAMA_REGION_2_3, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET, mask_sh),\
0267     SF_DWB2(DWB_OGAM_RAMA_REGION_2_3, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS, mask_sh),\
0268     SF_DWB2(DWB_OGAM_RAMA_REGION_2_3, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET, mask_sh),\
0269     SF_DWB2(DWB_OGAM_RAMA_REGION_2_3, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS, mask_sh),\
0270     SF_DWB2(DWB_OGAM_RAMA_REGION_4_5, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET, mask_sh),\
0271     SF_DWB2(DWB_OGAM_RAMA_REGION_4_5, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS, mask_sh),\
0272     SF_DWB2(DWB_OGAM_RAMA_REGION_4_5, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET, mask_sh),\
0273     SF_DWB2(DWB_OGAM_RAMA_REGION_4_5, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS, mask_sh),\
0274     SF_DWB2(DWB_OGAM_RAMA_REGION_6_7, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET, mask_sh),\
0275     SF_DWB2(DWB_OGAM_RAMA_REGION_6_7, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS, mask_sh),\
0276     SF_DWB2(DWB_OGAM_RAMA_REGION_6_7, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET, mask_sh),\
0277     SF_DWB2(DWB_OGAM_RAMA_REGION_6_7, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS, mask_sh),\
0278     SF_DWB2(DWB_OGAM_RAMA_REGION_8_9, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET, mask_sh),\
0279     SF_DWB2(DWB_OGAM_RAMA_REGION_8_9, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS, mask_sh),\
0280     SF_DWB2(DWB_OGAM_RAMA_REGION_8_9, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET, mask_sh),\
0281     SF_DWB2(DWB_OGAM_RAMA_REGION_8_9, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS, mask_sh),\
0282     SF_DWB2(DWB_OGAM_RAMA_REGION_10_11, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET, mask_sh),\
0283     SF_DWB2(DWB_OGAM_RAMA_REGION_10_11, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS, mask_sh),\
0284     SF_DWB2(DWB_OGAM_RAMA_REGION_10_11, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET, mask_sh),\
0285     SF_DWB2(DWB_OGAM_RAMA_REGION_10_11, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS, mask_sh),\
0286     SF_DWB2(DWB_OGAM_RAMA_REGION_12_13, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET, mask_sh),\
0287     SF_DWB2(DWB_OGAM_RAMA_REGION_12_13, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS, mask_sh),\
0288     SF_DWB2(DWB_OGAM_RAMA_REGION_12_13, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET, mask_sh),\
0289     SF_DWB2(DWB_OGAM_RAMA_REGION_12_13, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS, mask_sh),\
0290     SF_DWB2(DWB_OGAM_RAMA_REGION_14_15, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh),\
0291     SF_DWB2(DWB_OGAM_RAMA_REGION_14_15, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh),\
0292     SF_DWB2(DWB_OGAM_RAMA_REGION_14_15, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh),\
0293     SF_DWB2(DWB_OGAM_RAMA_REGION_14_15, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh),\
0294     SF_DWB2(DWB_OGAM_RAMA_REGION_16_17, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET, mask_sh),\
0295     SF_DWB2(DWB_OGAM_RAMA_REGION_16_17, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS, mask_sh),\
0296     SF_DWB2(DWB_OGAM_RAMA_REGION_16_17, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET, mask_sh),\
0297     SF_DWB2(DWB_OGAM_RAMA_REGION_16_17, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS, mask_sh),\
0298     SF_DWB2(DWB_OGAM_RAMA_REGION_18_19, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET, mask_sh),\
0299     SF_DWB2(DWB_OGAM_RAMA_REGION_18_19, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS, mask_sh),\
0300     SF_DWB2(DWB_OGAM_RAMA_REGION_18_19, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET, mask_sh),\
0301     SF_DWB2(DWB_OGAM_RAMA_REGION_18_19, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS, mask_sh),\
0302     SF_DWB2(DWB_OGAM_RAMA_REGION_20_21, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET, mask_sh),\
0303     SF_DWB2(DWB_OGAM_RAMA_REGION_20_21, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS, mask_sh),\
0304     SF_DWB2(DWB_OGAM_RAMA_REGION_20_21, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET, mask_sh),\
0305     SF_DWB2(DWB_OGAM_RAMA_REGION_20_21, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS, mask_sh),\
0306     SF_DWB2(DWB_OGAM_RAMA_REGION_22_23, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET, mask_sh),\
0307     SF_DWB2(DWB_OGAM_RAMA_REGION_22_23, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS, mask_sh),\
0308     SF_DWB2(DWB_OGAM_RAMA_REGION_22_23, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET, mask_sh),\
0309     SF_DWB2(DWB_OGAM_RAMA_REGION_22_23, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS, mask_sh),\
0310     SF_DWB2(DWB_OGAM_RAMA_REGION_24_25, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET, mask_sh),\
0311     SF_DWB2(DWB_OGAM_RAMA_REGION_24_25, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS, mask_sh),\
0312     SF_DWB2(DWB_OGAM_RAMA_REGION_24_25, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET, mask_sh),\
0313     SF_DWB2(DWB_OGAM_RAMA_REGION_24_25, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS, mask_sh),\
0314     SF_DWB2(DWB_OGAM_RAMA_REGION_26_27, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET, mask_sh),\
0315     SF_DWB2(DWB_OGAM_RAMA_REGION_26_27, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS, mask_sh),\
0316     SF_DWB2(DWB_OGAM_RAMA_REGION_26_27, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET, mask_sh),\
0317     SF_DWB2(DWB_OGAM_RAMA_REGION_26_27, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS, mask_sh),\
0318     SF_DWB2(DWB_OGAM_RAMA_REGION_28_29, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET, mask_sh),\
0319     SF_DWB2(DWB_OGAM_RAMA_REGION_28_29, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS, mask_sh),\
0320     SF_DWB2(DWB_OGAM_RAMA_REGION_28_29, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET, mask_sh),\
0321     SF_DWB2(DWB_OGAM_RAMA_REGION_28_29, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS, mask_sh),\
0322     SF_DWB2(DWB_OGAM_RAMA_REGION_30_31, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET, mask_sh),\
0323     SF_DWB2(DWB_OGAM_RAMA_REGION_30_31, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS, mask_sh),\
0324     SF_DWB2(DWB_OGAM_RAMA_REGION_30_31, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET, mask_sh),\
0325     SF_DWB2(DWB_OGAM_RAMA_REGION_30_31, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS, mask_sh),\
0326     SF_DWB2(DWB_OGAM_RAMA_REGION_32_33, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET, mask_sh),\
0327     SF_DWB2(DWB_OGAM_RAMA_REGION_32_33, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS, mask_sh),\
0328     SF_DWB2(DWB_OGAM_RAMA_REGION_32_33, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh),\
0329     SF_DWB2(DWB_OGAM_RAMA_REGION_32_33, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh),\
0330     SF_DWB2(DWB_OGAM_RAMB_START_CNTL_B, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_START_B, mask_sh),\
0331     SF_DWB2(DWB_OGAM_RAMB_START_CNTL_B, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh),\
0332     SF_DWB2(DWB_OGAM_RAMB_START_CNTL_G, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_START_G, mask_sh),\
0333     SF_DWB2(DWB_OGAM_RAMB_START_CNTL_G, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh),\
0334     SF_DWB2(DWB_OGAM_RAMB_START_CNTL_R, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_START_R, mask_sh),\
0335     SF_DWB2(DWB_OGAM_RAMB_START_CNTL_R, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh),\
0336     SF_DWB2(DWB_OGAM_RAMB_START_BASE_CNTL_B, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_START_BASE_B, mask_sh),\
0337     SF_DWB2(DWB_OGAM_RAMB_START_SLOPE_CNTL_B, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B, mask_sh),\
0338     SF_DWB2(DWB_OGAM_RAMB_START_BASE_CNTL_G, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_START_BASE_G, mask_sh),\
0339     SF_DWB2(DWB_OGAM_RAMB_START_SLOPE_CNTL_G, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G, mask_sh),\
0340     SF_DWB2(DWB_OGAM_RAMB_START_BASE_CNTL_R, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_START_BASE_R, mask_sh),\
0341     SF_DWB2(DWB_OGAM_RAMB_START_SLOPE_CNTL_R, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R, mask_sh),\
0342     SF_DWB2(DWB_OGAM_RAMB_END_CNTL1_B, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh),\
0343     SF_DWB2(DWB_OGAM_RAMB_END_CNTL2_B, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_END_B, mask_sh),\
0344     SF_DWB2(DWB_OGAM_RAMB_END_CNTL2_B, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh),\
0345     SF_DWB2(DWB_OGAM_RAMB_END_CNTL1_G, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh),\
0346     SF_DWB2(DWB_OGAM_RAMB_END_CNTL2_G, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_END_G, mask_sh),\
0347     SF_DWB2(DWB_OGAM_RAMB_END_CNTL2_G, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh),\
0348     SF_DWB2(DWB_OGAM_RAMB_END_CNTL1_R, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh),\
0349     SF_DWB2(DWB_OGAM_RAMB_END_CNTL2_R, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_END_R, mask_sh),\
0350     SF_DWB2(DWB_OGAM_RAMB_END_CNTL2_R, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh),\
0351     SF_DWB2(DWB_OGAM_RAMB_OFFSET_B, DWBCP, 0, DWB_OGAM_RAMB_OFFSET_B, mask_sh),\
0352     SF_DWB2(DWB_OGAM_RAMB_OFFSET_G, DWBCP, 0, DWB_OGAM_RAMB_OFFSET_G, mask_sh),\
0353     SF_DWB2(DWB_OGAM_RAMB_OFFSET_R, DWBCP, 0, DWB_OGAM_RAMB_OFFSET_R, mask_sh),\
0354     SF_DWB2(DWB_OGAM_RAMB_REGION_0_1, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh),\
0355     SF_DWB2(DWB_OGAM_RAMB_REGION_0_1, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
0356     SF_DWB2(DWB_OGAM_RAMB_REGION_0_1, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh),\
0357     SF_DWB2(DWB_OGAM_RAMB_REGION_0_1, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
0358     SF_DWB2(DWB_OGAM_RAMB_REGION_2_3, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET, mask_sh),\
0359     SF_DWB2(DWB_OGAM_RAMB_REGION_2_3, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS, mask_sh),\
0360     SF_DWB2(DWB_OGAM_RAMB_REGION_2_3, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET, mask_sh),\
0361     SF_DWB2(DWB_OGAM_RAMB_REGION_2_3, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS, mask_sh),\
0362     SF_DWB2(DWB_OGAM_RAMB_REGION_4_5, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET, mask_sh),\
0363     SF_DWB2(DWB_OGAM_RAMB_REGION_4_5, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS, mask_sh),\
0364     SF_DWB2(DWB_OGAM_RAMB_REGION_4_5, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET, mask_sh),\
0365     SF_DWB2(DWB_OGAM_RAMB_REGION_4_5, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS, mask_sh),\
0366     SF_DWB2(DWB_OGAM_RAMB_REGION_6_7, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET, mask_sh),\
0367     SF_DWB2(DWB_OGAM_RAMB_REGION_6_7, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS, mask_sh),\
0368     SF_DWB2(DWB_OGAM_RAMB_REGION_6_7, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET, mask_sh),\
0369     SF_DWB2(DWB_OGAM_RAMB_REGION_6_7, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS, mask_sh),\
0370     SF_DWB2(DWB_OGAM_RAMB_REGION_8_9, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET, mask_sh),\
0371     SF_DWB2(DWB_OGAM_RAMB_REGION_8_9, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS, mask_sh),\
0372     SF_DWB2(DWB_OGAM_RAMB_REGION_8_9, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET, mask_sh),\
0373     SF_DWB2(DWB_OGAM_RAMB_REGION_8_9, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS, mask_sh),\
0374     SF_DWB2(DWB_OGAM_RAMB_REGION_10_11, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET, mask_sh),\
0375     SF_DWB2(DWB_OGAM_RAMB_REGION_10_11, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS, mask_sh),\
0376     SF_DWB2(DWB_OGAM_RAMB_REGION_10_11, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET, mask_sh),\
0377     SF_DWB2(DWB_OGAM_RAMB_REGION_10_11, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS, mask_sh),\
0378     SF_DWB2(DWB_OGAM_RAMB_REGION_12_13, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET, mask_sh),\
0379     SF_DWB2(DWB_OGAM_RAMB_REGION_12_13, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS, mask_sh),\
0380     SF_DWB2(DWB_OGAM_RAMB_REGION_12_13, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET, mask_sh),\
0381     SF_DWB2(DWB_OGAM_RAMB_REGION_12_13, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS, mask_sh),\
0382     SF_DWB2(DWB_OGAM_RAMB_REGION_14_15, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh),\
0383     SF_DWB2(DWB_OGAM_RAMB_REGION_14_15, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh),\
0384     SF_DWB2(DWB_OGAM_RAMB_REGION_14_15, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh),\
0385     SF_DWB2(DWB_OGAM_RAMB_REGION_14_15, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh),\
0386     SF_DWB2(DWB_OGAM_RAMB_REGION_16_17, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET, mask_sh),\
0387     SF_DWB2(DWB_OGAM_RAMB_REGION_16_17, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS, mask_sh),\
0388     SF_DWB2(DWB_OGAM_RAMB_REGION_16_17, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET, mask_sh),\
0389     SF_DWB2(DWB_OGAM_RAMB_REGION_16_17, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS, mask_sh),\
0390     SF_DWB2(DWB_OGAM_RAMB_REGION_18_19, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET, mask_sh),\
0391     SF_DWB2(DWB_OGAM_RAMB_REGION_18_19, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS, mask_sh),\
0392     SF_DWB2(DWB_OGAM_RAMB_REGION_18_19, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET, mask_sh),\
0393     SF_DWB2(DWB_OGAM_RAMB_REGION_18_19, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS, mask_sh),\
0394     SF_DWB2(DWB_OGAM_RAMB_REGION_20_21, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET, mask_sh),\
0395     SF_DWB2(DWB_OGAM_RAMB_REGION_20_21, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS, mask_sh),\
0396     SF_DWB2(DWB_OGAM_RAMB_REGION_20_21, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET, mask_sh),\
0397     SF_DWB2(DWB_OGAM_RAMB_REGION_20_21, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS, mask_sh),\
0398     SF_DWB2(DWB_OGAM_RAMB_REGION_22_23, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET, mask_sh),\
0399     SF_DWB2(DWB_OGAM_RAMB_REGION_22_23, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS, mask_sh),\
0400     SF_DWB2(DWB_OGAM_RAMB_REGION_22_23, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET, mask_sh),\
0401     SF_DWB2(DWB_OGAM_RAMB_REGION_22_23, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS, mask_sh),\
0402     SF_DWB2(DWB_OGAM_RAMB_REGION_24_25, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET, mask_sh),\
0403     SF_DWB2(DWB_OGAM_RAMB_REGION_24_25, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS, mask_sh),\
0404     SF_DWB2(DWB_OGAM_RAMB_REGION_24_25, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET, mask_sh),\
0405     SF_DWB2(DWB_OGAM_RAMB_REGION_24_25, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS, mask_sh),\
0406     SF_DWB2(DWB_OGAM_RAMB_REGION_26_27, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET, mask_sh),\
0407     SF_DWB2(DWB_OGAM_RAMB_REGION_26_27, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS, mask_sh),\
0408     SF_DWB2(DWB_OGAM_RAMB_REGION_26_27, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET, mask_sh),\
0409     SF_DWB2(DWB_OGAM_RAMB_REGION_26_27, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS, mask_sh),\
0410     SF_DWB2(DWB_OGAM_RAMB_REGION_28_29, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET, mask_sh),\
0411     SF_DWB2(DWB_OGAM_RAMB_REGION_28_29, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS, mask_sh),\
0412     SF_DWB2(DWB_OGAM_RAMB_REGION_28_29, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET, mask_sh),\
0413     SF_DWB2(DWB_OGAM_RAMB_REGION_28_29, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS, mask_sh),\
0414     SF_DWB2(DWB_OGAM_RAMB_REGION_30_31, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET, mask_sh),\
0415     SF_DWB2(DWB_OGAM_RAMB_REGION_30_31, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS, mask_sh),\
0416     SF_DWB2(DWB_OGAM_RAMB_REGION_30_31, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET, mask_sh),\
0417     SF_DWB2(DWB_OGAM_RAMB_REGION_30_31, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS, mask_sh),\
0418     SF_DWB2(DWB_OGAM_RAMB_REGION_32_33, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET, mask_sh),\
0419     SF_DWB2(DWB_OGAM_RAMB_REGION_32_33, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS, mask_sh),\
0420     SF_DWB2(DWB_OGAM_RAMB_REGION_32_33, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET, mask_sh),\
0421     SF_DWB2(DWB_OGAM_RAMB_REGION_32_33, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS, mask_sh)
0422
0423
0424 #define DWBC_REG_FIELD_LIST_DCN3_0(type) \
0425     type DWB_ENABLE;\
0426     type DISPCLK_R_DWB_GATE_DIS;\
0427     type DISPCLK_G_DWB_GATE_DIS;\
0428     type DWB_TEST_CLK_SEL;\
0429     type DWBSCL_LUT_MEM_PWR_FORCE;\
0430     type DWBSCL_LUT_MEM_PWR_DIS;\
0431     type DWBSCL_LUT_MEM_PWR_STATE;\
0432     type DWBSCL_LB_MEM_PWR_FORCE;\
0433     type DWBSCL_LB_MEM_PWR_DIS;\
0434     type DWBSCL_LB_MEM_PWR_STATE;\
0435     type DWB_OGAM_LUT_MEM_PWR_FORCE;\
0436     type DWB_OGAM_LUT_MEM_PWR_DIS;\
0437     type DWB_OGAM_LUT_MEM_PWR_STATE;\
0438     type FC_FRAME_CAPTURE_EN;\
0439     type FC_FRAME_CAPTURE_RATE;\
0440     type FC_WINDOW_CROP_EN;\
0441     type FC_EYE_SELECTION;\
0442     type FC_STEREO_EYE_POLARITY;\
0443     type FC_NEW_CONTENT;\
0444     type FC_FI_EN;\
0445     type FC_FI_PHASE;\
0446     type FC_FRAME_CAPTURE_EN_CURRENT;\
0447     type FC_FIRST_PIXEL_DELAY_COUNT;\
0448     type FC_WINDOW_START_X;\
0449     type FC_WINDOW_START_Y;\
0450     type FC_WINDOW_WIDTH;\
0451     type FC_WINDOW_HEIGHT;\
0452     type FC_SOURCE_WIDTH;\
0453     type FC_SOURCE_HEIGHT;\
0454     type DWB_UPDATE_LOCK;\
0455     type DWB_UPDATE_PENDING;\
0456     type DWB_CRC_EN;\
0457     type DWB_CRC_CONT_EN;\
0458     type DWB_CRC_SRC_SEL;\
0459     type DWB_CRC_RED_MASK;\
0460     type DWB_CRC_GREEN_MASK;\
0461     type DWB_CRC_BLUE_MASK;\
0462     type DWB_CRC_A_MASK;\
0463     type DWB_CRC_SIG_RED;\
0464     type DWB_CRC_SIG_GREEN;\
0465     type DWB_CRC_SIG_BLUE;\
0466     type DWB_CRC_SIG_A;\
0467     type OUT_FORMAT;\
0468     type OUT_DENORM;\
0469     type OUT_MAX;\
0470     type OUT_MIN;\
0471     type DWB_MMHUBBUB_BACKPRESSURE_CNT_EN;\
0472     type DWB_MMHUBBUB_MAX_BACKPRESSURE;\
0473     type DWB_HOST_READ_RATE_CONTROL;\
0474     type DWBSCL_DATA_OVERFLOW_FLAG;\
0475     type DWBSCL_DATA_OVERFLOW_ACK;\
0476     type DWBSCL_DATA_OVERFLOW_MASK;\
0477     type DWBSCL_DATA_OVERFLOW_INT_STATUS;\
0478     type DWBSCL_DATA_OVERFLOW_INT_TYPE;\
0479     type DWBSCL_DATA_OVERFLOW_TYPE;\
0480     type DWBSCL_DATA_OVERFLOW_OUT_X_CNT;\
0481     type DWBSCL_DATA_OVERFLOW_OUT_Y_CNT;\
0482     type DWB_SOFT_RESET;\
0483     type DWBSCL_COEF_RAM_TAP_PAIR_IDX;\
0484     type DWBSCL_COEF_RAM_PHASE;\
0485     type DWBSCL_COEF_RAM_FILTER_TYPE;\
0486     type DWBSCL_COEF_RAM_SELECT_RD;\
0487     type DWBSCL_COEF_RAM_EVEN_TAP_COEF;\
0488     type DWBSCL_COEF_RAM_EVEN_TAP_COEF_EN;\
0489     type DWBSCL_COEF_RAM_ODD_TAP_COEF;\
0490     type DWBSCL_COEF_RAM_ODD_TAP_COEF_EN;\
0491     type DWBSCL_MODE;\
0492     type DWBSCL_COEF_RAM_SELECT;\
0493     type DWBSCL_COEF_RAM_SELECT_CURRENT;\
0494     type DWBSCL_H_NUM_OF_TAPS;\
0495     type DWBSCL_V_NUM_OF_TAPS;\
0496     type DWBSCL_H_SCALE_RATIO;\
0497     type DWBSCL_H_INIT_FRAC;\
0498     type DWBSCL_H_INIT_INT;\
0499     type DWBSCL_V_SCALE_RATIO;\
0500     type DWBSCL_V_INIT_FRAC;\
0501     type DWBSCL_V_INIT_INT;\
0502     type DWBSCL_BOUNDARY_MODE;\
0503     type DWBSCL_BLACK_COLOR_RGB;\
0504     type DWBSCL_DEST_WIDTH;\
0505     type DWBSCL_DEST_HEIGHT;\
0506     type DWB_HDR_MULT_COEF;\
0507     type DWB_GAMUT_REMAP_MODE;\
0508     type DWB_GAMUT_REMAP_MODE_CURRENT;\
0509     type DWB_GAMUT_REMAP_COEF_FORMAT;\
0510     type DWB_GAMUT_REMAPA_C11;\
0511     type DWB_GAMUT_REMAPA_C12;\
0512     type DWB_GAMUT_REMAPA_C13;\
0513     type DWB_GAMUT_REMAPA_C14;\
0514     type DWB_GAMUT_REMAPA_C21;\
0515     type DWB_GAMUT_REMAPA_C22;\
0516     type DWB_GAMUT_REMAPA_C23;\
0517     type DWB_GAMUT_REMAPA_C24;\
0518     type DWB_GAMUT_REMAPA_C31;\
0519     type DWB_GAMUT_REMAPA_C32;\
0520     type DWB_GAMUT_REMAPA_C33;\
0521     type DWB_GAMUT_REMAPA_C34;\
0522     type DWB_GAMUT_REMAPB_C11;\
0523     type DWB_GAMUT_REMAPB_C12;\
0524     type DWB_GAMUT_REMAPB_C13;\
0525     type DWB_GAMUT_REMAPB_C14;\
0526     type DWB_GAMUT_REMAPB_C21;\
0527     type DWB_GAMUT_REMAPB_C22;\
0528     type DWB_GAMUT_REMAPB_C23;\
0529     type DWB_GAMUT_REMAPB_C24;\
0530     type DWB_GAMUT_REMAPB_C31;\
0531     type DWB_GAMUT_REMAPB_C32;\
0532     type DWB_GAMUT_REMAPB_C33;\
0533     type DWB_GAMUT_REMAPB_C34;\
0534     type DWB_OGAM_MODE;\
0535     type DWB_OGAM_SELECT;\
0536     type DWB_OGAM_PWL_DISABLE;\
0537     type DWB_OGAM_MODE_CURRENT;\
0538     type DWB_OGAM_SELECT_CURRENT;\
0539     type DWB_OGAM_LUT_INDEX;\
0540     type DWB_OGAM_LUT_DATA;\
0541     type DWB_OGAM_LUT_WRITE_COLOR_MASK;\
0542     type DWB_OGAM_LUT_READ_COLOR_SEL;\
0543     type DWB_OGAM_LUT_READ_DBG;\
0544     type DWB_OGAM_LUT_HOST_SEL;\
0545     type DWB_OGAM_LUT_CONFIG_MODE;\
0546     type DWB_OGAM_LUT_STATUS;\
0547     type DWB_OGAM_RAMA_EXP_REGION_START_B;\
0548     type DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;\
0549     type DWB_OGAM_RAMA_EXP_REGION_START_G;\
0550     type DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G;\
0551     type DWB_OGAM_RAMA_EXP_REGION_START_R;\
0552     type DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R;\
0553     type DWB_OGAM_RAMA_EXP_REGION_START_BASE_B;\
0554     type DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B;\
0555     type DWB_OGAM_RAMA_EXP_REGION_START_BASE_G;\
0556     type DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G;\
0557     type DWB_OGAM_RAMA_EXP_REGION_START_BASE_R;\
0558     type DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R;\
0559     type DWB_OGAM_RAMA_EXP_REGION_END_BASE_B;\
0560     type DWB_OGAM_RAMA_EXP_REGION_END_B;\
0561     type DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B;\
0562     type DWB_OGAM_RAMA_EXP_REGION_END_BASE_G;\
0563     type DWB_OGAM_RAMA_EXP_REGION_END_G;\
0564     type DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G;\
0565     type DWB_OGAM_RAMA_EXP_REGION_END_BASE_R;\
0566     type DWB_OGAM_RAMA_EXP_REGION_END_R;\
0567     type DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R;\
0568     type DWB_OGAM_RAMA_OFFSET_B;\
0569     type DWB_OGAM_RAMA_OFFSET_G;\
0570     type DWB_OGAM_RAMA_OFFSET_R;\
0571     type DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;\
0572     type DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;\
0573     type DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;\
0574     type DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;\
0575     type DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET;\
0576     type DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS;\
0577     type DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET;\
0578     type DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS;\
0579     type DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET;\
0580     type DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS;\
0581     type DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET;\
0582     type DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS;\
0583     type DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET;\
0584     type DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS;\
0585     type DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET;\
0586     type DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS;\
0587     type DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET;\
0588     type DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS;\
0589     type DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET;\
0590     type DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS;\
0591     type DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET;\
0592     type DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS;\
0593     type DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET;\
0594     type DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS;\
0595     type DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET;\
0596     type DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS;\
0597     type DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET;\
0598     type DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS;\
0599     type DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET;\
0600     type DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS;\
0601     type DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET;\
0602     type DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS;\
0603     type DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET;\
0604     type DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS;\
0605     type DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET;\
0606     type DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS;\
0607     type DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET;\
0608     type DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS;\
0609     type DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET;\
0610     type DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS;\
0611     type DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET;\
0612     type DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS;\
0613     type DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET;\
0614     type DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS;\
0615     type DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET;\
0616     type DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS;\
0617     type DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET;\
0618     type DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS;\
0619     type DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET;\
0620     type DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS;\
0621     type DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET;\
0622     type DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS;\
0623     type DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET;\
0624     type DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS;\
0625     type DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET;\
0626     type DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS;\
0627     type DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET;\
0628     type DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS;\
0629     type DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET;\
0630     type DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS;\
0631     type DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET;\
0632     type DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS;\
0633     type DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET;\
0634     type DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS;\
0635     type DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET;\
0636     type DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS;\
0637     type DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET;\
0638     type DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS;\
0639     type DWB_OGAM_RAMB_EXP_REGION_START_B;\
0640     type DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B;\
0641     type DWB_OGAM_RAMB_EXP_REGION_START_G;\
0642     type DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G;\
0643     type DWB_OGAM_RAMB_EXP_REGION_START_R;\
0644     type DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R;\
0645     type DWB_OGAM_RAMB_EXP_REGION_START_BASE_B;\
0646     type DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B;\
0647     type DWB_OGAM_RAMB_EXP_REGION_START_BASE_G;\
0648     type DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G;\
0649     type DWB_OGAM_RAMB_EXP_REGION_START_BASE_R;\
0650     type DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R;\
0651     type DWB_OGAM_RAMB_EXP_REGION_END_BASE_B;\
0652     type DWB_OGAM_RAMB_EXP_REGION_END_B;\
0653     type DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B;\
0654     type DWB_OGAM_RAMB_EXP_REGION_END_BASE_G;\
0655     type DWB_OGAM_RAMB_EXP_REGION_END_G;\
0656     type DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G;\
0657     type DWB_OGAM_RAMB_EXP_REGION_END_BASE_R;\
0658     type DWB_OGAM_RAMB_EXP_REGION_END_R;\
0659     type DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R;\
0660     type DWB_OGAM_RAMB_OFFSET_B;\
0661     type DWB_OGAM_RAMB_OFFSET_G;\
0662     type DWB_OGAM_RAMB_OFFSET_R;\
0663     type DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET;\
0664     type DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS;\
0665     type DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET;\
0666     type DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS;\
0667     type DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET;\
0668     type DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS;\
0669     type DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET;\
0670     type DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS;\
0671     type DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET;\
0672     type DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS;\
0673     type DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET;\
0674     type DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS;\
0675     type DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET;\
0676     type DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS;\
0677     type DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET;\
0678     type DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS;\
0679     type DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET;\
0680     type DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS;\
0681     type DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET;\
0682     type DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS;\
0683     type DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET;\
0684     type DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS;\
0685     type DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET;\
0686     type DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS;\
0687     type DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET;\
0688     type DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS;\
0689     type DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET;\
0690     type DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS;\
0691     type DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET;\
0692     type DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS;\
0693     type DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET;\
0694     type DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS;\
0695     type DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET;\
0696     type DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS;\
0697     type DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET;\
0698     type DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS;\
0699     type DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET;\
0700     type DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS;\
0701     type DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET;\
0702     type DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS;\
0703     type DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET;\
0704     type DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS;\
0705     type DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET;\
0706     type DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS;\
0707     type DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET;\
0708     type DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS;\
0709     type DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET;\
0710     type DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS;\
0711     type DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET;\
0712     type DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS;\
0713     type DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET;\
0714     type DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS;\
0715     type DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET;\
0716     type DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS;\
0717     type DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET;\
0718     type DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS;\
0719     type DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET;\
0720     type DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS;\
0721     type DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET;\
0722     type DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS;\
0723     type DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET;\
0724     type DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS;\
0725     type DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET;\
0726     type DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS;\
0727     type DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET;\
0728     type DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS;\
0729     type DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET;\
0730     type DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS;
0731
0732 struct dcn30_dwbc_registers {
0733     /* DCN3AG */
0734     /* DWB_TOP */
0735     uint32_t DWB_ENABLE_CLK_CTRL;
0736     uint32_t DWB_MEM_PWR_CTRL;
0737     uint32_t FC_MODE_CTRL;
0738     uint32_t FC_FLOW_CTRL;
0739     uint32_t FC_WINDOW_START;
0740     uint32_t FC_WINDOW_SIZE;
0741     uint32_t FC_SOURCE_SIZE;
0742     uint32_t DWB_UPDATE_CTRL;
0743     uint32_t DWB_CRC_CTRL;
0744     uint32_t DWB_CRC_MASK_R_G;
0745     uint32_t DWB_CRC_MASK_B_A;
0746     uint32_t DWB_CRC_VAL_R_G;
0747     uint32_t DWB_CRC_VAL_B_A;
0748     uint32_t DWB_OUT_CTRL;
0749     uint32_t DWB_MMHUBBUB_BACKPRESSURE_CNT_EN;
0750     uint32_t DWB_MMHUBBUB_BACKPRESSURE_CNT;
0751     uint32_t DWB_HOST_READ_CONTROL;
0752     uint32_t DWB_SOFT_RESET;
0753
0754     /* DWBSCL */
0755     uint32_t DWBSCL_COEF_RAM_TAP_SELECT;
0756     uint32_t DWBSCL_COEF_RAM_TAP_DATA;
0757     uint32_t DWBSCL_MODE;
0758     uint32_t DWBSCL_TAP_CONTROL;
0759     uint32_t DWBSCL_HORZ_FILTER_SCALE_RATIO;
0760     uint32_t DWBSCL_HORZ_FILTER_INIT;
0761     uint32_t DWBSCL_VERT_FILTER_SCALE_RATIO;
0762     uint32_t DWBSCL_VERT_FILTER_INIT;
0763     uint32_t DWBSCL_BOUNDARY_CTRL;
0764     uint32_t DWBSCL_DEST_SIZE;
0765     uint32_t DWBSCL_OVERFLOW_STATUS;
0766     uint32_t DWBSCL_OVERFLOW_COUNTER;
0767
0768     /* DWBCP */
0769     uint32_t DWB_HDR_MULT_COEF;
0770     uint32_t DWB_GAMUT_REMAP_MODE;
0771     uint32_t DWB_GAMUT_REMAP_COEF_FORMAT;
0772     uint32_t DWB_GAMUT_REMAPA_C11_C12;
0773     uint32_t DWB_GAMUT_REMAPA_C13_C14;
0774     uint32_t DWB_GAMUT_REMAPA_C21_C22;
0775     uint32_t DWB_GAMUT_REMAPA_C23_C24;
0776     uint32_t DWB_GAMUT_REMAPA_C31_C32;
0777     uint32_t DWB_GAMUT_REMAPA_C33_C34;
0778     uint32_t DWB_GAMUT_REMAPB_C11_C12;
0779     uint32_t DWB_GAMUT_REMAPB_C13_C14;
0780     uint32_t DWB_GAMUT_REMAPB_C21_C22;
0781     uint32_t DWB_GAMUT_REMAPB_C23_C24;
0782     uint32_t DWB_GAMUT_REMAPB_C31_C32;
0783     uint32_t DWB_GAMUT_REMAPB_C33_C34;
0784     uint32_t DWB_OGAM_CONTROL;
0785     uint32_t DWB_OGAM_LUT_INDEX;
0786     uint32_t DWB_OGAM_LUT_DATA;
0787     uint32_t DWB_OGAM_LUT_CONTROL;
0788     uint32_t DWB_OGAM_RAMA_START_CNTL_B;
0789     uint32_t DWB_OGAM_RAMA_START_CNTL_G;
0790     uint32_t DWB_OGAM_RAMA_START_CNTL_R;
0791     uint32_t DWB_OGAM_RAMA_START_BASE_CNTL_B;
0792     uint32_t DWB_OGAM_RAMA_START_SLOPE_CNTL_B;
0793     uint32_t DWB_OGAM_RAMA_START_BASE_CNTL_G;
0794     uint32_t DWB_OGAM_RAMA_START_SLOPE_CNTL_G;
0795     uint32_t DWB_OGAM_RAMA_START_BASE_CNTL_R;
0796     uint32_t DWB_OGAM_RAMA_START_SLOPE_CNTL_R;
0797     uint32_t DWB_OGAM_RAMA_END_CNTL1_B;
0798     uint32_t DWB_OGAM_RAMA_END_CNTL2_B;
0799     uint32_t DWB_OGAM_RAMA_END_CNTL1_G;
0800     uint32_t DWB_OGAM_RAMA_END_CNTL2_G;
0801     uint32_t DWB_OGAM_RAMA_END_CNTL1_R;
0802     uint32_t DWB_OGAM_RAMA_END_CNTL2_R;
0803     uint32_t DWB_OGAM_RAMA_OFFSET_B;
0804     uint32_t DWB_OGAM_RAMA_OFFSET_G;
0805     uint32_t DWB_OGAM_RAMA_OFFSET_R;
0806     uint32_t DWB_OGAM_RAMA_REGION_0_1;
0807     uint32_t DWB_OGAM_RAMA_REGION_2_3;
0808     uint32_t DWB_OGAM_RAMA_REGION_4_5;
0809     uint32_t DWB_OGAM_RAMA_REGION_6_7;
0810     uint32_t DWB_OGAM_RAMA_REGION_8_9;
0811     uint32_t DWB_OGAM_RAMA_REGION_10_11;
0812     uint32_t DWB_OGAM_RAMA_REGION_12_13;
0813     uint32_t DWB_OGAM_RAMA_REGION_14_15;
0814     uint32_t DWB_OGAM_RAMA_REGION_16_17;
0815     uint32_t DWB_OGAM_RAMA_REGION_18_19;
0816     uint32_t DWB_OGAM_RAMA_REGION_20_21;
0817     uint32_t DWB_OGAM_RAMA_REGION_22_23;
0818     uint32_t DWB_OGAM_RAMA_REGION_24_25;
0819     uint32_t DWB_OGAM_RAMA_REGION_26_27;
0820     uint32_t DWB_OGAM_RAMA_REGION_28_29;
0821     uint32_t DWB_OGAM_RAMA_REGION_30_31;
0822     uint32_t DWB_OGAM_RAMA_REGION_32_33;
0823     uint32_t DWB_OGAM_RAMB_START_CNTL_B;
0824     uint32_t DWB_OGAM_RAMB_START_CNTL_G;
0825     uint32_t DWB_OGAM_RAMB_START_CNTL_R;
0826     uint32_t DWB_OGAM_RAMB_START_BASE_CNTL_B;
0827     uint32_t DWB_OGAM_RAMB_START_SLOPE_CNTL_B;
0828     uint32_t DWB_OGAM_RAMB_START_BASE_CNTL_G;
0829     uint32_t DWB_OGAM_RAMB_START_SLOPE_CNTL_G;
0830     uint32_t DWB_OGAM_RAMB_START_BASE_CNTL_R;
0831     uint32_t DWB_OGAM_RAMB_START_SLOPE_CNTL_R;
0832     uint32_t DWB_OGAM_RAMB_END_CNTL1_B;
0833     uint32_t DWB_OGAM_RAMB_END_CNTL2_B;
0834     uint32_t DWB_OGAM_RAMB_END_CNTL1_G;
0835     uint32_t DWB_OGAM_RAMB_END_CNTL2_G;
0836     uint32_t DWB_OGAM_RAMB_END_CNTL1_R;
0837     uint32_t DWB_OGAM_RAMB_END_CNTL2_R;
0838     uint32_t DWB_OGAM_RAMB_OFFSET_B;
0839     uint32_t DWB_OGAM_RAMB_OFFSET_G;
0840     uint32_t DWB_OGAM_RAMB_OFFSET_R;
0841     uint32_t DWB_OGAM_RAMB_REGION_0_1;
0842     uint32_t DWB_OGAM_RAMB_REGION_2_3;
0843     uint32_t DWB_OGAM_RAMB_REGION_4_5;
0844     uint32_t DWB_OGAM_RAMB_REGION_6_7;
0845     uint32_t DWB_OGAM_RAMB_REGION_8_9;
0846     uint32_t DWB_OGAM_RAMB_REGION_10_11;
0847     uint32_t DWB_OGAM_RAMB_REGION_12_13;
0848     uint32_t DWB_OGAM_RAMB_REGION_14_15;
0849     uint32_t DWB_OGAM_RAMB_REGION_16_17;
0850     uint32_t DWB_OGAM_RAMB_REGION_18_19;
0851     uint32_t DWB_OGAM_RAMB_REGION_20_21;
0852     uint32_t DWB_OGAM_RAMB_REGION_22_23;
0853     uint32_t DWB_OGAM_RAMB_REGION_24_25;
0854     uint32_t DWB_OGAM_RAMB_REGION_26_27;
0855     uint32_t DWB_OGAM_RAMB_REGION_28_29;
0856     uint32_t DWB_OGAM_RAMB_REGION_30_31;
0857     uint32_t DWB_OGAM_RAMB_REGION_32_33;
0858 };
0859
0860 /* Internal enums / structs */
0861 enum dwbscl_coef_filter_type_sel {
0862     DWBSCL_COEF_RAM_FILTER_TYPE_VERT_RGB = 0,
0863     DWBSCL_COEF_RAM_FILTER_TYPE_HORZ_RGB = 1
0864 };
0865
0866
0867 struct dcn30_dwbc_mask {
0868     DWBC_REG_FIELD_LIST_DCN3_0(uint32_t);
0869 };
0870
0871 struct dcn30_dwbc_shift {
0872     DWBC_REG_FIELD_LIST_DCN3_0(uint8_t);
0873 };
0874
0875 struct dcn30_dwbc {
0876     struct dwbc base;
0877     const struct dcn30_dwbc_registers *dwbc_regs;
0878     const struct dcn30_dwbc_shift *dwbc_shift;
0879     const struct dcn30_dwbc_mask *dwbc_mask;
0880 };
0881
0882 void dcn30_dwbc_construct(struct dcn30_dwbc *dwbc30,
0883     struct dc_context *ctx,
0884     const struct dcn30_dwbc_registers *dwbc_regs,
0885     const struct dcn30_dwbc_shift *dwbc_shift,
0886     const struct dcn30_dwbc_mask *dwbc_mask,
0887     int inst);
0888
0889 bool dwb3_enable(struct dwbc *dwbc, struct dc_dwb_params *params);
0890
0891 bool dwb3_disable(struct dwbc *dwbc);
0892
0893 bool dwb3_update(struct dwbc *dwbc, struct dc_dwb_params *params);
0894
0895 bool dwb3_is_enabled(struct dwbc *dwbc);
0896
0897 void dwb3_set_stereo(struct dwbc *dwbc,
0898     struct dwb_stereo_params *stereo_params);
0899
0900 void dwb3_set_new_content(struct dwbc *dwbc,
0901     bool is_new_content);
0902
0903 void dwb3_config_fc(struct dwbc *dwbc,
0904     struct dc_dwb_params *params);
0905
0906 void dwb3_set_denorm(struct dwbc *dwbc, struct dc_dwb_params *params);
0907
0908 void dwb3_program_hdr_mult(
0909     struct dwbc *dwbc,
0910     const struct dc_dwb_params *params);
0911
0912 void dwb3_set_gamut_remap(
0913     struct dwbc *dwbc,
0914     const struct dc_dwb_params *params);
0915
0916 bool dwb3_ogam_set_input_transfer_func(
0917     struct dwbc *dwbc,
0918     const struct dc_transfer_func *in_transfer_func_dwb_ogam);
0919
0920 void dwb3_set_host_read_rate_control(struct dwbc *dwbc, bool host_read_delay);
0921 #endif
0922
0923