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OSCL-LXR
 
 

     

0001 /* Copyright 2020 Advanced Micro Devices, Inc.
0002  *
0003  * Permission is hereby granted, free of charge, to any person obtaining a
0004  * copy of this software and associated documentation files (the "Software"),
0005  * to deal in the Software without restriction, including without limitation
0006  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0007  * and/or sell copies of the Software, and to permit persons to whom the
0008  * Software is furnished to do so, subject to the following conditions:
0009  *
0010  * The above copyright notice and this permission notice shall be included in
0011  * all copies or substantial portions of the Software.
0012  *
0013  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0014  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0015  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0016  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0017  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0018  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0019  * OTHER DEALINGS IN THE SOFTWARE.
0020  *
0021  * Authors: AMD
0022  *
0023  */
0024 
0025 #ifndef __DCN30_DPP_H__
0026 #define __DCN30_DPP_H__
0027 
0028 #include "dcn20/dcn20_dpp.h"
0029 
0030 #define TO_DCN30_DPP(dpp)\
0031     container_of(dpp, struct dcn3_dpp, base)
0032 
0033 #define DPP_REG_LIST_DCN30_COMMON(id)\
0034     SRI(CM_DEALPHA, CM, id),\
0035     SRI(CM_MEM_PWR_STATUS, CM, id),\
0036     SRI(CM_BIAS_CR_R, CM, id),\
0037     SRI(CM_BIAS_Y_G_CB_B, CM, id),\
0038     SRI(PRE_DEGAM, CNVC_CFG, id),\
0039     SRI(CM_GAMCOR_CONTROL, CM, id),\
0040     SRI(CM_GAMCOR_LUT_CONTROL, CM, id),\
0041     SRI(CM_GAMCOR_LUT_INDEX, CM, id),\
0042     SRI(CM_GAMCOR_LUT_INDEX, CM, id),\
0043     SRI(CM_GAMCOR_LUT_DATA, CM, id),\
0044     SRI(CM_GAMCOR_RAMB_START_CNTL_B, CM, id),\
0045     SRI(CM_GAMCOR_RAMB_START_CNTL_G, CM, id),\
0046     SRI(CM_GAMCOR_RAMB_START_CNTL_R, CM, id),\
0047     SRI(CM_GAMCOR_RAMB_START_SLOPE_CNTL_B, CM, id),\
0048     SRI(CM_GAMCOR_RAMB_START_SLOPE_CNTL_G, CM, id),\
0049     SRI(CM_GAMCOR_RAMB_START_SLOPE_CNTL_R, CM, id),\
0050     SRI(CM_GAMCOR_RAMB_END_CNTL1_B, CM, id),\
0051     SRI(CM_GAMCOR_RAMB_END_CNTL2_B, CM, id),\
0052     SRI(CM_GAMCOR_RAMB_END_CNTL1_G, CM, id),\
0053     SRI(CM_GAMCOR_RAMB_END_CNTL2_G, CM, id),\
0054     SRI(CM_GAMCOR_RAMB_END_CNTL1_R, CM, id),\
0055     SRI(CM_GAMCOR_RAMB_END_CNTL2_R, CM, id),\
0056     SRI(CM_GAMCOR_RAMB_REGION_0_1, CM, id),\
0057     SRI(CM_GAMCOR_RAMB_REGION_32_33, CM, id),\
0058     SRI(CM_GAMCOR_RAMB_OFFSET_B, CM, id),\
0059     SRI(CM_GAMCOR_RAMB_OFFSET_G, CM, id),\
0060     SRI(CM_GAMCOR_RAMB_OFFSET_R, CM, id),\
0061     SRI(CM_GAMCOR_RAMB_START_BASE_CNTL_B, CM, id),\
0062     SRI(CM_GAMCOR_RAMB_START_BASE_CNTL_G, CM, id),\
0063     SRI(CM_GAMCOR_RAMB_START_BASE_CNTL_R, CM, id),\
0064     SRI(CM_GAMCOR_RAMA_START_CNTL_B, CM, id),\
0065     SRI(CM_GAMCOR_RAMA_START_CNTL_G, CM, id),\
0066     SRI(CM_GAMCOR_RAMA_START_CNTL_R, CM, id),\
0067     SRI(CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, CM, id),\
0068     SRI(CM_GAMCOR_RAMA_START_SLOPE_CNTL_G, CM, id),\
0069     SRI(CM_GAMCOR_RAMA_START_SLOPE_CNTL_R, CM, id),\
0070     SRI(CM_GAMCOR_RAMA_END_CNTL1_B, CM, id),\
0071     SRI(CM_GAMCOR_RAMA_END_CNTL2_B, CM, id),\
0072     SRI(CM_GAMCOR_RAMA_END_CNTL1_G, CM, id),\
0073     SRI(CM_GAMCOR_RAMA_END_CNTL2_G, CM, id),\
0074     SRI(CM_GAMCOR_RAMA_END_CNTL1_R, CM, id),\
0075     SRI(CM_GAMCOR_RAMA_END_CNTL2_R, CM, id),\
0076     SRI(CM_GAMCOR_RAMA_REGION_0_1, CM, id),\
0077     SRI(CM_GAMCOR_RAMA_REGION_32_33, CM, id),\
0078     SRI(CM_GAMCOR_RAMA_OFFSET_B, CM, id),\
0079     SRI(CM_GAMCOR_RAMA_OFFSET_G, CM, id),\
0080     SRI(CM_GAMCOR_RAMA_OFFSET_R, CM, id),\
0081     SRI(CM_GAMCOR_RAMA_START_BASE_CNTL_B, CM, id),\
0082     SRI(CM_GAMCOR_RAMA_START_BASE_CNTL_G, CM, id),\
0083     SRI(CM_GAMCOR_RAMA_START_BASE_CNTL_R, CM, id),\
0084     SRI(CM_GAMUT_REMAP_CONTROL, CM, id),\
0085     SRI(CM_GAMUT_REMAP_C11_C12, CM, id),\
0086     SRI(CM_GAMUT_REMAP_C13_C14, CM, id),\
0087     SRI(CM_GAMUT_REMAP_C21_C22, CM, id),\
0088     SRI(CM_GAMUT_REMAP_C23_C24, CM, id),\
0089     SRI(CM_GAMUT_REMAP_C31_C32, CM, id),\
0090     SRI(CM_GAMUT_REMAP_C33_C34, CM, id),\
0091     SRI(CM_GAMUT_REMAP_B_C11_C12, CM, id),\
0092     SRI(CM_GAMUT_REMAP_B_C13_C14, CM, id),\
0093     SRI(CM_GAMUT_REMAP_B_C21_C22, CM, id),\
0094     SRI(CM_GAMUT_REMAP_B_C23_C24, CM, id),\
0095     SRI(CM_GAMUT_REMAP_B_C31_C32, CM, id),\
0096     SRI(CM_GAMUT_REMAP_B_C33_C34, CM, id),\
0097     SRI(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \
0098     SRI(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \
0099     SRI(OTG_H_BLANK, DSCL, id), \
0100     SRI(OTG_V_BLANK, DSCL, id), \
0101     SRI(SCL_MODE, DSCL, id), \
0102     SRI(LB_DATA_FORMAT, DSCL, id), \
0103     SRI(LB_MEMORY_CTRL, DSCL, id), \
0104     SRI(DSCL_AUTOCAL, DSCL, id), \
0105     SRI(SCL_TAP_CONTROL, DSCL, id), \
0106     SRI(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \
0107     SRI(SCL_COEF_RAM_TAP_DATA, DSCL, id), \
0108     SRI(DSCL_2TAP_CONTROL, DSCL, id), \
0109     SRI(MPC_SIZE, DSCL, id), \
0110     SRI(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id), \
0111     SRI(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id), \
0112     SRI(SCL_HORZ_FILTER_SCALE_RATIO_C, DSCL, id), \
0113     SRI(SCL_VERT_FILTER_SCALE_RATIO_C, DSCL, id), \
0114     SRI(SCL_HORZ_FILTER_INIT, DSCL, id), \
0115     SRI(SCL_HORZ_FILTER_INIT_C, DSCL, id), \
0116     SRI(SCL_VERT_FILTER_INIT, DSCL, id), \
0117     SRI(SCL_VERT_FILTER_INIT_C, DSCL, id), \
0118     SRI(RECOUT_START, DSCL, id), \
0119     SRI(RECOUT_SIZE, DSCL, id), \
0120     SRI(PRE_DEALPHA, CNVC_CFG, id), \
0121     SRI(PRE_REALPHA, CNVC_CFG, id), \
0122     SRI(PRE_CSC_MODE, CNVC_CFG, id), \
0123     SRI(PRE_CSC_C11_C12, CNVC_CFG, id), \
0124     SRI(PRE_CSC_C33_C34, CNVC_CFG, id), \
0125     SRI(PRE_CSC_B_C11_C12, CNVC_CFG, id), \
0126     SRI(PRE_CSC_B_C33_C34, CNVC_CFG, id), \
0127     SRI(CM_POST_CSC_CONTROL, CM, id), \
0128     SRI(CM_POST_CSC_C11_C12, CM, id), \
0129     SRI(CM_POST_CSC_C33_C34, CM, id), \
0130     SRI(CM_POST_CSC_B_C11_C12, CM, id), \
0131     SRI(CM_POST_CSC_B_C33_C34, CM, id), \
0132     SRI(CM_MEM_PWR_CTRL, CM, id), \
0133     SRI(CM_CONTROL, CM, id), \
0134     SRI(FORMAT_CONTROL, CNVC_CFG, id), \
0135     SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
0136     SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
0137     SRI(CURSOR0_COLOR0, CNVC_CUR, id), \
0138     SRI(CURSOR0_COLOR1, CNVC_CUR, id), \
0139     SRI(CURSOR0_FP_SCALE_BIAS, CNVC_CUR, id), \
0140     SRI(DPP_CONTROL, DPP_TOP, id), \
0141     SRI(CM_HDR_MULT_COEF, CM, id), \
0142     SRI(CURSOR_CONTROL, CURSOR0_, id), \
0143     SRI(ALPHA_2BIT_LUT, CNVC_CFG, id), \
0144     SRI(FCNV_FP_BIAS_R, CNVC_CFG, id), \
0145     SRI(FCNV_FP_BIAS_G, CNVC_CFG, id), \
0146     SRI(FCNV_FP_BIAS_B, CNVC_CFG, id), \
0147     SRI(FCNV_FP_SCALE_R, CNVC_CFG, id), \
0148     SRI(FCNV_FP_SCALE_G, CNVC_CFG, id), \
0149     SRI(FCNV_FP_SCALE_B, CNVC_CFG, id), \
0150     SRI(COLOR_KEYER_CONTROL, CNVC_CFG, id), \
0151     SRI(COLOR_KEYER_ALPHA, CNVC_CFG, id), \
0152     SRI(COLOR_KEYER_RED, CNVC_CFG, id), \
0153     SRI(COLOR_KEYER_GREEN, CNVC_CFG, id), \
0154     SRI(COLOR_KEYER_BLUE, CNVC_CFG, id), \
0155     SRI(CURSOR_CONTROL, CURSOR0_, id),\
0156     SRI(OBUF_MEM_PWR_CTRL, DSCL, id),\
0157     SRI(DSCL_MEM_PWR_STATUS, DSCL, id), \
0158     SRI(DSCL_MEM_PWR_CTRL, DSCL, id)
0159 
0160 #define DPP_REG_LIST_DCN30(id)\
0161     DPP_REG_LIST_DCN30_COMMON(id), \
0162     TF_REG_LIST_DCN20_COMMON(id), \
0163     SRI(CM_BLNDGAM_CONTROL, CM, id), \
0164     SRI(CM_SHAPER_LUT_DATA, CM, id),\
0165     SRI(CM_MEM_PWR_CTRL2, CM, id), \
0166     SRI(CM_MEM_PWR_STATUS2, CM, id), \
0167     SRI(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B, CM, id),\
0168     SRI(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G, CM, id),\
0169     SRI(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R, CM, id),\
0170     SRI(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B, CM, id),\
0171     SRI(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G, CM, id),\
0172     SRI(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R, CM, id),\
0173     SRI(CM_BLNDGAM_LUT_CONTROL, CM, id)
0174 
0175 
0176 
0177 #define DPP_REG_LIST_SH_MASK_DCN30_COMMON(mask_sh)\
0178     TF_SF(CM0_CM_MEM_PWR_STATUS, GAMCOR_MEM_PWR_STATE, mask_sh),\
0179     TF_SF(CM0_CM_DEALPHA, CM_DEALPHA_EN, mask_sh),\
0180     TF_SF(CM0_CM_DEALPHA, CM_DEALPHA_ABLND, mask_sh),\
0181     TF_SF(CM0_CM_BIAS_CR_R, CM_BIAS_CR_R, mask_sh),\
0182     TF_SF(CM0_CM_BIAS_Y_G_CB_B, CM_BIAS_Y_G, mask_sh),\
0183     TF_SF(CM0_CM_BIAS_Y_G_CB_B, CM_BIAS_CB_B, mask_sh),\
0184     TF_SF(CM0_CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_DIS, mask_sh),\
0185     TF_SF(CM0_CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_FORCE, mask_sh),\
0186     TF_SF(CNVC_CFG0_PRE_DEGAM, PRE_DEGAM_MODE, mask_sh),\
0187     TF_SF(CNVC_CFG0_PRE_DEGAM, PRE_DEGAM_SELECT, mask_sh),\
0188     TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_MODE, mask_sh),\
0189     TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_SELECT, mask_sh),\
0190     TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_PWL_DISABLE, mask_sh),\
0191     TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_MODE_CURRENT, mask_sh),\
0192     TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_SELECT_CURRENT, mask_sh),\
0193     TF_SF(CM0_CM_GAMCOR_LUT_INDEX, CM_GAMCOR_LUT_INDEX, mask_sh),\
0194     TF_SF(CM0_CM_GAMCOR_LUT_DATA, CM_GAMCOR_LUT_DATA, mask_sh),\
0195     TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_WRITE_COLOR_MASK, mask_sh),\
0196     TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_READ_COLOR_SEL, mask_sh),\
0197     TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_READ_DBG, mask_sh),\
0198     TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_HOST_SEL, mask_sh),\
0199     TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_CONFIG_MODE, mask_sh),\
0200     TF_SF(CM0_CM_GAMCOR_RAMA_START_CNTL_B, CM_GAMCOR_RAMA_EXP_REGION_START_B, mask_sh),\
0201     TF_SF(CM0_CM_GAMCOR_RAMA_START_CNTL_B, CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\
0202     TF_SF(CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B, mask_sh),\
0203     TF_SF(CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B, CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B, mask_sh),\
0204     TF_SF(CM0_CM_GAMCOR_RAMA_END_CNTL1_B, CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B, mask_sh),\
0205     TF_SF(CM0_CM_GAMCOR_RAMA_END_CNTL2_B, CM_GAMCOR_RAMA_EXP_REGION_END_B, mask_sh),\
0206     TF_SF(CM0_CM_GAMCOR_RAMA_END_CNTL2_B, CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\
0207     TF_SF(CM0_CM_GAMCOR_RAMA_OFFSET_B, CM_GAMCOR_RAMA_OFFSET_B, mask_sh),\
0208     TF_SF(CM0_CM_GAMCOR_RAMA_REGION_0_1, CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\
0209     TF_SF(CM0_CM_GAMCOR_RAMA_REGION_0_1, CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
0210     TF_SF(CM0_CM_GAMCOR_RAMA_REGION_0_1, CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\
0211     TF_SF(CM0_CM_GAMCOR_RAMA_REGION_0_1, CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
0212     TF_SF(CM0_CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE, mask_sh),\
0213     TF_SF(CM0_CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE_CURRENT, mask_sh),\
0214     TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C11, mask_sh),\
0215     TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C12, mask_sh),\
0216     TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C13, mask_sh),\
0217     TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C14, mask_sh),\
0218     TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C21, mask_sh),\
0219     TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C22, mask_sh),\
0220     TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C23, mask_sh),\
0221     TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C24, mask_sh),\
0222     TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C31, mask_sh),\
0223     TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C32, mask_sh),\
0224     TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C33, mask_sh),\
0225     TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C34, mask_sh),\
0226     TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh),\
0227     TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh),\
0228     TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh),\
0229     TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh),\
0230     TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_START, mask_sh),\
0231     TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_END, mask_sh),\
0232     TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_START, mask_sh),\
0233     TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_END, mask_sh),\
0234     TF_SF(DSCL0_LB_DATA_FORMAT, INTERLEAVE_EN, mask_sh),\
0235     TF2_SF(DSCL0, LB_DATA_FORMAT__ALPHA_EN, mask_sh),\
0236     TF_SF(DSCL0_LB_MEMORY_CTRL, MEMORY_CONFIG, mask_sh),\
0237     TF_SF(DSCL0_LB_MEMORY_CTRL, LB_MAX_PARTITIONS, mask_sh),\
0238     TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_MODE, mask_sh),\
0239     TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_NUM_PIPE, mask_sh),\
0240     TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_PIPE_ID, mask_sh),\
0241     TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS, mask_sh),\
0242     TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS, mask_sh),\
0243     TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS_C, mask_sh),\
0244     TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS_C, mask_sh),\
0245     TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\
0246     TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_PHASE, mask_sh),\
0247     TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_FILTER_TYPE, mask_sh),\
0248     TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\
0249     TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\
0250     TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\
0251     TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\
0252     TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh),\
0253     TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_EN, mask_sh),\
0254     TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_FACTOR, mask_sh),\
0255     TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh),\
0256     TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_EN, mask_sh),\
0257     TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_FACTOR, mask_sh),\
0258     TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT, mask_sh),\
0259     TF_SF(DSCL0_SCL_MODE, DSCL_MODE, mask_sh),\
0260     TF_SF(DSCL0_RECOUT_START, RECOUT_START_X, mask_sh),\
0261     TF_SF(DSCL0_RECOUT_START, RECOUT_START_Y, mask_sh),\
0262     TF_SF(DSCL0_RECOUT_SIZE, RECOUT_WIDTH, mask_sh),\
0263     TF_SF(DSCL0_RECOUT_SIZE, RECOUT_HEIGHT, mask_sh),\
0264     TF_SF(DSCL0_MPC_SIZE, MPC_WIDTH, mask_sh),\
0265     TF_SF(DSCL0_MPC_SIZE, MPC_HEIGHT, mask_sh),\
0266     TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh),\
0267     TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh),\
0268     TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C, SCL_H_SCALE_RATIO_C, mask_sh),\
0269     TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C, SCL_V_SCALE_RATIO_C, mask_sh),\
0270     TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh),\
0271     TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh),\
0272     TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_FRAC_C, mask_sh),\
0273     TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_INT_C, mask_sh),\
0274     TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh),\
0275     TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh),\
0276     TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_FRAC_C, mask_sh),\
0277     TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_INT_C, mask_sh),\
0278     TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\
0279     TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh), \
0280     TF_SF(CNVC_CFG0_PRE_DEALPHA, PRE_DEALPHA_EN, mask_sh), \
0281     TF_SF(CNVC_CFG0_PRE_DEALPHA, PRE_DEALPHA_ABLND_EN, mask_sh), \
0282     TF_SF(CNVC_CFG0_PRE_REALPHA, PRE_REALPHA_EN, mask_sh), \
0283     TF_SF(CNVC_CFG0_PRE_REALPHA, PRE_REALPHA_ABLND_EN, mask_sh), \
0284     TF_SF(CNVC_CFG0_PRE_CSC_MODE, PRE_CSC_MODE, mask_sh), \
0285     TF_SF(CNVC_CFG0_PRE_CSC_MODE, PRE_CSC_MODE_CURRENT, mask_sh), \
0286     TF_SF(CNVC_CFG0_PRE_CSC_C11_C12, PRE_CSC_C11, mask_sh), \
0287     TF_SF(CNVC_CFG0_PRE_CSC_C11_C12, PRE_CSC_C12, mask_sh), \
0288     TF_SF(CNVC_CFG0_PRE_CSC_C33_C34, PRE_CSC_C33, mask_sh), \
0289     TF_SF(CNVC_CFG0_PRE_CSC_C33_C34, PRE_CSC_C34, mask_sh), \
0290     TF_SF(CM0_CM_POST_CSC_CONTROL, CM_POST_CSC_MODE, mask_sh), \
0291     TF_SF(CM0_CM_POST_CSC_CONTROL, CM_POST_CSC_MODE_CURRENT, mask_sh), \
0292     TF_SF(CM0_CM_POST_CSC_C11_C12, CM_POST_CSC_C11, mask_sh), \
0293     TF_SF(CM0_CM_POST_CSC_C11_C12, CM_POST_CSC_C12, mask_sh), \
0294     TF_SF(CM0_CM_POST_CSC_C33_C34, CM_POST_CSC_C33, mask_sh), \
0295     TF_SF(CM0_CM_POST_CSC_C33_C34, CM_POST_CSC_C34, mask_sh), \
0296     TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \
0297     TF2_SF(CNVC_CFG0, FORMAT_CONTROL__ALPHA_EN, mask_sh), \
0298     TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \
0299     TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \
0300     TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_ALPHA_PLANE_ENABLE, mask_sh), \
0301     TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \
0302     TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_EXPANSION_MODE, mask_sh), \
0303     TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh), \
0304     TF_SF(CNVC_CUR0_CURSOR0_COLOR0, CUR0_COLOR0, mask_sh), \
0305     TF_SF(CNVC_CUR0_CURSOR0_COLOR1, CUR0_COLOR1, mask_sh), \
0306     TF_SF(CNVC_CUR0_CURSOR0_FP_SCALE_BIAS, CUR0_FP_BIAS, mask_sh), \
0307     TF_SF(CNVC_CUR0_CURSOR0_FP_SCALE_BIAS, CUR0_FP_SCALE, mask_sh), \
0308     TF_SF(DPP_TOP0_DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \
0309     TF_SF(CM0_CM_HDR_MULT_COEF, CM_HDR_MULT_COEF, mask_sh), \
0310     TF_SF(CM0_CM_CONTROL, CM_BYPASS, mask_sh), \
0311     TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
0312     TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
0313     TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
0314     TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
0315     TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CNV16, mask_sh), \
0316     TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, mask_sh), \
0317     TF_SF(CNVC_CFG0_FORMAT_CONTROL, CLAMP_POSITIVE, mask_sh), \
0318     TF_SF(CNVC_CFG0_FORMAT_CONTROL, CLAMP_POSITIVE_C, mask_sh), \
0319     TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CROSSBAR_R, mask_sh), \
0320     TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CROSSBAR_G, mask_sh), \
0321     TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CROSSBAR_B, mask_sh), \
0322     TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, mask_sh), \
0323     TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, mask_sh), \
0324     TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, mask_sh), \
0325     TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, mask_sh), \
0326     TF_SF(CNVC_CFG0_FCNV_FP_BIAS_R, FCNV_FP_BIAS_R, mask_sh), \
0327     TF_SF(CNVC_CFG0_FCNV_FP_BIAS_G, FCNV_FP_BIAS_G, mask_sh), \
0328     TF_SF(CNVC_CFG0_FCNV_FP_BIAS_B, FCNV_FP_BIAS_B, mask_sh), \
0329     TF_SF(CNVC_CFG0_FCNV_FP_SCALE_R, FCNV_FP_SCALE_R, mask_sh), \
0330     TF_SF(CNVC_CFG0_FCNV_FP_SCALE_G, FCNV_FP_SCALE_G, mask_sh), \
0331     TF_SF(CNVC_CFG0_FCNV_FP_SCALE_B, FCNV_FP_SCALE_B, mask_sh), \
0332     TF_SF(CNVC_CFG0_COLOR_KEYER_CONTROL, COLOR_KEYER_EN, mask_sh), \
0333     TF_SF(CNVC_CFG0_COLOR_KEYER_CONTROL, COLOR_KEYER_MODE, mask_sh), \
0334     TF_SF(CNVC_CFG0_COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_LOW, mask_sh), \
0335     TF_SF(CNVC_CFG0_COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_HIGH, mask_sh), \
0336     TF_SF(CNVC_CFG0_COLOR_KEYER_RED, COLOR_KEYER_RED_LOW, mask_sh), \
0337     TF_SF(CNVC_CFG0_COLOR_KEYER_RED, COLOR_KEYER_RED_HIGH, mask_sh), \
0338     TF_SF(CNVC_CFG0_COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_LOW, mask_sh), \
0339     TF_SF(CNVC_CFG0_COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_HIGH, mask_sh), \
0340     TF_SF(CNVC_CFG0_COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_LOW, mask_sh), \
0341     TF_SF(CNVC_CFG0_COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_HIGH, mask_sh), \
0342     TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_PIX_INV_MODE, mask_sh), \
0343     TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_PIXEL_ALPHA_MOD_EN, mask_sh), \
0344     TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ROM_EN, mask_sh),\
0345     TF_SF(DSCL0_OBUF_MEM_PWR_CTRL, OBUF_MEM_PWR_FORCE, mask_sh),\
0346     TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, mask_sh),\
0347     TF_SF(DSCL0_DSCL_MEM_PWR_STATUS, LUT_MEM_PWR_STATE, mask_sh)
0348 
0349 #define DPP_REG_LIST_SH_MASK_DCN30_UPDATED(mask_sh)\
0350     TF_SF(CM0_CM_MEM_PWR_STATUS, BLNDGAM_MEM_PWR_STATE, mask_sh), \
0351     TF_SF(CM0_CM_MEM_PWR_CTRL2, HDR3DLUT_MEM_PWR_FORCE, mask_sh),\
0352     TF_SF(CM0_CM_MEM_PWR_CTRL2, SHAPER_MEM_PWR_FORCE, mask_sh),\
0353     TF_SF(CM0_CM_MEM_PWR_STATUS2, HDR3DLUT_MEM_PWR_STATE, mask_sh),\
0354     TF_SF(CM0_CM_MEM_PWR_STATUS2, SHAPER_MEM_PWR_STATE, mask_sh),\
0355     TF_SF(CM0_CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE, mask_sh), \
0356     TF_SF(CM0_CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE_CURRENT, mask_sh), \
0357     TF_SF(CM0_CM_BLNDGAM_CONTROL, CM_BLNDGAM_SELECT_CURRENT, mask_sh), \
0358     TF_SF(CM0_CM_BLNDGAM_CONTROL, CM_BLNDGAM_SELECT, mask_sh), \
0359     TF_SF(CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B, CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B, mask_sh), \
0360     TF_SF(CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G, CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G, mask_sh), \
0361     TF_SF(CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R, CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R, mask_sh), \
0362     TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_B, CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \
0363     TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_G, CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \
0364     TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_R, CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \
0365     TF_SF(CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B, CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B, mask_sh), \
0366     TF_SF(CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G, CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G, mask_sh), \
0367     TF_SF(CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R, CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R, mask_sh), \
0368     TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_B, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \
0369     TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_G, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \
0370     TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_R, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \
0371     TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_B, CM_BLNDGAM_RAMA_EXP_REGION_END_B, mask_sh), \
0372     TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_G, CM_BLNDGAM_RAMA_EXP_REGION_END_G, mask_sh), \
0373     TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_R, CM_BLNDGAM_RAMA_EXP_REGION_END_R, mask_sh), \
0374     TF_SF(CM0_CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, mask_sh), \
0375     TF_SF(CM0_CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_HOST_SEL, mask_sh), \
0376     TF_SF(CM0_CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_CONFIG_MODE, mask_sh), \
0377     TF_SF(CM0_CM_3DLUT_MODE, CM_3DLUT_MODE_CURRENT, mask_sh), \
0378     TF_SF(CM0_CM_SHAPER_CONTROL, CM_SHAPER_MODE_CURRENT, mask_sh)
0379 
0380 
0381 #define DPP_REG_LIST_SH_MASK_DCN30(mask_sh)\
0382     DPP_REG_LIST_SH_MASK_DCN30_COMMON(mask_sh), \
0383     TF_REG_LIST_SH_MASK_DCN20_COMMON(mask_sh), \
0384     DPP_REG_LIST_SH_MASK_DCN30_UPDATED(mask_sh)
0385 
0386 #define DPP_REG_FIELD_LIST_DCN3(type) \
0387     TF_REG_FIELD_LIST_DCN2_0(type); \
0388     type FORMAT_CROSSBAR_R; \
0389     type FORMAT_CROSSBAR_G; \
0390     type FORMAT_CROSSBAR_B; \
0391     type CM_DEALPHA_EN;\
0392     type CM_DEALPHA_ABLND;\
0393     type CM_BIAS_Y_G;\
0394     type CM_BIAS_CB_B;\
0395     type CM_BIAS_CR_R;\
0396     type GAMCOR_MEM_PWR_DIS; \
0397     type GAMCOR_MEM_PWR_FORCE; \
0398     type HDR3DLUT_MEM_PWR_FORCE; \
0399     type SHAPER_MEM_PWR_FORCE; \
0400     type PRE_DEGAM_MODE;\
0401     type PRE_DEGAM_SELECT;\
0402     type CNVC_ALPHA_PLANE_ENABLE; \
0403     type PRE_DEALPHA_EN; \
0404     type PRE_DEALPHA_ABLND_EN; \
0405     type PRE_REALPHA_EN; \
0406     type PRE_REALPHA_ABLND_EN; \
0407     type PRE_CSC_MODE; \
0408     type PRE_CSC_MODE_CURRENT; \
0409     type PRE_CSC_C11; \
0410     type PRE_CSC_C12; \
0411     type PRE_CSC_C33; \
0412     type PRE_CSC_C34; \
0413     type CM_POST_CSC_MODE; \
0414     type CM_POST_CSC_MODE_CURRENT; \
0415     type CM_POST_CSC_C11; \
0416     type CM_POST_CSC_C12; \
0417     type CM_POST_CSC_C33; \
0418     type CM_POST_CSC_C34; \
0419     type CM_GAMCOR_MODE; \
0420     type CM_GAMCOR_SELECT; \
0421     type CM_GAMCOR_PWL_DISABLE; \
0422     type CM_GAMCOR_MODE_CURRENT; \
0423     type CM_GAMCOR_SELECT_CURRENT; \
0424     type CM_GAMCOR_LUT_INDEX; \
0425     type CM_GAMCOR_LUT_DATA; \
0426     type CM_GAMCOR_LUT_WRITE_COLOR_MASK; \
0427     type CM_GAMCOR_LUT_READ_COLOR_SEL; \
0428     type CM_GAMCOR_LUT_READ_DBG; \
0429     type CM_GAMCOR_LUT_HOST_SEL; \
0430     type CM_GAMCOR_LUT_CONFIG_MODE; \
0431     type CM_GAMCOR_LUT_STATUS; \
0432     type CM_GAMCOR_RAMA_EXP_REGION_START_B; \
0433     type CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B; \
0434     type CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B; \
0435     type CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B; \
0436     type CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B; \
0437     type CM_GAMCOR_RAMA_EXP_REGION_END_B; \
0438     type CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B; \
0439     type CM_GAMCOR_RAMA_OFFSET_B; \
0440     type CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET; \
0441     type CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS; \
0442     type CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET; \
0443     type CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS;\
0444     type CM_GAMUT_REMAP_MODE_CURRENT;\
0445     type CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B; \
0446     type CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G; \
0447     type CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R; \
0448     type CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B; \
0449     type CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G; \
0450     type CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R; \
0451     type CM_BLNDGAM_LUT_WRITE_COLOR_MASK; \
0452     type CM_BLNDGAM_LUT_HOST_SEL; \
0453     type CM_BLNDGAM_LUT_CONFIG_MODE; \
0454     type CM_3DLUT_MODE_CURRENT; \
0455     type CM_SHAPER_MODE_CURRENT; \
0456     type CM_BLNDGAM_MODE; \
0457     type CM_BLNDGAM_MODE_CURRENT; \
0458     type CM_BLNDGAM_SELECT_CURRENT; \
0459     type CM_BLNDGAM_SELECT; \
0460     type GAMCOR_MEM_PWR_STATE; \
0461     type BLNDGAM_MEM_PWR_STATE; \
0462     type HDR3DLUT_MEM_PWR_STATE; \
0463     type SHAPER_MEM_PWR_STATE
0464 
0465 struct dcn3_dpp_shift {
0466     DPP_REG_FIELD_LIST_DCN3(uint8_t);
0467 };
0468 
0469 struct dcn3_dpp_mask {
0470     DPP_REG_FIELD_LIST_DCN3(uint32_t);
0471 };
0472 
0473 #define DPP_DCN3_REG_VARIABLE_LIST_COMMON \
0474     DPP_DCN2_REG_VARIABLE_LIST; \
0475     uint32_t CM_MEM_PWR_STATUS;\
0476     uint32_t CM_MEM_PWR_STATUS2;\
0477     uint32_t CM_MEM_PWR_CTRL2;\
0478     uint32_t CM_DEALPHA;\
0479     uint32_t CM_BIAS_CR_R;\
0480     uint32_t CM_BIAS_Y_G_CB_B;\
0481     uint32_t PRE_DEGAM;\
0482     uint32_t PRE_DEALPHA; \
0483     uint32_t PRE_REALPHA; \
0484     uint32_t PRE_CSC_MODE; \
0485     uint32_t PRE_CSC_C11_C12; \
0486     uint32_t PRE_CSC_C33_C34; \
0487     uint32_t PRE_CSC_B_C11_C12; \
0488     uint32_t PRE_CSC_B_C33_C34; \
0489     uint32_t CM_POST_CSC_CONTROL; \
0490     uint32_t CM_POST_CSC_C11_C12; \
0491     uint32_t CM_POST_CSC_C33_C34; \
0492     uint32_t CM_POST_CSC_B_C11_C12; \
0493     uint32_t CM_POST_CSC_B_C33_C34; \
0494     uint32_t CM_GAMUT_REMAP_B_C11_C12; \
0495     uint32_t CM_GAMUT_REMAP_B_C13_C14; \
0496     uint32_t CM_GAMUT_REMAP_B_C21_C22; \
0497     uint32_t CM_GAMUT_REMAP_B_C23_C24; \
0498     uint32_t CM_GAMUT_REMAP_B_C31_C32; \
0499     uint32_t CM_GAMUT_REMAP_B_C33_C34; \
0500     uint32_t CM_GAMCOR_CONTROL; \
0501     uint32_t CM_GAMCOR_LUT_CONTROL; \
0502     uint32_t CM_GAMCOR_LUT_INDEX; \
0503     uint32_t CM_GAMCOR_LUT_DATA; \
0504     uint32_t CM_GAMCOR_RAMB_START_CNTL_B; \
0505     uint32_t CM_GAMCOR_RAMB_START_CNTL_G; \
0506     uint32_t CM_GAMCOR_RAMB_START_CNTL_R; \
0507     uint32_t CM_GAMCOR_RAMB_START_SLOPE_CNTL_B; \
0508     uint32_t CM_GAMCOR_RAMB_START_SLOPE_CNTL_G; \
0509     uint32_t CM_GAMCOR_RAMB_START_SLOPE_CNTL_R; \
0510     uint32_t CM_GAMCOR_RAMB_END_CNTL1_B; \
0511     uint32_t CM_GAMCOR_RAMB_END_CNTL2_B; \
0512     uint32_t CM_GAMCOR_RAMB_END_CNTL1_G; \
0513     uint32_t CM_GAMCOR_RAMB_END_CNTL2_G; \
0514     uint32_t CM_GAMCOR_RAMB_END_CNTL1_R; \
0515     uint32_t CM_GAMCOR_RAMB_END_CNTL2_R; \
0516     uint32_t CM_GAMCOR_RAMB_REGION_0_1; \
0517     uint32_t CM_GAMCOR_RAMB_REGION_32_33; \
0518     uint32_t CM_GAMCOR_RAMB_OFFSET_B; \
0519     uint32_t CM_GAMCOR_RAMB_OFFSET_G; \
0520     uint32_t CM_GAMCOR_RAMB_OFFSET_R; \
0521     uint32_t CM_GAMCOR_RAMB_START_BASE_CNTL_B; \
0522     uint32_t CM_GAMCOR_RAMB_START_BASE_CNTL_G; \
0523     uint32_t CM_GAMCOR_RAMB_START_BASE_CNTL_R; \
0524     uint32_t CM_GAMCOR_RAMA_START_CNTL_B; \
0525     uint32_t CM_GAMCOR_RAMA_START_CNTL_G; \
0526     uint32_t CM_GAMCOR_RAMA_START_CNTL_R; \
0527     uint32_t CM_GAMCOR_RAMA_START_SLOPE_CNTL_B; \
0528     uint32_t CM_GAMCOR_RAMA_START_SLOPE_CNTL_G; \
0529     uint32_t CM_GAMCOR_RAMA_START_SLOPE_CNTL_R; \
0530     uint32_t CM_GAMCOR_RAMA_END_CNTL1_B; \
0531     uint32_t CM_GAMCOR_RAMA_END_CNTL2_B; \
0532     uint32_t CM_GAMCOR_RAMA_END_CNTL1_G; \
0533     uint32_t CM_GAMCOR_RAMA_END_CNTL2_G; \
0534     uint32_t CM_GAMCOR_RAMA_END_CNTL1_R; \
0535     uint32_t CM_GAMCOR_RAMA_END_CNTL2_R; \
0536     uint32_t CM_GAMCOR_RAMA_REGION_0_1; \
0537     uint32_t CM_GAMCOR_RAMA_REGION_32_33; \
0538     uint32_t CM_GAMCOR_RAMA_OFFSET_B; \
0539     uint32_t CM_GAMCOR_RAMA_OFFSET_G; \
0540     uint32_t CM_GAMCOR_RAMA_OFFSET_R; \
0541     uint32_t CM_GAMCOR_RAMA_START_BASE_CNTL_B; \
0542     uint32_t CM_GAMCOR_RAMA_START_BASE_CNTL_G; \
0543     uint32_t CM_GAMCOR_RAMA_START_BASE_CNTL_R; \
0544     uint32_t CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B; \
0545     uint32_t CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G; \
0546     uint32_t CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R; \
0547     uint32_t CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B; \
0548     uint32_t CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G; \
0549     uint32_t CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R; \
0550     uint32_t CM_BLNDGAM_LUT_CONTROL
0551 
0552 
0553 struct dcn3_dpp_registers {
0554     DPP_DCN3_REG_VARIABLE_LIST_COMMON;
0555 };
0556 
0557 
0558 struct dcn3_dpp {
0559     struct dpp base;
0560 
0561     const struct dcn3_dpp_registers *tf_regs;
0562     const struct dcn3_dpp_shift *tf_shift;
0563     const struct dcn3_dpp_mask *tf_mask;
0564 
0565     const uint16_t *filter_v;
0566     const uint16_t *filter_h;
0567     const uint16_t *filter_v_c;
0568     const uint16_t *filter_h_c;
0569     int lb_pixel_depth_supported;
0570     int lb_memory_size;
0571     int lb_bits_per_entry;
0572     bool is_write_to_ram_a_safe;
0573     struct scaler_data scl_data;
0574     struct pwl_params pwl_data;
0575 };
0576 
0577 bool dpp3_construct(struct dcn3_dpp *dpp3,
0578     struct dc_context *ctx,
0579     uint32_t inst,
0580     const struct dcn3_dpp_registers *tf_regs,
0581     const struct dcn3_dpp_shift *tf_shift,
0582     const struct dcn3_dpp_mask *tf_mask);
0583 
0584 bool dpp3_program_gamcor_lut(
0585     struct dpp *dpp_base, const struct pwl_params *params);
0586 
0587 void dpp3_program_CM_dealpha(
0588         struct dpp *dpp_base,
0589         uint32_t enable, uint32_t additive_blending);
0590 
0591 void dpp30_read_state(struct dpp *dpp_base,
0592         struct dcn_dpp_state *s);
0593 
0594 bool dpp3_get_optimal_number_of_taps(
0595         struct dpp *dpp,
0596         struct scaler_data *scl_data,
0597         const struct scaling_taps *in_taps);
0598 
0599 void dpp3_cnv_setup (
0600         struct dpp *dpp_base,
0601         enum surface_pixel_format format,
0602         enum expansion_mode mode,
0603         struct dc_csc_transform input_csc_color_matrix,
0604         enum dc_color_space input_color_space,
0605         struct cnv_alpha_2bit_lut *alpha_2bit_lut);
0606 
0607 void dpp3_program_CM_bias(
0608         struct dpp *dpp_base,
0609         struct CM_bias_params *bias_params);
0610 
0611 void dpp3_set_hdr_multiplier(
0612         struct dpp *dpp_base,
0613         uint32_t multiplier);
0614 
0615 void dpp3_cm_set_gamut_remap(
0616         struct dpp *dpp_base,
0617         const struct dpp_grph_csc_adjustment *adjust);
0618 
0619 void dpp3_set_pre_degam(struct dpp *dpp_base,
0620         enum dc_transfer_func_predefined tr);
0621 
0622 void dpp3_set_cursor_attributes(
0623         struct dpp *dpp_base,
0624         struct dc_cursor_attributes *cursor_attributes);
0625 
0626 void dpp3_program_post_csc(
0627         struct dpp *dpp_base,
0628         enum dc_color_space color_space,
0629         enum dcn10_input_csc_select input_select,
0630         const struct out_csc_color_matrix *tbl_entry);
0631 
0632 void dpp3_program_cm_bias(
0633     struct dpp *dpp_base,
0634     struct CM_bias_params *bias_params);
0635 
0636 void dpp3_program_cm_dealpha(
0637         struct dpp *dpp_base,
0638     uint32_t enable, uint32_t additive_blending);
0639 
0640 #endif /* __DC_HWSS_DCN30_H__ */
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