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0001 /*
0002  * Copyright 2020 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 
0026 #include "dm_services.h"
0027 #include "core_types.h"
0028 #include "reg_helper.h"
0029 #include "dcn30_dpp.h"
0030 #include "basics/conversion.h"
0031 #include "dcn30_cm_common.h"
0032 
0033 #define REG(reg)\
0034     dpp->tf_regs->reg
0035 
0036 #define CTX \
0037     dpp->base.ctx
0038 
0039 #undef FN
0040 #define FN(reg_name, field_name) \
0041     dpp->tf_shift->field_name, dpp->tf_mask->field_name
0042 
0043 
0044 void dpp30_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s)
0045 {
0046     struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
0047 
0048     REG_GET(DPP_CONTROL,
0049             DPP_CLOCK_ENABLE, &s->is_enabled);
0050 
0051     // TODO: Implement for DCN3
0052 }
0053 /*program post scaler scs block in dpp CM*/
0054 void dpp3_program_post_csc(
0055         struct dpp *dpp_base,
0056         enum dc_color_space color_space,
0057         enum dcn10_input_csc_select input_select,
0058         const struct out_csc_color_matrix *tbl_entry)
0059 {
0060     struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
0061     int i;
0062     int arr_size = sizeof(dpp_input_csc_matrix)/sizeof(struct dpp_input_csc_matrix);
0063     const uint16_t *regval = NULL;
0064     uint32_t cur_select = 0;
0065     enum dcn10_input_csc_select select;
0066     struct color_matrices_reg gam_regs;
0067 
0068     if (input_select == INPUT_CSC_SELECT_BYPASS) {
0069         REG_SET(CM_POST_CSC_CONTROL, 0, CM_POST_CSC_MODE, 0);
0070         return;
0071     }
0072 
0073     if (tbl_entry == NULL) {
0074         for (i = 0; i < arr_size; i++)
0075             if (dpp_input_csc_matrix[i].color_space == color_space) {
0076                 regval = dpp_input_csc_matrix[i].regval;
0077                 break;
0078             }
0079 
0080         if (regval == NULL) {
0081             BREAK_TO_DEBUGGER();
0082             return;
0083         }
0084     } else {
0085         regval = tbl_entry->regval;
0086     }
0087 
0088     /* determine which CSC matrix (icsc or coma) we are using
0089      * currently.  select the alternate set to double buffer
0090      * the CSC update so CSC is updated on frame boundary
0091      */
0092     REG_GET(CM_POST_CSC_CONTROL,
0093             CM_POST_CSC_MODE_CURRENT, &cur_select);
0094 
0095     if (cur_select != INPUT_CSC_SELECT_ICSC)
0096         select = INPUT_CSC_SELECT_ICSC;
0097     else
0098         select = INPUT_CSC_SELECT_COMA;
0099 
0100     gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_POST_CSC_C11;
0101     gam_regs.masks.csc_c11  = dpp->tf_mask->CM_POST_CSC_C11;
0102     gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_POST_CSC_C12;
0103     gam_regs.masks.csc_c12 = dpp->tf_mask->CM_POST_CSC_C12;
0104 
0105     if (select == INPUT_CSC_SELECT_ICSC) {
0106 
0107         gam_regs.csc_c11_c12 = REG(CM_POST_CSC_C11_C12);
0108         gam_regs.csc_c33_c34 = REG(CM_POST_CSC_C33_C34);
0109 
0110     } else {
0111 
0112         gam_regs.csc_c11_c12 = REG(CM_POST_CSC_B_C11_C12);
0113         gam_regs.csc_c33_c34 = REG(CM_POST_CSC_B_C33_C34);
0114 
0115     }
0116 
0117     cm_helper_program_color_matrices(
0118             dpp->base.ctx,
0119             regval,
0120             &gam_regs);
0121 
0122     REG_SET(CM_POST_CSC_CONTROL, 0,
0123             CM_POST_CSC_MODE, select);
0124 }
0125 
0126 
0127 /*CNVC degam unit has read only LUTs*/
0128 void dpp3_set_pre_degam(struct dpp *dpp_base, enum dc_transfer_func_predefined tr)
0129 {
0130     struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
0131     int pre_degam_en = 1;
0132     int degamma_lut_selection = 0;
0133 
0134     switch (tr) {
0135     case TRANSFER_FUNCTION_LINEAR:
0136     case TRANSFER_FUNCTION_UNITY:
0137         pre_degam_en = 0; //bypass
0138         break;
0139     case TRANSFER_FUNCTION_SRGB:
0140         degamma_lut_selection = 0;
0141         break;
0142     case TRANSFER_FUNCTION_BT709:
0143         degamma_lut_selection = 4;
0144         break;
0145     case TRANSFER_FUNCTION_PQ:
0146         degamma_lut_selection = 5;
0147         break;
0148     case TRANSFER_FUNCTION_HLG:
0149         degamma_lut_selection = 6;
0150         break;
0151     case TRANSFER_FUNCTION_GAMMA22:
0152         degamma_lut_selection = 1;
0153         break;
0154     case TRANSFER_FUNCTION_GAMMA24:
0155         degamma_lut_selection = 2;
0156         break;
0157     case TRANSFER_FUNCTION_GAMMA26:
0158         degamma_lut_selection = 3;
0159         break;
0160     default:
0161         pre_degam_en = 0;
0162         break;
0163     }
0164 
0165     REG_SET_2(PRE_DEGAM, 0,
0166             PRE_DEGAM_MODE, pre_degam_en,
0167             PRE_DEGAM_SELECT, degamma_lut_selection);
0168 }
0169 
0170 void dpp3_cnv_setup (
0171         struct dpp *dpp_base,
0172         enum surface_pixel_format format,
0173         enum expansion_mode mode,
0174         struct dc_csc_transform input_csc_color_matrix,
0175         enum dc_color_space input_color_space,
0176         struct cnv_alpha_2bit_lut *alpha_2bit_lut)
0177 {
0178     struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
0179     uint32_t pixel_format = 0;
0180     uint32_t alpha_en = 1;
0181     enum dc_color_space color_space = COLOR_SPACE_SRGB;
0182     enum dcn10_input_csc_select select = INPUT_CSC_SELECT_BYPASS;
0183     bool force_disable_cursor = false;
0184     uint32_t is_2bit = 0;
0185     uint32_t alpha_plane_enable = 0;
0186     uint32_t dealpha_en = 0, dealpha_ablnd_en = 0;
0187     uint32_t realpha_en = 0, realpha_ablnd_en = 0;
0188     uint32_t program_prealpha_dealpha = 0;
0189     struct out_csc_color_matrix tbl_entry;
0190     int i;
0191 
0192     REG_SET_2(FORMAT_CONTROL, 0,
0193         CNVC_BYPASS, 0,
0194         FORMAT_EXPANSION_MODE, mode);
0195 
0196     REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0);
0197     REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0);
0198     REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0);
0199     REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0);
0200 
0201     REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_R, 0);
0202     REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_G, 1);
0203     REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_B, 2);
0204 
0205     switch (format) {
0206     case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
0207         pixel_format = 1;
0208         break;
0209     case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
0210         pixel_format = 3;
0211         alpha_en = 0;
0212         break;
0213     case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
0214     case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
0215         pixel_format = 8;
0216         break;
0217     case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
0218     case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
0219         pixel_format = 10;
0220         is_2bit = 1;
0221         break;
0222     case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
0223         force_disable_cursor = false;
0224         pixel_format = 65;
0225         color_space = COLOR_SPACE_YCBCR709;
0226         select = INPUT_CSC_SELECT_ICSC;
0227         break;
0228     case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
0229         force_disable_cursor = true;
0230         pixel_format = 64;
0231         color_space = COLOR_SPACE_YCBCR709;
0232         select = INPUT_CSC_SELECT_ICSC;
0233         break;
0234     case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
0235         force_disable_cursor = true;
0236         pixel_format = 67;
0237         color_space = COLOR_SPACE_YCBCR709;
0238         select = INPUT_CSC_SELECT_ICSC;
0239         break;
0240     case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
0241         force_disable_cursor = true;
0242         pixel_format = 66;
0243         color_space = COLOR_SPACE_YCBCR709;
0244         select = INPUT_CSC_SELECT_ICSC;
0245         break;
0246     case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
0247     case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
0248         pixel_format = 26; /* ARGB16161616_UNORM */
0249         break;
0250     case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
0251         pixel_format = 24;
0252         break;
0253     case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
0254         pixel_format = 25;
0255         break;
0256     case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888:
0257         pixel_format = 12;
0258         color_space = COLOR_SPACE_YCBCR709;
0259         select = INPUT_CSC_SELECT_ICSC;
0260         break;
0261     case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
0262         pixel_format = 112;
0263         break;
0264     case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
0265         pixel_format = 113;
0266         break;
0267     case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:
0268         pixel_format = 114;
0269         color_space = COLOR_SPACE_YCBCR709;
0270         select = INPUT_CSC_SELECT_ICSC;
0271         is_2bit = 1;
0272         break;
0273     case SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102:
0274         pixel_format = 115;
0275         color_space = COLOR_SPACE_YCBCR709;
0276         select = INPUT_CSC_SELECT_ICSC;
0277         is_2bit = 1;
0278         break;
0279     case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
0280         pixel_format = 116;
0281         alpha_plane_enable = 0;
0282         break;
0283     case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
0284         pixel_format = 116;
0285         alpha_plane_enable = 1;
0286         break;
0287     case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
0288         pixel_format = 118;
0289         break;
0290     case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
0291         pixel_format = 119;
0292         break;
0293     default:
0294         break;
0295     }
0296 
0297     /* Set default color space based on format if none is given. */
0298     color_space = input_color_space ? input_color_space : color_space;
0299 
0300     if (is_2bit == 1 && alpha_2bit_lut != NULL) {
0301         REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);
0302         REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);
0303         REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2);
0304         REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3);
0305     }
0306 
0307     REG_SET_2(CNVC_SURFACE_PIXEL_FORMAT, 0,
0308             CNVC_SURFACE_PIXEL_FORMAT, pixel_format,
0309             CNVC_ALPHA_PLANE_ENABLE, alpha_plane_enable);
0310     REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
0311 
0312     if (program_prealpha_dealpha) {
0313         dealpha_en = 1;
0314         realpha_en = 1;
0315     }
0316     REG_SET_2(PRE_DEALPHA, 0,
0317             PRE_DEALPHA_EN, dealpha_en,
0318             PRE_DEALPHA_ABLND_EN, dealpha_ablnd_en);
0319     REG_SET_2(PRE_REALPHA, 0,
0320             PRE_REALPHA_EN, realpha_en,
0321             PRE_REALPHA_ABLND_EN, realpha_ablnd_en);
0322 
0323     /* If input adjustment exists, program the ICSC with those values. */
0324     if (input_csc_color_matrix.enable_adjustment == true) {
0325         for (i = 0; i < 12; i++)
0326             tbl_entry.regval[i] = input_csc_color_matrix.matrix[i];
0327 
0328         tbl_entry.color_space = input_color_space;
0329 
0330         if (color_space >= COLOR_SPACE_YCBCR601)
0331             select = INPUT_CSC_SELECT_ICSC;
0332         else
0333             select = INPUT_CSC_SELECT_BYPASS;
0334 
0335         dpp3_program_post_csc(dpp_base, color_space, select,
0336                       &tbl_entry);
0337     } else {
0338         dpp3_program_post_csc(dpp_base, color_space, select, NULL);
0339     }
0340 
0341     if (force_disable_cursor) {
0342         REG_UPDATE(CURSOR_CONTROL,
0343                 CURSOR_ENABLE, 0);
0344         REG_UPDATE(CURSOR0_CONTROL,
0345                 CUR0_ENABLE, 0);
0346     }
0347 }
0348 
0349 #define IDENTITY_RATIO(ratio) (dc_fixpt_u3d19(ratio) == (1 << 19))
0350 
0351 void dpp3_set_cursor_attributes(
0352         struct dpp *dpp_base,
0353         struct dc_cursor_attributes *cursor_attributes)
0354 {
0355     enum dc_cursor_color_format color_format = cursor_attributes->color_format;
0356     struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
0357     int cur_rom_en = 0;
0358 
0359     if (color_format == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA ||
0360         color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA)
0361         cur_rom_en = 1;
0362 
0363     REG_UPDATE_3(CURSOR0_CONTROL,
0364             CUR0_MODE, color_format,
0365             CUR0_EXPANSION_MODE, 0,
0366             CUR0_ROM_EN, cur_rom_en);
0367 
0368     if (color_format == CURSOR_MODE_MONO) {
0369         /* todo: clarify what to program these to */
0370         REG_UPDATE(CURSOR0_COLOR0,
0371                 CUR0_COLOR0, 0x00000000);
0372         REG_UPDATE(CURSOR0_COLOR1,
0373                 CUR0_COLOR1, 0xFFFFFFFF);
0374     }
0375 }
0376 
0377 
0378 bool dpp3_get_optimal_number_of_taps(
0379         struct dpp *dpp,
0380         struct scaler_data *scl_data,
0381         const struct scaling_taps *in_taps)
0382 {
0383     int num_part_y, num_part_c;
0384     int max_taps_y, max_taps_c;
0385     int min_taps_y, min_taps_c;
0386     enum lb_memory_config lb_config;
0387 
0388     if (scl_data->viewport.width > scl_data->h_active &&
0389         dpp->ctx->dc->debug.max_downscale_src_width != 0 &&
0390         scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)
0391         return false;
0392 
0393     /*
0394      * Set default taps if none are provided
0395      * From programming guide: taps = min{ ceil(2*H_RATIO,1), 8} for downscaling
0396      * taps = 4 for upscaling
0397      */
0398     if (in_taps->h_taps == 0) {
0399         if (dc_fixpt_ceil(scl_data->ratios.horz) > 1)
0400             scl_data->taps.h_taps = min(2 * dc_fixpt_ceil(scl_data->ratios.horz), 8);
0401         else
0402             scl_data->taps.h_taps = 4;
0403     } else
0404         scl_data->taps.h_taps = in_taps->h_taps;
0405     if (in_taps->v_taps == 0) {
0406         if (dc_fixpt_ceil(scl_data->ratios.vert) > 1)
0407             scl_data->taps.v_taps = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert, 2)), 8);
0408         else
0409             scl_data->taps.v_taps = 4;
0410     } else
0411         scl_data->taps.v_taps = in_taps->v_taps;
0412     if (in_taps->v_taps_c == 0) {
0413         if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 1)
0414             scl_data->taps.v_taps_c = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert_c, 2)), 8);
0415         else
0416             scl_data->taps.v_taps_c = 4;
0417     } else
0418         scl_data->taps.v_taps_c = in_taps->v_taps_c;
0419     if (in_taps->h_taps_c == 0) {
0420         if (dc_fixpt_ceil(scl_data->ratios.horz_c) > 1)
0421             scl_data->taps.h_taps_c = min(2 * dc_fixpt_ceil(scl_data->ratios.horz_c), 8);
0422         else
0423             scl_data->taps.h_taps_c = 4;
0424     } else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1)
0425         /* Only 1 and even h_taps_c are supported by hw */
0426         scl_data->taps.h_taps_c = in_taps->h_taps_c - 1;
0427     else
0428         scl_data->taps.h_taps_c = in_taps->h_taps_c;
0429 
0430     /*Ensure we can support the requested number of vtaps*/
0431     min_taps_y = dc_fixpt_ceil(scl_data->ratios.vert);
0432     min_taps_c = dc_fixpt_ceil(scl_data->ratios.vert_c);
0433 
0434     /* Use LB_MEMORY_CONFIG_3 for 4:2:0 */
0435     if ((scl_data->format == PIXEL_FORMAT_420BPP8) || (scl_data->format == PIXEL_FORMAT_420BPP10))
0436         lb_config = LB_MEMORY_CONFIG_3;
0437     else
0438         lb_config = LB_MEMORY_CONFIG_0;
0439 
0440     dpp->caps->dscl_calc_lb_num_partitions(
0441             scl_data, lb_config, &num_part_y, &num_part_c);
0442 
0443     /* MAX_V_TAPS = MIN (NUM_LINES - MAX(CEILING(V_RATIO,1)-2, 0), 8) */
0444     if (dc_fixpt_ceil(scl_data->ratios.vert) > 2)
0445         max_taps_y = num_part_y - (dc_fixpt_ceil(scl_data->ratios.vert) - 2);
0446     else
0447         max_taps_y = num_part_y;
0448 
0449     if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 2)
0450         max_taps_c = num_part_c - (dc_fixpt_ceil(scl_data->ratios.vert_c) - 2);
0451     else
0452         max_taps_c = num_part_c;
0453 
0454     if (max_taps_y < min_taps_y)
0455         return false;
0456     else if (max_taps_c < min_taps_c)
0457         return false;
0458 
0459     if (scl_data->taps.v_taps > max_taps_y)
0460         scl_data->taps.v_taps = max_taps_y;
0461 
0462     if (scl_data->taps.v_taps_c > max_taps_c)
0463         scl_data->taps.v_taps_c = max_taps_c;
0464 
0465     if (!dpp->ctx->dc->debug.always_scale) {
0466         if (IDENTITY_RATIO(scl_data->ratios.horz))
0467             scl_data->taps.h_taps = 1;
0468         if (IDENTITY_RATIO(scl_data->ratios.vert))
0469             scl_data->taps.v_taps = 1;
0470         if (IDENTITY_RATIO(scl_data->ratios.horz_c))
0471             scl_data->taps.h_taps_c = 1;
0472         if (IDENTITY_RATIO(scl_data->ratios.vert_c))
0473             scl_data->taps.v_taps_c = 1;
0474     }
0475 
0476     return true;
0477 }
0478 
0479 static void dpp3_deferred_update(struct dpp *dpp_base)
0480 {
0481     int bypass_state;
0482     struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
0483 
0484     if (dpp_base->deferred_reg_writes.bits.disable_dscl) {
0485         REG_UPDATE(DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, 3);
0486         dpp_base->deferred_reg_writes.bits.disable_dscl = false;
0487     }
0488 
0489     if (dpp_base->deferred_reg_writes.bits.disable_gamcor) {
0490         REG_GET(CM_GAMCOR_CONTROL, CM_GAMCOR_MODE_CURRENT, &bypass_state);
0491         if (bypass_state == 0) {    // only program if bypass was latched
0492             REG_UPDATE(CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_FORCE, 3);
0493         } else
0494             ASSERT(0); // LUT select was updated again before vupdate
0495         dpp_base->deferred_reg_writes.bits.disable_gamcor = false;
0496     }
0497 
0498     if (dpp_base->deferred_reg_writes.bits.disable_blnd_lut) {
0499         REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE_CURRENT, &bypass_state);
0500         if (bypass_state == 0) {    // only program if bypass was latched
0501             REG_UPDATE(CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, 3);
0502         } else
0503             ASSERT(0); // LUT select was updated again before vupdate
0504         dpp_base->deferred_reg_writes.bits.disable_blnd_lut = false;
0505     }
0506 
0507     if (dpp_base->deferred_reg_writes.bits.disable_3dlut) {
0508         REG_GET(CM_3DLUT_MODE, CM_3DLUT_MODE_CURRENT, &bypass_state);
0509         if (bypass_state == 0) {    // only program if bypass was latched
0510             REG_UPDATE(CM_MEM_PWR_CTRL2, HDR3DLUT_MEM_PWR_FORCE, 3);
0511         } else
0512             ASSERT(0); // LUT select was updated again before vupdate
0513         dpp_base->deferred_reg_writes.bits.disable_3dlut = false;
0514     }
0515 
0516     if (dpp_base->deferred_reg_writes.bits.disable_shaper) {
0517         REG_GET(CM_SHAPER_CONTROL, CM_SHAPER_MODE_CURRENT, &bypass_state);
0518         if (bypass_state == 0) {    // only program if bypass was latched
0519             REG_UPDATE(CM_MEM_PWR_CTRL2, SHAPER_MEM_PWR_FORCE, 3);
0520         } else
0521             ASSERT(0); // LUT select was updated again before vupdate
0522         dpp_base->deferred_reg_writes.bits.disable_shaper = false;
0523     }
0524 }
0525 
0526 static void dpp3_power_on_blnd_lut(
0527     struct dpp *dpp_base,
0528     bool power_on)
0529 {
0530     struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
0531 
0532     if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {
0533         if (power_on) {
0534             REG_UPDATE(CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, 0);
0535             REG_WAIT(CM_MEM_PWR_STATUS, BLNDGAM_MEM_PWR_STATE, 0, 1, 5);
0536         } else {
0537             dpp_base->ctx->dc->optimized_required = true;
0538             dpp_base->deferred_reg_writes.bits.disable_blnd_lut = true;
0539         }
0540     } else {
0541         REG_SET(CM_MEM_PWR_CTRL, 0,
0542                 BLNDGAM_MEM_PWR_FORCE, power_on == true ? 0 : 1);
0543     }
0544 }
0545 
0546 static void dpp3_power_on_hdr3dlut(
0547     struct dpp *dpp_base,
0548     bool power_on)
0549 {
0550     struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
0551 
0552     if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {
0553         if (power_on) {
0554             REG_UPDATE(CM_MEM_PWR_CTRL2, HDR3DLUT_MEM_PWR_FORCE, 0);
0555             REG_WAIT(CM_MEM_PWR_STATUS2, HDR3DLUT_MEM_PWR_STATE, 0, 1, 5);
0556         } else {
0557             dpp_base->ctx->dc->optimized_required = true;
0558             dpp_base->deferred_reg_writes.bits.disable_3dlut = true;
0559         }
0560     }
0561 }
0562 
0563 static void dpp3_power_on_shaper(
0564     struct dpp *dpp_base,
0565     bool power_on)
0566 {
0567     struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
0568 
0569     if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {
0570         if (power_on) {
0571             REG_UPDATE(CM_MEM_PWR_CTRL2, SHAPER_MEM_PWR_FORCE, 0);
0572             REG_WAIT(CM_MEM_PWR_STATUS2, SHAPER_MEM_PWR_STATE, 0, 1, 5);
0573         } else {
0574             dpp_base->ctx->dc->optimized_required = true;
0575             dpp_base->deferred_reg_writes.bits.disable_shaper = true;
0576         }
0577     }
0578 }
0579 
0580 static void dpp3_configure_blnd_lut(
0581         struct dpp *dpp_base,
0582         bool is_ram_a)
0583 {
0584     struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
0585 
0586     REG_UPDATE_2(CM_BLNDGAM_LUT_CONTROL,
0587             CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 7,
0588             CM_BLNDGAM_LUT_HOST_SEL, is_ram_a == true ? 0 : 1);
0589 
0590     REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0);
0591 }
0592 
0593 static void dpp3_program_blnd_pwl(
0594         struct dpp *dpp_base,
0595         const struct pwl_result_data *rgb,
0596         uint32_t num)
0597 {
0598     uint32_t i;
0599     struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
0600     uint32_t last_base_value_red = rgb[num-1].red_reg + rgb[num-1].delta_red_reg;
0601     uint32_t last_base_value_green = rgb[num-1].green_reg + rgb[num-1].delta_green_reg;
0602     uint32_t last_base_value_blue = rgb[num-1].blue_reg + rgb[num-1].delta_blue_reg;
0603 
0604     if (is_rgb_equal(rgb, num)) {
0605         for (i = 0 ; i < num; i++)
0606             REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg);
0607         REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_red);
0608     } else {
0609         REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 4);
0610         for (i = 0 ; i < num; i++)
0611             REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg);
0612         REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_red);
0613 
0614         REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 2);
0615         for (i = 0 ; i < num; i++)
0616             REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].green_reg);
0617         REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_green);
0618 
0619         REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 1);
0620         for (i = 0 ; i < num; i++)
0621             REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].blue_reg);
0622         REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_blue);
0623     }
0624 }
0625 
0626 static void dcn3_dpp_cm_get_reg_field(
0627         struct dcn3_dpp *dpp,
0628         struct dcn3_xfer_func_reg *reg)
0629 {
0630     reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;
0631     reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;
0632     reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
0633     reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
0634     reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;
0635     reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;
0636     reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
0637     reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
0638 
0639     reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B;
0640     reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B;
0641     reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;
0642     reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;
0643     reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;
0644     reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;
0645     reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B;
0646     reg->masks.field_region_linear_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B;
0647     reg->shifts.exp_region_start = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_B;
0648     reg->masks.exp_region_start = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_B;
0649     reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;
0650     reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;
0651 }
0652 
0653 /*program blnd lut RAM A*/
0654 static void dpp3_program_blnd_luta_settings(
0655         struct dpp *dpp_base,
0656         const struct pwl_params *params)
0657 {
0658     struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
0659     struct dcn3_xfer_func_reg gam_regs;
0660 
0661     dcn3_dpp_cm_get_reg_field(dpp, &gam_regs);
0662 
0663     gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMA_START_CNTL_B);
0664     gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMA_START_CNTL_G);
0665     gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMA_START_CNTL_R);
0666     gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B);
0667     gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G);
0668     gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R);
0669     gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMA_END_CNTL1_B);
0670     gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMA_END_CNTL2_B);
0671     gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMA_END_CNTL1_G);
0672     gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMA_END_CNTL2_G);
0673     gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMA_END_CNTL1_R);
0674     gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMA_END_CNTL2_R);
0675     gam_regs.region_start = REG(CM_BLNDGAM_RAMA_REGION_0_1);
0676     gam_regs.region_end = REG(CM_BLNDGAM_RAMA_REGION_32_33);
0677 
0678     cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs);
0679 }
0680 
0681 /*program blnd lut RAM B*/
0682 static void dpp3_program_blnd_lutb_settings(
0683         struct dpp *dpp_base,
0684         const struct pwl_params *params)
0685 {
0686     struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
0687     struct dcn3_xfer_func_reg gam_regs;
0688 
0689     dcn3_dpp_cm_get_reg_field(dpp, &gam_regs);
0690 
0691     gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMB_START_CNTL_B);
0692     gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMB_START_CNTL_G);
0693     gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMB_START_CNTL_R);
0694     gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B);
0695     gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G);
0696     gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R);
0697     gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMB_END_CNTL1_B);
0698     gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMB_END_CNTL2_B);
0699     gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMB_END_CNTL1_G);
0700     gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMB_END_CNTL2_G);
0701     gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMB_END_CNTL1_R);
0702     gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMB_END_CNTL2_R);
0703     gam_regs.region_start = REG(CM_BLNDGAM_RAMB_REGION_0_1);
0704     gam_regs.region_end = REG(CM_BLNDGAM_RAMB_REGION_32_33);
0705 
0706     cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs);
0707 }
0708 
0709 static enum dc_lut_mode dpp3_get_blndgam_current(struct dpp *dpp_base)
0710 {
0711     enum dc_lut_mode mode;
0712     uint32_t mode_current = 0;
0713     uint32_t in_use = 0;
0714 
0715     struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
0716 
0717     REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE_CURRENT, &mode_current);
0718     REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_SELECT_CURRENT, &in_use);
0719 
0720     switch (mode_current) {
0721     case 0:
0722     case 1:
0723         mode = LUT_BYPASS;
0724         break;
0725 
0726     case 2:
0727         if (in_use == 0)
0728             mode = LUT_RAM_A;
0729         else
0730             mode = LUT_RAM_B;
0731         break;
0732     default:
0733         mode = LUT_BYPASS;
0734         break;
0735     }
0736 
0737     return mode;
0738 }
0739 
0740 static bool dpp3_program_blnd_lut(struct dpp *dpp_base,
0741                   const struct pwl_params *params)
0742 {
0743     enum dc_lut_mode current_mode;
0744     enum dc_lut_mode next_mode;
0745     struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
0746 
0747     if (params == NULL) {
0748         REG_SET(CM_BLNDGAM_CONTROL, 0, CM_BLNDGAM_MODE, 0);
0749         if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
0750             dpp3_power_on_blnd_lut(dpp_base, false);
0751         return false;
0752     }
0753 
0754     current_mode = dpp3_get_blndgam_current(dpp_base);
0755     if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_B)
0756         next_mode = LUT_RAM_A;
0757     else
0758         next_mode = LUT_RAM_B;
0759 
0760     dpp3_power_on_blnd_lut(dpp_base, true);
0761     dpp3_configure_blnd_lut(dpp_base, next_mode == LUT_RAM_A);
0762 
0763     if (next_mode == LUT_RAM_A)
0764         dpp3_program_blnd_luta_settings(dpp_base, params);
0765     else
0766         dpp3_program_blnd_lutb_settings(dpp_base, params);
0767 
0768     dpp3_program_blnd_pwl(
0769             dpp_base, params->rgb_resulted, params->hw_points_num);
0770 
0771     REG_UPDATE_2(CM_BLNDGAM_CONTROL,
0772             CM_BLNDGAM_MODE, 2,
0773             CM_BLNDGAM_SELECT, next_mode == LUT_RAM_A ? 0 : 1);
0774 
0775     return true;
0776 }
0777 
0778 
0779 static void dpp3_program_shaper_lut(
0780         struct dpp *dpp_base,
0781         const struct pwl_result_data *rgb,
0782         uint32_t num)
0783 {
0784     uint32_t i, red, green, blue;
0785     uint32_t  red_delta, green_delta, blue_delta;
0786     uint32_t  red_value, green_value, blue_value;
0787 
0788     struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
0789 
0790     for (i = 0 ; i < num; i++) {
0791 
0792         red   = rgb[i].red_reg;
0793         green = rgb[i].green_reg;
0794         blue  = rgb[i].blue_reg;
0795 
0796         red_delta   = rgb[i].delta_red_reg;
0797         green_delta = rgb[i].delta_green_reg;
0798         blue_delta  = rgb[i].delta_blue_reg;
0799 
0800         red_value   = ((red_delta   & 0x3ff) << 14) | (red   & 0x3fff);
0801         green_value = ((green_delta & 0x3ff) << 14) | (green & 0x3fff);
0802         blue_value  = ((blue_delta  & 0x3ff) << 14) | (blue  & 0x3fff);
0803 
0804         REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, red_value);
0805         REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, green_value);
0806         REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, blue_value);
0807     }
0808 
0809 }
0810 
0811 static enum dc_lut_mode dpp3_get_shaper_current(struct dpp *dpp_base)
0812 {
0813     enum dc_lut_mode mode;
0814     uint32_t state_mode;
0815     struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
0816 
0817     REG_GET(CM_SHAPER_CONTROL, CM_SHAPER_MODE_CURRENT, &state_mode);
0818 
0819     switch (state_mode) {
0820     case 0:
0821         mode = LUT_BYPASS;
0822         break;
0823     case 1:
0824         mode = LUT_RAM_A;
0825         break;
0826     case 2:
0827         mode = LUT_RAM_B;
0828         break;
0829     default:
0830         mode = LUT_BYPASS;
0831         break;
0832     }
0833 
0834     return mode;
0835 }
0836 
0837 static void dpp3_configure_shaper_lut(
0838         struct dpp *dpp_base,
0839         bool is_ram_a)
0840 {
0841     struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
0842 
0843     REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK,
0844             CM_SHAPER_LUT_WRITE_EN_MASK, 7);
0845     REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK,
0846             CM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1);
0847     REG_SET(CM_SHAPER_LUT_INDEX, 0, CM_SHAPER_LUT_INDEX, 0);
0848 }
0849 
0850 /*program shaper RAM A*/
0851 
0852 static void dpp3_program_shaper_luta_settings(
0853         struct dpp *dpp_base,
0854         const struct pwl_params *params)
0855 {
0856     const struct gamma_curve *curve;
0857     struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
0858 
0859     REG_SET_2(CM_SHAPER_RAMA_START_CNTL_B, 0,
0860         CM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
0861         CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
0862     REG_SET_2(CM_SHAPER_RAMA_START_CNTL_G, 0,
0863         CM_SHAPER_RAMA_EXP_REGION_START_G, params->corner_points[0].green.custom_float_x,
0864         CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G, 0);
0865     REG_SET_2(CM_SHAPER_RAMA_START_CNTL_R, 0,
0866         CM_SHAPER_RAMA_EXP_REGION_START_R, params->corner_points[0].red.custom_float_x,
0867         CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R, 0);
0868 
0869     REG_SET_2(CM_SHAPER_RAMA_END_CNTL_B, 0,
0870         CM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
0871         CM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
0872 
0873     REG_SET_2(CM_SHAPER_RAMA_END_CNTL_G, 0,
0874         CM_SHAPER_RAMA_EXP_REGION_END_G, params->corner_points[1].green.custom_float_x,
0875         CM_SHAPER_RAMA_EXP_REGION_END_BASE_G, params->corner_points[1].green.custom_float_y);
0876 
0877     REG_SET_2(CM_SHAPER_RAMA_END_CNTL_R, 0,
0878         CM_SHAPER_RAMA_EXP_REGION_END_R, params->corner_points[1].red.custom_float_x,
0879         CM_SHAPER_RAMA_EXP_REGION_END_BASE_R, params->corner_points[1].red.custom_float_y);
0880 
0881     curve = params->arr_curve_points;
0882     REG_SET_4(CM_SHAPER_RAMA_REGION_0_1, 0,
0883         CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
0884         CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
0885         CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
0886         CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
0887 
0888     curve += 2;
0889     REG_SET_4(CM_SHAPER_RAMA_REGION_2_3, 0,
0890         CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET, curve[0].offset,
0891         CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num,
0892         CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET, curve[1].offset,
0893         CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num);
0894 
0895     curve += 2;
0896     REG_SET_4(CM_SHAPER_RAMA_REGION_4_5, 0,
0897         CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET, curve[0].offset,
0898         CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num,
0899         CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET, curve[1].offset,
0900         CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num);
0901 
0902     curve += 2;
0903     REG_SET_4(CM_SHAPER_RAMA_REGION_6_7, 0,
0904         CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET, curve[0].offset,
0905         CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num,
0906         CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET, curve[1].offset,
0907         CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num);
0908 
0909     curve += 2;
0910     REG_SET_4(CM_SHAPER_RAMA_REGION_8_9, 0,
0911         CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET, curve[0].offset,
0912         CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num,
0913         CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET, curve[1].offset,
0914         CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num);
0915 
0916     curve += 2;
0917     REG_SET_4(CM_SHAPER_RAMA_REGION_10_11, 0,
0918         CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET, curve[0].offset,
0919         CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num,
0920         CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET, curve[1].offset,
0921         CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num);
0922 
0923     curve += 2;
0924     REG_SET_4(CM_SHAPER_RAMA_REGION_12_13, 0,
0925         CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET, curve[0].offset,
0926         CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num,
0927         CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET, curve[1].offset,
0928         CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num);
0929 
0930     curve += 2;
0931     REG_SET_4(CM_SHAPER_RAMA_REGION_14_15, 0,
0932         CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET, curve[0].offset,
0933         CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num,
0934         CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET, curve[1].offset,
0935         CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);
0936 
0937     curve += 2;
0938     REG_SET_4(CM_SHAPER_RAMA_REGION_16_17, 0,
0939         CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET, curve[0].offset,
0940         CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num,
0941         CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET, curve[1].offset,
0942         CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num);
0943 
0944     curve += 2;
0945     REG_SET_4(CM_SHAPER_RAMA_REGION_18_19, 0,
0946         CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET, curve[0].offset,
0947         CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num,
0948         CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET, curve[1].offset,
0949         CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num);
0950 
0951     curve += 2;
0952     REG_SET_4(CM_SHAPER_RAMA_REGION_20_21, 0,
0953         CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET, curve[0].offset,
0954         CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num,
0955         CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET, curve[1].offset,
0956         CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num);
0957 
0958     curve += 2;
0959     REG_SET_4(CM_SHAPER_RAMA_REGION_22_23, 0,
0960         CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET, curve[0].offset,
0961         CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num,
0962         CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET, curve[1].offset,
0963         CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num);
0964 
0965     curve += 2;
0966     REG_SET_4(CM_SHAPER_RAMA_REGION_24_25, 0,
0967         CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET, curve[0].offset,
0968         CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num,
0969         CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET, curve[1].offset,
0970         CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num);
0971 
0972     curve += 2;
0973     REG_SET_4(CM_SHAPER_RAMA_REGION_26_27, 0,
0974         CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET, curve[0].offset,
0975         CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num,
0976         CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET, curve[1].offset,
0977         CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num);
0978 
0979     curve += 2;
0980     REG_SET_4(CM_SHAPER_RAMA_REGION_28_29, 0,
0981         CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET, curve[0].offset,
0982         CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num,
0983         CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET, curve[1].offset,
0984         CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num);
0985 
0986     curve += 2;
0987     REG_SET_4(CM_SHAPER_RAMA_REGION_30_31, 0,
0988         CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET, curve[0].offset,
0989         CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num,
0990         CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET, curve[1].offset,
0991         CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num);
0992 
0993     curve += 2;
0994     REG_SET_4(CM_SHAPER_RAMA_REGION_32_33, 0,
0995         CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET, curve[0].offset,
0996         CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num,
0997         CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET, curve[1].offset,
0998         CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num);
0999 }
1000 
1001 /*program shaper RAM B*/
1002 static void dpp3_program_shaper_lutb_settings(
1003         struct dpp *dpp_base,
1004         const struct pwl_params *params)
1005 {
1006     const struct gamma_curve *curve;
1007     struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1008 
1009     REG_SET_2(CM_SHAPER_RAMB_START_CNTL_B, 0,
1010         CM_SHAPER_RAMB_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
1011         CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B, 0);
1012     REG_SET_2(CM_SHAPER_RAMB_START_CNTL_G, 0,
1013         CM_SHAPER_RAMB_EXP_REGION_START_G, params->corner_points[0].green.custom_float_x,
1014         CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G, 0);
1015     REG_SET_2(CM_SHAPER_RAMB_START_CNTL_R, 0,
1016         CM_SHAPER_RAMB_EXP_REGION_START_R, params->corner_points[0].red.custom_float_x,
1017         CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R, 0);
1018 
1019     REG_SET_2(CM_SHAPER_RAMB_END_CNTL_B, 0,
1020         CM_SHAPER_RAMB_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
1021         CM_SHAPER_RAMB_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
1022 
1023     REG_SET_2(CM_SHAPER_RAMB_END_CNTL_G, 0,
1024         CM_SHAPER_RAMB_EXP_REGION_END_G, params->corner_points[1].green.custom_float_x,
1025         CM_SHAPER_RAMB_EXP_REGION_END_BASE_G, params->corner_points[1].green.custom_float_y);
1026 
1027     REG_SET_2(CM_SHAPER_RAMB_END_CNTL_R, 0,
1028         CM_SHAPER_RAMB_EXP_REGION_END_R, params->corner_points[1].red.custom_float_x,
1029         CM_SHAPER_RAMB_EXP_REGION_END_BASE_R, params->corner_points[1].red.custom_float_y);
1030 
1031     curve = params->arr_curve_points;
1032     REG_SET_4(CM_SHAPER_RAMB_REGION_0_1, 0,
1033         CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset,
1034         CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
1035         CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset,
1036         CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
1037 
1038     curve += 2;
1039     REG_SET_4(CM_SHAPER_RAMB_REGION_2_3, 0,
1040         CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET, curve[0].offset,
1041         CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num,
1042         CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET, curve[1].offset,
1043         CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num);
1044 
1045     curve += 2;
1046     REG_SET_4(CM_SHAPER_RAMB_REGION_4_5, 0,
1047         CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET, curve[0].offset,
1048         CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num,
1049         CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET, curve[1].offset,
1050         CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num);
1051 
1052     curve += 2;
1053     REG_SET_4(CM_SHAPER_RAMB_REGION_6_7, 0,
1054         CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET, curve[0].offset,
1055         CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num,
1056         CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET, curve[1].offset,
1057         CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num);
1058 
1059     curve += 2;
1060     REG_SET_4(CM_SHAPER_RAMB_REGION_8_9, 0,
1061         CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET, curve[0].offset,
1062         CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num,
1063         CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET, curve[1].offset,
1064         CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num);
1065 
1066     curve += 2;
1067     REG_SET_4(CM_SHAPER_RAMB_REGION_10_11, 0,
1068         CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET, curve[0].offset,
1069         CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num,
1070         CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET, curve[1].offset,
1071         CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num);
1072 
1073     curve += 2;
1074     REG_SET_4(CM_SHAPER_RAMB_REGION_12_13, 0,
1075         CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET, curve[0].offset,
1076         CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num,
1077         CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET, curve[1].offset,
1078         CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num);
1079 
1080     curve += 2;
1081     REG_SET_4(CM_SHAPER_RAMB_REGION_14_15, 0,
1082         CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET, curve[0].offset,
1083         CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num,
1084         CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET, curve[1].offset,
1085         CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);
1086 
1087     curve += 2;
1088     REG_SET_4(CM_SHAPER_RAMB_REGION_16_17, 0,
1089         CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET, curve[0].offset,
1090         CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num,
1091         CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET, curve[1].offset,
1092         CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num);
1093 
1094     curve += 2;
1095     REG_SET_4(CM_SHAPER_RAMB_REGION_18_19, 0,
1096         CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET, curve[0].offset,
1097         CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num,
1098         CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET, curve[1].offset,
1099         CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num);
1100 
1101     curve += 2;
1102     REG_SET_4(CM_SHAPER_RAMB_REGION_20_21, 0,
1103         CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET, curve[0].offset,
1104         CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num,
1105         CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET, curve[1].offset,
1106         CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num);
1107 
1108     curve += 2;
1109     REG_SET_4(CM_SHAPER_RAMB_REGION_22_23, 0,
1110         CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET, curve[0].offset,
1111         CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num,
1112         CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET, curve[1].offset,
1113         CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num);
1114 
1115     curve += 2;
1116     REG_SET_4(CM_SHAPER_RAMB_REGION_24_25, 0,
1117         CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET, curve[0].offset,
1118         CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num,
1119         CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET, curve[1].offset,
1120         CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num);
1121 
1122     curve += 2;
1123     REG_SET_4(CM_SHAPER_RAMB_REGION_26_27, 0,
1124         CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET, curve[0].offset,
1125         CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num,
1126         CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET, curve[1].offset,
1127         CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num);
1128 
1129     curve += 2;
1130     REG_SET_4(CM_SHAPER_RAMB_REGION_28_29, 0,
1131         CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET, curve[0].offset,
1132         CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num,
1133         CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET, curve[1].offset,
1134         CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num);
1135 
1136     curve += 2;
1137     REG_SET_4(CM_SHAPER_RAMB_REGION_30_31, 0,
1138         CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET, curve[0].offset,
1139         CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num,
1140         CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET, curve[1].offset,
1141         CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num);
1142 
1143     curve += 2;
1144     REG_SET_4(CM_SHAPER_RAMB_REGION_32_33, 0,
1145         CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET, curve[0].offset,
1146         CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num,
1147         CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET, curve[1].offset,
1148         CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num);
1149 
1150 }
1151 
1152 
1153 static bool dpp3_program_shaper(struct dpp *dpp_base,
1154                 const struct pwl_params *params)
1155 {
1156     enum dc_lut_mode current_mode;
1157     enum dc_lut_mode next_mode;
1158 
1159     struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1160 
1161     if (params == NULL) {
1162         REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, 0);
1163         if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
1164             dpp3_power_on_shaper(dpp_base, false);
1165         return false;
1166     }
1167 
1168     if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
1169         dpp3_power_on_shaper(dpp_base, true);
1170 
1171     current_mode = dpp3_get_shaper_current(dpp_base);
1172 
1173     if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
1174         next_mode = LUT_RAM_B;
1175     else
1176         next_mode = LUT_RAM_A;
1177 
1178     dpp3_configure_shaper_lut(dpp_base, next_mode == LUT_RAM_A);
1179 
1180     if (next_mode == LUT_RAM_A)
1181         dpp3_program_shaper_luta_settings(dpp_base, params);
1182     else
1183         dpp3_program_shaper_lutb_settings(dpp_base, params);
1184 
1185     dpp3_program_shaper_lut(
1186             dpp_base, params->rgb_resulted, params->hw_points_num);
1187 
1188     REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2);
1189 
1190     return true;
1191 
1192 }
1193 
1194 static enum dc_lut_mode get3dlut_config(
1195             struct dpp *dpp_base,
1196             bool *is_17x17x17,
1197             bool *is_12bits_color_channel)
1198 {
1199     uint32_t i_mode, i_enable_10bits, lut_size;
1200     enum dc_lut_mode mode;
1201     struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1202 
1203     REG_GET(CM_3DLUT_READ_WRITE_CONTROL,
1204             CM_3DLUT_30BIT_EN, &i_enable_10bits);
1205     REG_GET(CM_3DLUT_MODE,
1206             CM_3DLUT_MODE_CURRENT, &i_mode);
1207 
1208     switch (i_mode) {
1209     case 0:
1210         mode = LUT_BYPASS;
1211         break;
1212     case 1:
1213         mode = LUT_RAM_A;
1214         break;
1215     case 2:
1216         mode = LUT_RAM_B;
1217         break;
1218     default:
1219         mode = LUT_BYPASS;
1220         break;
1221     }
1222     if (i_enable_10bits > 0)
1223         *is_12bits_color_channel = false;
1224     else
1225         *is_12bits_color_channel = true;
1226 
1227     REG_GET(CM_3DLUT_MODE, CM_3DLUT_SIZE, &lut_size);
1228 
1229     if (lut_size == 0)
1230         *is_17x17x17 = true;
1231     else
1232         *is_17x17x17 = false;
1233 
1234     return mode;
1235 }
1236 /*
1237  * select ramA or ramB, or bypass
1238  * select color channel size 10 or 12 bits
1239  * select 3dlut size 17x17x17 or 9x9x9
1240  */
1241 static void dpp3_set_3dlut_mode(
1242         struct dpp *dpp_base,
1243         enum dc_lut_mode mode,
1244         bool is_color_channel_12bits,
1245         bool is_lut_size17x17x17)
1246 {
1247     uint32_t lut_mode;
1248     struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1249 
1250     if (mode == LUT_BYPASS)
1251         lut_mode = 0;
1252     else if (mode == LUT_RAM_A)
1253         lut_mode = 1;
1254     else
1255         lut_mode = 2;
1256 
1257     REG_UPDATE_2(CM_3DLUT_MODE,
1258             CM_3DLUT_MODE, lut_mode,
1259             CM_3DLUT_SIZE, is_lut_size17x17x17 == true ? 0 : 1);
1260 }
1261 
1262 static void dpp3_select_3dlut_ram(
1263         struct dpp *dpp_base,
1264         enum dc_lut_mode mode,
1265         bool is_color_channel_12bits)
1266 {
1267     struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1268 
1269     REG_UPDATE_2(CM_3DLUT_READ_WRITE_CONTROL,
1270             CM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1,
1271             CM_3DLUT_30BIT_EN,
1272             is_color_channel_12bits == true ? 0:1);
1273 }
1274 
1275 
1276 
1277 static void dpp3_set3dlut_ram12(
1278         struct dpp *dpp_base,
1279         const struct dc_rgb *lut,
1280         uint32_t entries)
1281 {
1282     uint32_t i, red, green, blue, red1, green1, blue1;
1283     struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1284 
1285     for (i = 0 ; i < entries; i += 2) {
1286         red   = lut[i].red<<4;
1287         green = lut[i].green<<4;
1288         blue  = lut[i].blue<<4;
1289         red1   = lut[i+1].red<<4;
1290         green1 = lut[i+1].green<<4;
1291         blue1  = lut[i+1].blue<<4;
1292 
1293         REG_SET_2(CM_3DLUT_DATA, 0,
1294                 CM_3DLUT_DATA0, red,
1295                 CM_3DLUT_DATA1, red1);
1296 
1297         REG_SET_2(CM_3DLUT_DATA, 0,
1298                 CM_3DLUT_DATA0, green,
1299                 CM_3DLUT_DATA1, green1);
1300 
1301         REG_SET_2(CM_3DLUT_DATA, 0,
1302                 CM_3DLUT_DATA0, blue,
1303                 CM_3DLUT_DATA1, blue1);
1304 
1305     }
1306 }
1307 
1308 /*
1309  * load selected lut with 10 bits color channels
1310  */
1311 static void dpp3_set3dlut_ram10(
1312         struct dpp *dpp_base,
1313         const struct dc_rgb *lut,
1314         uint32_t entries)
1315 {
1316     uint32_t i, red, green, blue, value;
1317     struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1318 
1319     for (i = 0; i < entries; i++) {
1320         red   = lut[i].red;
1321         green = lut[i].green;
1322         blue  = lut[i].blue;
1323 
1324         value = (red<<20) | (green<<10) | blue;
1325 
1326         REG_SET(CM_3DLUT_DATA_30BIT, 0, CM_3DLUT_DATA_30BIT, value);
1327     }
1328 
1329 }
1330 
1331 
1332 static void dpp3_select_3dlut_ram_mask(
1333         struct dpp *dpp_base,
1334         uint32_t ram_selection_mask)
1335 {
1336     struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1337 
1338     REG_UPDATE(CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_WRITE_EN_MASK,
1339             ram_selection_mask);
1340     REG_SET(CM_3DLUT_INDEX, 0, CM_3DLUT_INDEX, 0);
1341 }
1342 
1343 static bool dpp3_program_3dlut(struct dpp *dpp_base,
1344                    struct tetrahedral_params *params)
1345 {
1346     enum dc_lut_mode mode;
1347     bool is_17x17x17;
1348     bool is_12bits_color_channel;
1349     struct dc_rgb *lut0;
1350     struct dc_rgb *lut1;
1351     struct dc_rgb *lut2;
1352     struct dc_rgb *lut3;
1353     int lut_size0;
1354     int lut_size;
1355 
1356     if (params == NULL) {
1357         dpp3_set_3dlut_mode(dpp_base, LUT_BYPASS, false, false);
1358         if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
1359             dpp3_power_on_hdr3dlut(dpp_base, false);
1360         return false;
1361     }
1362 
1363     if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
1364         dpp3_power_on_hdr3dlut(dpp_base, true);
1365 
1366     mode = get3dlut_config(dpp_base, &is_17x17x17, &is_12bits_color_channel);
1367 
1368     if (mode == LUT_BYPASS || mode == LUT_RAM_B)
1369         mode = LUT_RAM_A;
1370     else
1371         mode = LUT_RAM_B;
1372 
1373     is_17x17x17 = !params->use_tetrahedral_9;
1374     is_12bits_color_channel = params->use_12bits;
1375     if (is_17x17x17) {
1376         lut0 = params->tetrahedral_17.lut0;
1377         lut1 = params->tetrahedral_17.lut1;
1378         lut2 = params->tetrahedral_17.lut2;
1379         lut3 = params->tetrahedral_17.lut3;
1380         lut_size0 = sizeof(params->tetrahedral_17.lut0)/
1381                     sizeof(params->tetrahedral_17.lut0[0]);
1382         lut_size  = sizeof(params->tetrahedral_17.lut1)/
1383                     sizeof(params->tetrahedral_17.lut1[0]);
1384     } else {
1385         lut0 = params->tetrahedral_9.lut0;
1386         lut1 = params->tetrahedral_9.lut1;
1387         lut2 = params->tetrahedral_9.lut2;
1388         lut3 = params->tetrahedral_9.lut3;
1389         lut_size0 = sizeof(params->tetrahedral_9.lut0)/
1390                 sizeof(params->tetrahedral_9.lut0[0]);
1391         lut_size  = sizeof(params->tetrahedral_9.lut1)/
1392                 sizeof(params->tetrahedral_9.lut1[0]);
1393         }
1394 
1395     dpp3_select_3dlut_ram(dpp_base, mode,
1396                 is_12bits_color_channel);
1397     dpp3_select_3dlut_ram_mask(dpp_base, 0x1);
1398     if (is_12bits_color_channel)
1399         dpp3_set3dlut_ram12(dpp_base, lut0, lut_size0);
1400     else
1401         dpp3_set3dlut_ram10(dpp_base, lut0, lut_size0);
1402 
1403     dpp3_select_3dlut_ram_mask(dpp_base, 0x2);
1404     if (is_12bits_color_channel)
1405         dpp3_set3dlut_ram12(dpp_base, lut1, lut_size);
1406     else
1407         dpp3_set3dlut_ram10(dpp_base, lut1, lut_size);
1408 
1409     dpp3_select_3dlut_ram_mask(dpp_base, 0x4);
1410     if (is_12bits_color_channel)
1411         dpp3_set3dlut_ram12(dpp_base, lut2, lut_size);
1412     else
1413         dpp3_set3dlut_ram10(dpp_base, lut2, lut_size);
1414 
1415     dpp3_select_3dlut_ram_mask(dpp_base, 0x8);
1416     if (is_12bits_color_channel)
1417         dpp3_set3dlut_ram12(dpp_base, lut3, lut_size);
1418     else
1419         dpp3_set3dlut_ram10(dpp_base, lut3, lut_size);
1420 
1421 
1422     dpp3_set_3dlut_mode(dpp_base, mode, is_12bits_color_channel,
1423                     is_17x17x17);
1424 
1425     return true;
1426 }
1427 static struct dpp_funcs dcn30_dpp_funcs = {
1428     .dpp_program_gamcor_lut = dpp3_program_gamcor_lut,
1429     .dpp_read_state         = dpp30_read_state,
1430     .dpp_reset          = dpp_reset,
1431     .dpp_set_scaler         = dpp1_dscl_set_scaler_manual_scale,
1432     .dpp_get_optimal_number_of_taps = dpp3_get_optimal_number_of_taps,
1433     .dpp_set_gamut_remap        = dpp3_cm_set_gamut_remap,
1434     .dpp_set_csc_adjustment     = NULL,
1435     .dpp_set_csc_default        = NULL,
1436     .dpp_program_regamma_pwl    = NULL,
1437     .dpp_set_pre_degam      = dpp3_set_pre_degam,
1438     .dpp_program_input_lut      = NULL,
1439     .dpp_full_bypass        = dpp1_full_bypass,
1440     .dpp_setup          = dpp3_cnv_setup,
1441     .dpp_program_degamma_pwl    = NULL,
1442     .dpp_program_cm_dealpha = dpp3_program_cm_dealpha,
1443     .dpp_program_cm_bias = dpp3_program_cm_bias,
1444     .dpp_program_blnd_lut = dpp3_program_blnd_lut,
1445     .dpp_program_shaper_lut = dpp3_program_shaper,
1446     .dpp_program_3dlut = dpp3_program_3dlut,
1447     .dpp_deferred_update = dpp3_deferred_update,
1448     .dpp_program_bias_and_scale = NULL,
1449     .dpp_cnv_set_alpha_keyer    = dpp2_cnv_set_alpha_keyer,
1450     .set_cursor_attributes      = dpp3_set_cursor_attributes,
1451     .set_cursor_position        = dpp1_set_cursor_position,
1452     .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes,
1453     .dpp_dppclk_control     = dpp1_dppclk_control,
1454     .dpp_set_hdr_multiplier     = dpp3_set_hdr_multiplier,
1455 };
1456 
1457 
1458 static struct dpp_caps dcn30_dpp_cap = {
1459     .dscl_data_proc_format = DSCL_DATA_PRCESSING_FLOAT_FORMAT,
1460     .dscl_calc_lb_num_partitions = dscl2_calc_lb_num_partitions,
1461 };
1462 
1463 bool dpp3_construct(
1464     struct dcn3_dpp *dpp,
1465     struct dc_context *ctx,
1466     uint32_t inst,
1467     const struct dcn3_dpp_registers *tf_regs,
1468     const struct dcn3_dpp_shift *tf_shift,
1469     const struct dcn3_dpp_mask *tf_mask)
1470 {
1471     dpp->base.ctx = ctx;
1472 
1473     dpp->base.inst = inst;
1474     dpp->base.funcs = &dcn30_dpp_funcs;
1475     dpp->base.caps = &dcn30_dpp_cap;
1476 
1477     dpp->tf_regs = tf_regs;
1478     dpp->tf_shift = tf_shift;
1479     dpp->tf_mask = tf_mask;
1480 
1481     return true;
1482 }
1483
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