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0001 /*
0002  * Copyright 2020 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  *  and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 
0026 
0027 #include "dc_bios_types.h"
0028 #include "dcn30_dio_stream_encoder.h"
0029 #include "reg_helper.h"
0030 #include "hw_shared.h"
0031 #include "core_types.h"
0032 #include <linux/delay.h>
0033 
0034 
0035 #define DC_LOGGER \
0036         enc1->base.ctx->logger
0037 
0038 #define REG(reg)\
0039     (enc1->regs->reg)
0040 
0041 #undef FN
0042 #define FN(reg_name, field_name) \
0043     enc1->se_shift->field_name, enc1->se_mask->field_name
0044 
0045 #define VBI_LINE_0 0
0046 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
0047 
0048 #define CTX \
0049     enc1->base.ctx
0050 
0051 
0052 static void enc3_update_hdmi_info_packet(
0053     struct dcn10_stream_encoder *enc1,
0054     uint32_t packet_index,
0055     const struct dc_info_packet *info_packet)
0056 {
0057     uint32_t cont, send, line;
0058 
0059     if (info_packet->valid) {
0060         enc1->base.vpg->funcs->update_generic_info_packet(
0061                 enc1->base.vpg,
0062                 packet_index,
0063                 info_packet,
0064                 true);
0065 
0066         /* enable transmission of packet(s) -
0067          * packet transmission begins on the next frame */
0068         cont = 1;
0069         /* send packet(s) every frame */
0070         send = 1;
0071         /* select line number to send packets on */
0072         line = 2;
0073     } else {
0074         cont = 0;
0075         send = 0;
0076         line = 0;
0077     }
0078 
0079     /* DP_SEC_GSP[x]_LINE_REFERENCE - keep default value REFER_TO_DP_SOF */
0080 
0081     /* choose which generic packet control to use */
0082     switch (packet_index) {
0083     case 0:
0084         REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
0085                 HDMI_GENERIC0_CONT, cont,
0086                 HDMI_GENERIC0_SEND, send);
0087         REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1,
0088                 HDMI_GENERIC0_LINE, line);
0089         break;
0090     case 1:
0091         REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
0092                 HDMI_GENERIC1_CONT, cont,
0093                 HDMI_GENERIC1_SEND, send);
0094         REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1,
0095                 HDMI_GENERIC1_LINE, line);
0096         break;
0097     case 2:
0098         REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
0099                 HDMI_GENERIC2_CONT, cont,
0100                 HDMI_GENERIC2_SEND, send);
0101         REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2,
0102                 HDMI_GENERIC2_LINE, line);
0103         break;
0104     case 3:
0105         REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
0106                 HDMI_GENERIC3_CONT, cont,
0107                 HDMI_GENERIC3_SEND, send);
0108         REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2,
0109                 HDMI_GENERIC3_LINE, line);
0110         break;
0111     case 4:
0112         REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
0113                 HDMI_GENERIC4_CONT, cont,
0114                 HDMI_GENERIC4_SEND, send);
0115         REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3,
0116                 HDMI_GENERIC4_LINE, line);
0117         break;
0118     case 5:
0119         REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
0120                 HDMI_GENERIC5_CONT, cont,
0121                 HDMI_GENERIC5_SEND, send);
0122         REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3,
0123                 HDMI_GENERIC5_LINE, line);
0124         break;
0125     case 6:
0126         REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
0127                 HDMI_GENERIC6_CONT, cont,
0128                 HDMI_GENERIC6_SEND, send);
0129         REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4,
0130                 HDMI_GENERIC6_LINE, line);
0131         break;
0132     case 7:
0133         REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
0134                 HDMI_GENERIC7_CONT, cont,
0135                 HDMI_GENERIC7_SEND, send);
0136         REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4,
0137                 HDMI_GENERIC7_LINE, line);
0138         break;
0139     case 8:
0140         REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
0141                 HDMI_GENERIC8_CONT, cont,
0142                 HDMI_GENERIC8_SEND, send);
0143         REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL7,
0144                 HDMI_GENERIC8_LINE, line);
0145         break;
0146     case 9:
0147         REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
0148                 HDMI_GENERIC9_CONT, cont,
0149                 HDMI_GENERIC9_SEND, send);
0150         REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL7,
0151                 HDMI_GENERIC9_LINE, line);
0152         break;
0153     case 10:
0154         REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
0155                 HDMI_GENERIC10_CONT, cont,
0156                 HDMI_GENERIC10_SEND, send);
0157         REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL8,
0158                 HDMI_GENERIC10_LINE, line);
0159         break;
0160     case 11:
0161         REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
0162                 HDMI_GENERIC11_CONT, cont,
0163                 HDMI_GENERIC11_SEND, send);
0164         REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL8,
0165                 HDMI_GENERIC11_LINE, line);
0166         break;
0167     case 12:
0168         REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
0169                 HDMI_GENERIC12_CONT, cont,
0170                 HDMI_GENERIC12_SEND, send);
0171         REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL9,
0172                 HDMI_GENERIC12_LINE, line);
0173         break;
0174     case 13:
0175         REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
0176                 HDMI_GENERIC13_CONT, cont,
0177                 HDMI_GENERIC13_SEND, send);
0178         REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL9,
0179                 HDMI_GENERIC13_LINE, line);
0180         break;
0181     case 14:
0182         REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
0183                 HDMI_GENERIC14_CONT, cont,
0184                 HDMI_GENERIC14_SEND, send);
0185         REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL10,
0186                 HDMI_GENERIC14_LINE, line);
0187         break;
0188     default:
0189         /* invalid HW packet index */
0190         DC_LOG_WARNING(
0191             "Invalid HW packet index: %s()\n",
0192             __func__);
0193         return;
0194     }
0195 }
0196 
0197 void enc3_stream_encoder_update_hdmi_info_packets(
0198     struct stream_encoder *enc,
0199     const struct encoder_info_frame *info_frame)
0200 {
0201     struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
0202 
0203     /* for bring up, disable dp double  TODO */
0204     REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
0205     REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
0206 
0207     /*Always add mandatory packets first followed by optional ones*/
0208     enc3_update_hdmi_info_packet(enc1, 0, &info_frame->avi);
0209     enc3_update_hdmi_info_packet(enc1, 5, &info_frame->hfvsif);
0210     enc3_update_hdmi_info_packet(enc1, 2, &info_frame->gamut);
0211     enc3_update_hdmi_info_packet(enc1, 1, &info_frame->vendor);
0212     enc3_update_hdmi_info_packet(enc1, 3, &info_frame->spd);
0213     enc3_update_hdmi_info_packet(enc1, 4, &info_frame->hdrsmd);
0214     enc3_update_hdmi_info_packet(enc1, 6, &info_frame->vtem);
0215 }
0216 
0217 void enc3_stream_encoder_stop_hdmi_info_packets(
0218     struct stream_encoder *enc)
0219 {
0220     struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
0221 
0222     /* stop generic packets 0,1 on HDMI */
0223     REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,
0224         HDMI_GENERIC0_CONT, 0,
0225         HDMI_GENERIC0_SEND, 0,
0226         HDMI_GENERIC1_CONT, 0,
0227         HDMI_GENERIC1_SEND, 0);
0228     REG_SET_2(HDMI_GENERIC_PACKET_CONTROL1, 0,
0229         HDMI_GENERIC0_LINE, 0,
0230         HDMI_GENERIC1_LINE, 0);
0231 
0232     /* stop generic packets 2,3 on HDMI */
0233     REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,
0234         HDMI_GENERIC2_CONT, 0,
0235         HDMI_GENERIC2_SEND, 0,
0236         HDMI_GENERIC3_CONT, 0,
0237         HDMI_GENERIC3_SEND, 0);
0238     REG_SET_2(HDMI_GENERIC_PACKET_CONTROL2, 0,
0239         HDMI_GENERIC2_LINE, 0,
0240         HDMI_GENERIC3_LINE, 0);
0241 
0242     /* stop generic packets 4,5 on HDMI */
0243     REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,
0244         HDMI_GENERIC4_CONT, 0,
0245         HDMI_GENERIC4_SEND, 0,
0246         HDMI_GENERIC5_CONT, 0,
0247         HDMI_GENERIC5_SEND, 0);
0248     REG_SET_2(HDMI_GENERIC_PACKET_CONTROL3, 0,
0249         HDMI_GENERIC4_LINE, 0,
0250         HDMI_GENERIC5_LINE, 0);
0251 
0252     /* stop generic packets 6,7 on HDMI */
0253     REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,
0254         HDMI_GENERIC6_CONT, 0,
0255         HDMI_GENERIC6_SEND, 0,
0256         HDMI_GENERIC7_CONT, 0,
0257         HDMI_GENERIC7_SEND, 0);
0258     REG_SET_2(HDMI_GENERIC_PACKET_CONTROL4, 0,
0259         HDMI_GENERIC6_LINE, 0,
0260         HDMI_GENERIC7_LINE, 0);
0261 
0262     /* stop generic packets 8,9 on HDMI */
0263     REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0,
0264         HDMI_GENERIC8_CONT, 0,
0265         HDMI_GENERIC8_SEND, 0,
0266         HDMI_GENERIC9_CONT, 0,
0267         HDMI_GENERIC9_SEND, 0);
0268     REG_SET_2(HDMI_GENERIC_PACKET_CONTROL7, 0,
0269         HDMI_GENERIC8_LINE, 0,
0270         HDMI_GENERIC9_LINE, 0);
0271 
0272     /* stop generic packets 10,11 on HDMI */
0273     REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0,
0274         HDMI_GENERIC10_CONT, 0,
0275         HDMI_GENERIC10_SEND, 0,
0276         HDMI_GENERIC11_CONT, 0,
0277         HDMI_GENERIC11_SEND, 0);
0278     REG_SET_2(HDMI_GENERIC_PACKET_CONTROL8, 0,
0279         HDMI_GENERIC10_LINE, 0,
0280         HDMI_GENERIC11_LINE, 0);
0281 
0282     /* stop generic packets 12,13 on HDMI */
0283     REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0,
0284         HDMI_GENERIC12_CONT, 0,
0285         HDMI_GENERIC12_SEND, 0,
0286         HDMI_GENERIC13_CONT, 0,
0287         HDMI_GENERIC13_SEND, 0);
0288     REG_SET_2(HDMI_GENERIC_PACKET_CONTROL9, 0,
0289         HDMI_GENERIC12_LINE, 0,
0290         HDMI_GENERIC13_LINE, 0);
0291 
0292     /* stop generic packet 14 on HDMI */
0293     REG_SET_2(HDMI_GENERIC_PACKET_CONTROL6, 0,
0294         HDMI_GENERIC14_CONT, 0,
0295         HDMI_GENERIC14_SEND, 0);
0296     REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL10,
0297         HDMI_GENERIC14_LINE, 0);
0298 }
0299 
0300 /* Set DSC-related configuration.
0301  *   dsc_mode: 0 disables DSC, other values enable DSC in specified format
0302  *   sc_bytes_per_pixel: Bytes per pixel in u3.28 format
0303  *   dsc_slice_width: Slice width in pixels
0304  */
0305 static void enc3_dp_set_dsc_config(struct stream_encoder *enc,
0306                     enum optc_dsc_mode dsc_mode,
0307                     uint32_t dsc_bytes_per_pixel,
0308                     uint32_t dsc_slice_width)
0309 {
0310     struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
0311 
0312     REG_UPDATE_2(DP_DSC_CNTL,
0313             DP_DSC_MODE, dsc_mode,
0314             DP_DSC_SLICE_WIDTH, dsc_slice_width);
0315 
0316     REG_SET(DP_DSC_BYTES_PER_PIXEL, 0,
0317         DP_DSC_BYTES_PER_PIXEL, dsc_bytes_per_pixel);
0318 }
0319 
0320 
0321 void enc3_dp_set_dsc_pps_info_packet(struct stream_encoder *enc,
0322                     bool enable,
0323                     uint8_t *dsc_packed_pps,
0324                     bool immediate_update)
0325 {
0326     struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
0327 
0328     if (enable) {
0329         struct dc_info_packet pps_sdp;
0330         int i;
0331 
0332         /* Configure for PPS packet size (128 bytes) */
0333         REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP11_PPS, 1);
0334 
0335         /* We need turn on clock before programming AFMT block
0336          *
0337          * TODO: We may not need this here anymore since update_generic_info_packet
0338          * no longer touches AFMT
0339          */
0340         REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
0341 
0342         /* Load PPS into infoframe (SDP) registers */
0343         pps_sdp.valid = true;
0344         pps_sdp.hb0 = 0;
0345         pps_sdp.hb1 = DC_DP_INFOFRAME_TYPE_PPS;
0346         pps_sdp.hb2 = 127;
0347         pps_sdp.hb3 = 0;
0348 
0349         for (i = 0; i < 4; i++) {
0350             memcpy(pps_sdp.sb, &dsc_packed_pps[i * 32], 32);
0351             enc1->base.vpg->funcs->update_generic_info_packet(
0352                             enc1->base.vpg,
0353                             11 + i,
0354                             &pps_sdp,
0355                             immediate_update);
0356         }
0357 
0358         /* SW should make sure VBID[6] update line number is bigger
0359          * than PPS transmit line number
0360          */
0361         REG_UPDATE(DP_GSP11_CNTL,
0362                 DP_SEC_GSP11_LINE_NUM, 2);
0363         REG_UPDATE_2(DP_MSA_VBID_MISC,
0364                 DP_VBID6_LINE_REFERENCE, 0,
0365                 DP_VBID6_LINE_NUM, 3);
0366 
0367         /* Send PPS data at the line number specified above.
0368          * DP spec requires PPS to be sent only when it changes, however since
0369          * decoder has to be able to handle its change on every frame, we're
0370          * sending it always (i.e. on every frame) to reduce the chance it'd be
0371          * missed by decoder. If it turns out required to send PPS only when it
0372          * changes, we can use DP_SEC_GSP11_SEND register.
0373          */
0374         REG_UPDATE(DP_GSP11_CNTL,
0375             DP_SEC_GSP11_ENABLE, 1);
0376         REG_UPDATE(DP_SEC_CNTL,
0377             DP_SEC_STREAM_ENABLE, 1);
0378     } else {
0379         /* Disable Generic Stream Packet 11 (GSP) transmission */
0380         REG_UPDATE(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, 0);
0381         REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP11_PPS, 0);
0382     }
0383 }
0384 
0385 
0386 /* this function read dsc related register fields to be logged later in dcn10_log_hw_state
0387  * into a dcn_dsc_state struct.
0388  */
0389 static void enc3_read_state(struct stream_encoder *enc, struct enc_state *s)
0390 {
0391     struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
0392 
0393     //if dsc is enabled, continue to read
0394     REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode);
0395     if (s->dsc_mode) {
0396         REG_GET(DP_DSC_CNTL, DP_DSC_SLICE_WIDTH, &s->dsc_slice_width);
0397         REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_LINE_NUM, &s->sec_gsp_pps_line_num);
0398 
0399         REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference);
0400         REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num);
0401 
0402         REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, &s->sec_gsp_pps_enable);
0403         REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable);
0404     }
0405 }
0406 
0407 void enc3_stream_encoder_update_dp_info_packets(
0408     struct stream_encoder *enc,
0409     const struct encoder_info_frame *info_frame)
0410 {
0411     struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
0412     uint32_t value = 0;
0413     uint32_t dmdata_packet_enabled = 0;
0414 
0415     if (info_frame->vsc.valid) {
0416         enc->vpg->funcs->update_generic_info_packet(
0417                 enc->vpg,
0418                 0,  /* packetIndex */
0419                 &info_frame->vsc,
0420                 true);
0421     }
0422     /* TODO: VSC SDP at packetIndex 1 should be restricted only if PSR-SU on.
0423      * There should have another Infopacket type (e.g. vsc_psrsu) for PSR_SU.
0424      * In addition, currently the driver check the valid bit then update and
0425      * send the corresponding Infopacket. For PSR-SU, the SDP only be sent
0426      * while entering PSR-SU mode. So we need another parameter(e.g. send)
0427      * in dc_info_packet to indicate which infopacket should be enabled by
0428      * default here.
0429      */
0430     if (info_frame->vsc.valid) {
0431         enc->vpg->funcs->update_generic_info_packet(
0432                 enc->vpg,
0433                 1,  /* packetIndex */
0434                 &info_frame->vsc,
0435                 true);
0436     }
0437     if (info_frame->spd.valid) {
0438         enc->vpg->funcs->update_generic_info_packet(
0439                 enc->vpg,
0440                 2,  /* packetIndex */
0441                 &info_frame->spd,
0442                 true);
0443     }
0444     if (info_frame->hdrsmd.valid) {
0445         enc->vpg->funcs->update_generic_info_packet(
0446                 enc->vpg,
0447                 3,  /* packetIndex */
0448                 &info_frame->hdrsmd,
0449                 true);
0450     }
0451     /* packetIndex 4 is used for send immediate sdp message, and please
0452      * use other packetIndex (such as 5,6) for other info packet
0453      */
0454 
0455     /* enable/disable transmission of packet(s).
0456      * If enabled, packet transmission begins on the next frame
0457      */
0458     REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
0459     REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
0460     REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
0461 
0462     /* This bit is the master enable bit.
0463      * When enabling secondary stream engine,
0464      * this master bit must also be set.
0465      * This register shared with audio info frame.
0466      * Therefore we need to enable master bit
0467      * if at least on of the fields is not 0
0468      */
0469     value = REG_READ(DP_SEC_CNTL);
0470     if (value)
0471         REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
0472 
0473     /* check if dynamic metadata packet transmission is enabled */
0474     REG_GET(DP_SEC_METADATA_TRANSMISSION,
0475             DP_SEC_METADATA_PACKET_ENABLE, &dmdata_packet_enabled);
0476 
0477     if (dmdata_packet_enabled)
0478         REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
0479 }
0480 
0481 static void enc3_dp_set_odm_combine(
0482     struct stream_encoder *enc,
0483     bool odm_combine)
0484 {
0485     struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
0486 
0487     REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_COMBINE, odm_combine);
0488 }
0489 
0490 /* setup stream encoder in dvi mode */
0491 static void enc3_stream_encoder_dvi_set_stream_attribute(
0492     struct stream_encoder *enc,
0493     struct dc_crtc_timing *crtc_timing,
0494     bool is_dual_link)
0495 {
0496     struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
0497 
0498     if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
0499         struct bp_encoder_control cntl = {0};
0500 
0501         cntl.action = ENCODER_CONTROL_SETUP;
0502         cntl.engine_id = enc1->base.id;
0503         cntl.signal = is_dual_link ?
0504             SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
0505         cntl.enable_dp_audio = false;
0506         cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
0507         cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
0508 
0509         if (enc1->base.bp->funcs->encoder_control(
0510                 enc1->base.bp, &cntl) != BP_RESULT_OK)
0511             return;
0512 
0513     } else {
0514 
0515         //Set pattern for clock channel, default vlue 0x63 does not work
0516         REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);
0517 
0518         //DIG_BE_TMDS_DVI_MODE : TMDS-DVI mode is already set in link_encoder_setup
0519 
0520         //DIG_SOURCE_SELECT is already set in dig_connect_to_otg
0521 
0522         /* set DIG_START to 0x1 to reset FIFO */
0523         REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
0524         udelay(1);
0525 
0526         /* write 0 to take the FIFO out of reset */
0527         REG_UPDATE(DIG_FE_CNTL, DIG_START, 0);
0528         udelay(1);
0529     }
0530 
0531     ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
0532     ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
0533     enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
0534 }
0535 
0536 /* setup stream encoder in hdmi mode */
0537 static void enc3_stream_encoder_hdmi_set_stream_attribute(
0538     struct stream_encoder *enc,
0539     struct dc_crtc_timing *crtc_timing,
0540     int actual_pix_clk_khz,
0541     bool enable_audio)
0542 {
0543     struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
0544 
0545     if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
0546         struct bp_encoder_control cntl = {0};
0547 
0548         cntl.action = ENCODER_CONTROL_SETUP;
0549         cntl.engine_id = enc1->base.id;
0550         cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
0551         cntl.enable_dp_audio = enable_audio;
0552         cntl.pixel_clock = actual_pix_clk_khz;
0553         cntl.lanes_number = LANE_COUNT_FOUR;
0554 
0555         if (enc1->base.bp->funcs->encoder_control(
0556                 enc1->base.bp, &cntl) != BP_RESULT_OK)
0557             return;
0558 
0559     } else {
0560 
0561         //Set pattern for clock channel, default vlue 0x63 does not work
0562         REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);
0563 
0564         //DIG_BE_TMDS_HDMI_MODE : TMDS-HDMI mode is already set in link_encoder_setup
0565 
0566         //DIG_SOURCE_SELECT is already set in dig_connect_to_otg
0567 
0568         /* set DIG_START to 0x1 to reset FIFO */
0569         REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
0570         udelay(1);
0571 
0572         /* write 0 to take the FIFO out of reset */
0573         REG_UPDATE(DIG_FE_CNTL, DIG_START, 0);
0574         udelay(1);
0575     }
0576 
0577     /* Configure pixel encoding */
0578     enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
0579 
0580     /* setup HDMI engine */
0581     REG_UPDATE_6(HDMI_CONTROL,
0582         HDMI_PACKET_GEN_VERSION, 1,
0583         HDMI_KEEPOUT_MODE, 1,
0584         HDMI_DEEP_COLOR_ENABLE, 0,
0585         HDMI_DATA_SCRAMBLE_EN, 0,
0586         HDMI_NO_EXTRA_NULL_PACKET_FILLED, 1,
0587         HDMI_CLOCK_CHANNEL_RATE, 0);
0588 
0589     /* Configure color depth */
0590     switch (crtc_timing->display_color_depth) {
0591     case COLOR_DEPTH_888:
0592         REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
0593         break;
0594     case COLOR_DEPTH_101010:
0595         if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
0596             REG_UPDATE_2(HDMI_CONTROL,
0597                     HDMI_DEEP_COLOR_DEPTH, 1,
0598                     HDMI_DEEP_COLOR_ENABLE, 0);
0599         } else {
0600             REG_UPDATE_2(HDMI_CONTROL,
0601                     HDMI_DEEP_COLOR_DEPTH, 1,
0602                     HDMI_DEEP_COLOR_ENABLE, 1);
0603             }
0604         break;
0605     case COLOR_DEPTH_121212:
0606         if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
0607             REG_UPDATE_2(HDMI_CONTROL,
0608                     HDMI_DEEP_COLOR_DEPTH, 2,
0609                     HDMI_DEEP_COLOR_ENABLE, 0);
0610         } else {
0611             REG_UPDATE_2(HDMI_CONTROL,
0612                     HDMI_DEEP_COLOR_DEPTH, 2,
0613                     HDMI_DEEP_COLOR_ENABLE, 1);
0614             }
0615         break;
0616     case COLOR_DEPTH_161616:
0617         REG_UPDATE_2(HDMI_CONTROL,
0618                 HDMI_DEEP_COLOR_DEPTH, 3,
0619                 HDMI_DEEP_COLOR_ENABLE, 1);
0620         break;
0621     default:
0622         break;
0623     }
0624 
0625     if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
0626         /* enable HDMI data scrambler
0627          * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
0628          * Clock channel frequency is 1/4 of character rate.
0629          */
0630         REG_UPDATE_2(HDMI_CONTROL,
0631             HDMI_DATA_SCRAMBLE_EN, 1,
0632             HDMI_CLOCK_CHANNEL_RATE, 1);
0633     } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
0634 
0635         /* TODO: New feature for DCE11, still need to implement */
0636 
0637         /* enable HDMI data scrambler
0638          * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
0639          * Clock channel frequency is the same
0640          * as character rate
0641          */
0642         REG_UPDATE_2(HDMI_CONTROL,
0643             HDMI_DATA_SCRAMBLE_EN, 1,
0644             HDMI_CLOCK_CHANNEL_RATE, 0);
0645     }
0646 
0647 
0648     /* Enable transmission of General Control packet on every frame */
0649     REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
0650         HDMI_GC_CONT, 1,
0651         HDMI_GC_SEND, 1,
0652         HDMI_NULL_SEND, 1);
0653 
0654     /* Disable Audio Content Protection packet transmission */
0655     REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0);
0656 
0657     /* following belongs to audio */
0658     /* Enable Audio InfoFrame packet transmission. */
0659     REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
0660 
0661     /* update double-buffered AUDIO_INFO registers immediately */
0662     ASSERT (enc->afmt);
0663     enc->afmt->funcs->audio_info_immediate_update(enc->afmt);
0664 
0665     /* Select line number on which to send Audio InfoFrame packets */
0666     REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
0667                 VBI_LINE_0 + 2);
0668 
0669     /* set HDMI GC AVMUTE */
0670     REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
0671 }
0672 
0673 void enc3_audio_mute_control(
0674     struct stream_encoder *enc,
0675     bool mute)
0676 {
0677     ASSERT (enc->afmt);
0678     enc->afmt->funcs->audio_mute_control(enc->afmt, mute);
0679 }
0680 
0681 void enc3_se_dp_audio_setup(
0682     struct stream_encoder *enc,
0683     unsigned int az_inst,
0684     struct audio_info *info)
0685 {
0686     ASSERT (enc->afmt);
0687     enc->afmt->funcs->se_audio_setup(enc->afmt, az_inst, info);
0688 }
0689 
0690 #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
0691 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
0692 
0693 static void enc3_se_setup_dp_audio(
0694     struct stream_encoder *enc)
0695 {
0696     struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
0697 
0698     /* --- DP Audio packet configurations --- */
0699 
0700     /* ATP Configuration */
0701     REG_SET(DP_SEC_AUD_N, 0,
0702             DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT);
0703 
0704     /* Async/auto-calc timestamp mode */
0705     REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
0706             DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC);
0707 
0708     ASSERT (enc->afmt);
0709     enc->afmt->funcs->setup_dp_audio(enc->afmt);
0710 }
0711 
0712 void enc3_se_dp_audio_enable(
0713     struct stream_encoder *enc)
0714 {
0715     enc1_se_enable_audio_clock(enc, true);
0716     enc3_se_setup_dp_audio(enc);
0717     enc1_se_enable_dp_audio(enc);
0718 }
0719 
0720 static void enc3_se_setup_hdmi_audio(
0721     struct stream_encoder *enc,
0722     const struct audio_crtc_info *crtc_info)
0723 {
0724     struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
0725 
0726     struct audio_clock_info audio_clock_info = {0};
0727 
0728     /* Setup audio in AFMT - program AFMT block associated with DIO */
0729     ASSERT (enc->afmt);
0730     enc->afmt->funcs->setup_hdmi_audio(enc->afmt);
0731 
0732     /* HDMI_AUDIO_PACKET_CONTROL */
0733     REG_UPDATE(HDMI_AUDIO_PACKET_CONTROL,
0734             HDMI_AUDIO_DELAY_EN, 1);
0735 
0736     /* HDMI_ACR_PACKET_CONTROL */
0737     REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
0738             HDMI_ACR_AUTO_SEND, 1,
0739             HDMI_ACR_SOURCE, 0,
0740             HDMI_ACR_AUDIO_PRIORITY, 0);
0741 
0742     /* Program audio clock sample/regeneration parameters */
0743     get_audio_clock_info(crtc_info->color_depth,
0744                  crtc_info->requested_pixel_clock_100Hz,
0745                  crtc_info->calculated_pixel_clock_100Hz,
0746                  &audio_clock_info);
0747     DC_LOG_HW_AUDIO(
0748             "\n%s:Input::requested_pixel_clock_100Hz = %d"  \
0749             "calculated_pixel_clock_100Hz = %d \n", __func__,   \
0750             crtc_info->requested_pixel_clock_100Hz,     \
0751             crtc_info->calculated_pixel_clock_100Hz);
0752 
0753     /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
0754     REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
0755 
0756     /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
0757     REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
0758 
0759     /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
0760     REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
0761 
0762     /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
0763     REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
0764 
0765     /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
0766     REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
0767 
0768     /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
0769     REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
0770 
0771     /* Video driver cannot know in advance which sample rate will
0772      * be used by HD Audio driver
0773      * HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
0774      * programmed below in interruppt callback
0775      */
0776 }
0777 
0778 void enc3_se_hdmi_audio_setup(
0779     struct stream_encoder *enc,
0780     unsigned int az_inst,
0781     struct audio_info *info,
0782     struct audio_crtc_info *audio_crtc_info)
0783 {
0784     enc1_se_enable_audio_clock(enc, true);
0785     enc3_se_setup_hdmi_audio(enc, audio_crtc_info);
0786     ASSERT (enc->afmt);
0787     enc->afmt->funcs->se_audio_setup(enc->afmt, az_inst, info);
0788 }
0789 
0790 
0791 static const struct stream_encoder_funcs dcn30_str_enc_funcs = {
0792     .dp_set_odm_combine =
0793         enc3_dp_set_odm_combine,
0794     .dp_set_stream_attribute =
0795         enc2_stream_encoder_dp_set_stream_attribute,
0796     .hdmi_set_stream_attribute =
0797         enc3_stream_encoder_hdmi_set_stream_attribute,
0798     .dvi_set_stream_attribute =
0799         enc3_stream_encoder_dvi_set_stream_attribute,
0800     .set_throttled_vcp_size =
0801         enc1_stream_encoder_set_throttled_vcp_size,
0802     .update_hdmi_info_packets =
0803         enc3_stream_encoder_update_hdmi_info_packets,
0804     .stop_hdmi_info_packets =
0805         enc3_stream_encoder_stop_hdmi_info_packets,
0806     .update_dp_info_packets =
0807         enc3_stream_encoder_update_dp_info_packets,
0808     .stop_dp_info_packets =
0809         enc1_stream_encoder_stop_dp_info_packets,
0810     .dp_blank =
0811         enc1_stream_encoder_dp_blank,
0812     .dp_unblank =
0813         enc2_stream_encoder_dp_unblank,
0814     .audio_mute_control = enc3_audio_mute_control,
0815 
0816     .dp_audio_setup = enc3_se_dp_audio_setup,
0817     .dp_audio_enable = enc3_se_dp_audio_enable,
0818     .dp_audio_disable = enc1_se_dp_audio_disable,
0819 
0820     .hdmi_audio_setup = enc3_se_hdmi_audio_setup,
0821     .hdmi_audio_disable = enc1_se_hdmi_audio_disable,
0822     .setup_stereo_sync  = enc1_setup_stereo_sync,
0823     .set_avmute = enc1_stream_encoder_set_avmute,
0824     .dig_connect_to_otg = enc1_dig_connect_to_otg,
0825     .dig_source_otg = enc1_dig_source_otg,
0826 
0827     .dp_get_pixel_format  = enc1_stream_encoder_dp_get_pixel_format,
0828 
0829     .enc_read_state = enc3_read_state,
0830     .dp_set_dsc_config = enc3_dp_set_dsc_config,
0831     .dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet,
0832     .set_dynamic_metadata = enc2_set_dynamic_metadata,
0833     .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
0834 
0835     .get_fifo_cal_average_level = enc2_get_fifo_cal_average_level,
0836 };
0837 
0838 void dcn30_dio_stream_encoder_construct(
0839     struct dcn10_stream_encoder *enc1,
0840     struct dc_context *ctx,
0841     struct dc_bios *bp,
0842     enum engine_id eng_id,
0843     struct vpg *vpg,
0844     struct afmt *afmt,
0845     const struct dcn10_stream_enc_registers *regs,
0846     const struct dcn10_stream_encoder_shift *se_shift,
0847     const struct dcn10_stream_encoder_mask *se_mask)
0848 {
0849     enc1->base.funcs = &dcn30_str_enc_funcs;
0850     enc1->base.ctx = ctx;
0851     enc1->base.id = eng_id;
0852     enc1->base.bp = bp;
0853     enc1->base.vpg = vpg;
0854     enc1->base.afmt = afmt;
0855     enc1->regs = regs;
0856     enc1->se_shift = se_shift;
0857     enc1->se_mask = se_mask;
0858     enc1->base.stream_enc_inst = vpg->inst;
0859 }
0860
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