dc/dcn30/dcn30_dio_link_encoder.h

0001 /*
0002  * Copyright 2020 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  *  and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef __DC_LINK_ENCODER__DCN30_H__
0027 #define __DC_LINK_ENCODER__DCN30_H__
0028
0029 #include "dcn20/dcn20_link_encoder.h"
0030
0031 #define LE_DCN3_REG_LIST(id)\
0032     SRI(DIG_BE_CNTL, DIG, id), \
0033     SRI(DIG_BE_EN_CNTL, DIG, id), \
0034     SRI(TMDS_CTL_BITS, DIG, id), \
0035     SRI(TMDS_DCBALANCER_CONTROL, DIG, id), \
0036     SRI(DP_CONFIG, DP, id), \
0037     SRI(DP_DPHY_CNTL, DP, id), \
0038     SRI(DP_DPHY_PRBS_CNTL, DP, id), \
0039     SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
0040     SRI(DP_DPHY_SYM0, DP, id), \
0041     SRI(DP_DPHY_SYM1, DP, id), \
0042     SRI(DP_DPHY_SYM2, DP, id), \
0043     SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
0044     SRI(DP_LINK_CNTL, DP, id), \
0045     SRI(DP_LINK_FRAMING_CNTL, DP, id), \
0046     SRI(DP_MSE_SAT0, DP, id), \
0047     SRI(DP_MSE_SAT1, DP, id), \
0048     SRI(DP_MSE_SAT2, DP, id), \
0049     SRI(DP_MSE_SAT_UPDATE, DP, id), \
0050     SRI(DP_SEC_CNTL, DP, id), \
0051     SRI(DP_VID_STREAM_CNTL, DP, id), \
0052     SRI(DP_DPHY_FAST_TRAINING, DP, id), \
0053     SRI(DP_SEC_CNTL1, DP, id), \
0054     SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
0055     SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)
0056
0057 #define LINK_ENCODER_MASK_SH_LIST_DCN30(mask_sh) \
0058     LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh)
0059
0060 #define DPCS_DCN3_MASK_SH_LIST(mask_sh)\
0061     DPCS_DCN2_MASK_SH_LIST(mask_sh),\
0062     LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_DATA_ORDER_INVERT_18_BIT, mask_sh),\
0063     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_TX_VBOOST_LVL, mask_sh),\
0064     LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_TX_CLK_EN, mask_sh),\
0065     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, mask_sh),\
0066     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, mask_sh)
0067
0068
0069 void dcn30_link_encoder_construct(
0070     struct dcn20_link_encoder *enc20,
0071     const struct encoder_init_data *init_data,
0072     const struct encoder_feature_support *enc_features,
0073     const struct dcn10_link_enc_registers *link_regs,
0074     const struct dcn10_link_enc_aux_registers *aux_regs,
0075     const struct dcn10_link_enc_hpd_registers *hpd_regs,
0076     const struct dcn10_link_enc_shift *link_shift,
0077     const struct dcn10_link_enc_mask *link_mask);
0078
0079 void enc3_hw_init(struct link_encoder *enc);
0080
0081 bool dcn30_link_encoder_validate_output_with_stream(
0082     struct link_encoder *enc,
0083     const struct dc_stream_state *stream);
0084
0085 #endif /* __DC_LINK_ENCODER__DCN30_H__ */