dc/dcn30/dcn30_dio_link_encoder.c

0001 /*
0002  * Copyright 2020 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include "reg_helper.h"
0027
0028 #include "core_types.h"
0029 #include "link_encoder.h"
0030 #include "dcn30_dio_link_encoder.h"
0031 #include "stream_encoder.h"
0032 #include "i2caux_interface.h"
0033 #include "dc_bios_types.h"
0034 /* #include "dcn3ag/dcn3ag_phy_fw.h" */
0035
0036 #include "gpio_service_interface.h"
0037
0038 #define CTX \
0039     enc10->base.ctx
0040 #define DC_LOGGER \
0041     enc10->base.ctx->logger
0042
0043 #define REG(reg)\
0044     (enc10->link_regs->reg)
0045
0046 #undef FN
0047 #define FN(reg_name, field_name) \
0048     enc10->link_shift->field_name, enc10->link_mask->field_name
0049
0050 #define IND_REG(index) \
0051     (enc10->link_regs->index)
0052
0053
0054 bool dcn30_link_encoder_validate_output_with_stream(
0055     struct link_encoder *enc,
0056     const struct dc_stream_state *stream)
0057 {
0058         return dcn10_link_encoder_validate_output_with_stream(enc, stream);
0059 }
0060
0061 static const struct link_encoder_funcs dcn30_link_enc_funcs = {
0062     .read_state = link_enc2_read_state,
0063     .validate_output_with_stream =
0064             dcn30_link_encoder_validate_output_with_stream,
0065     .hw_init = enc3_hw_init,
0066     .setup = dcn10_link_encoder_setup,
0067     .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
0068     .enable_dp_output = dcn20_link_encoder_enable_dp_output,
0069     .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
0070     .disable_output = dcn10_link_encoder_disable_output,
0071     .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
0072     .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
0073     .update_mst_stream_allocation_table =
0074         dcn10_link_encoder_update_mst_stream_allocation_table,
0075     .psr_program_dp_dphy_fast_training =
0076             dcn10_psr_program_dp_dphy_fast_training,
0077     .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
0078     .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
0079     .enable_hpd = dcn10_link_encoder_enable_hpd,
0080     .disable_hpd = dcn10_link_encoder_disable_hpd,
0081     .is_dig_enabled = dcn10_is_dig_enabled,
0082     .destroy = dcn10_link_encoder_destroy,
0083     .fec_set_enable = enc2_fec_set_enable,
0084     .fec_set_ready = enc2_fec_set_ready,
0085     .fec_is_active = enc2_fec_is_active,
0086     .get_dig_frontend = dcn10_get_dig_frontend,
0087     .get_dig_mode = dcn10_get_dig_mode,
0088     .is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode,
0089     .get_max_link_cap = dcn20_link_encoder_get_max_link_cap,
0090 };
0091
0092 void dcn30_link_encoder_construct(
0093     struct dcn20_link_encoder *enc20,
0094     const struct encoder_init_data *init_data,
0095     const struct encoder_feature_support *enc_features,
0096     const struct dcn10_link_enc_registers *link_regs,
0097     const struct dcn10_link_enc_aux_registers *aux_regs,
0098     const struct dcn10_link_enc_hpd_registers *hpd_regs,
0099     const struct dcn10_link_enc_shift *link_shift,
0100     const struct dcn10_link_enc_mask *link_mask)
0101 {
0102     struct bp_encoder_cap_info bp_cap_info = {0};
0103     const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
0104     enum bp_result result = BP_RESULT_OK;
0105     struct dcn10_link_encoder *enc10 = &enc20->enc10;
0106
0107     enc10->base.funcs = &dcn30_link_enc_funcs;
0108     enc10->base.ctx = init_data->ctx;
0109     enc10->base.id = init_data->encoder;
0110
0111     enc10->base.hpd_source = init_data->hpd_source;
0112     enc10->base.connector = init_data->connector;
0113
0114     enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
0115
0116     enc10->base.features = *enc_features;
0117
0118     enc10->base.transmitter = init_data->transmitter;
0119
0120     /* set the flag to indicate whether driver poll the I2C data pin
0121      * while doing the DP sink detect
0122      */
0123
0124 /*  if (dal_adapter_service_is_feature_supported(as,
0125         FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
0126         enc10->base.features.flags.bits.
0127             DP_SINK_DETECT_POLL_DATA_PIN = true;*/
0128
0129     enc10->base.output_signals =
0130         SIGNAL_TYPE_DVI_SINGLE_LINK |
0131         SIGNAL_TYPE_DVI_DUAL_LINK |
0132         SIGNAL_TYPE_LVDS |
0133         SIGNAL_TYPE_DISPLAY_PORT |
0134         SIGNAL_TYPE_DISPLAY_PORT_MST |
0135         SIGNAL_TYPE_EDP |
0136         SIGNAL_TYPE_HDMI_TYPE_A;
0137
0138     /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
0139      * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
0140      * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
0141      * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
0142      * Prefer DIG assignment is decided by board design.
0143      * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
0144      * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
0145      * By this, adding DIGG should not hurt DCE 8.0.
0146      * This will let DCE 8.1 share DCE 8.0 as much as possible
0147      */
0148
0149     enc10->link_regs = link_regs;
0150     enc10->aux_regs = aux_regs;
0151     enc10->hpd_regs = hpd_regs;
0152     enc10->link_shift = link_shift;
0153     enc10->link_mask = link_mask;
0154
0155     switch (enc10->base.transmitter) {
0156     case TRANSMITTER_UNIPHY_A:
0157         enc10->base.preferred_engine = ENGINE_ID_DIGA;
0158     break;
0159     case TRANSMITTER_UNIPHY_B:
0160         enc10->base.preferred_engine = ENGINE_ID_DIGB;
0161     break;
0162     case TRANSMITTER_UNIPHY_C:
0163         enc10->base.preferred_engine = ENGINE_ID_DIGC;
0164     break;
0165     case TRANSMITTER_UNIPHY_D:
0166         enc10->base.preferred_engine = ENGINE_ID_DIGD;
0167     break;
0168     case TRANSMITTER_UNIPHY_E:
0169         enc10->base.preferred_engine = ENGINE_ID_DIGE;
0170     break;
0171     case TRANSMITTER_UNIPHY_F:
0172         enc10->base.preferred_engine = ENGINE_ID_DIGF;
0173     break;
0174     case TRANSMITTER_UNIPHY_G:
0175         enc10->base.preferred_engine = ENGINE_ID_DIGG;
0176     break;
0177     default:
0178         ASSERT_CRITICAL(false);
0179         enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
0180     }
0181
0182     /* default to one to mirror Windows behavior */
0183     enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
0184
0185     result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
0186                         enc10->base.id, &bp_cap_info);
0187
0188     /* Override features with DCE-specific values */
0189     if (result == BP_RESULT_OK) {
0190         enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
0191                 bp_cap_info.DP_HBR2_EN;
0192         enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
0193                 bp_cap_info.DP_HBR3_EN;
0194         enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
0195         enc10->base.features.flags.bits.IS_DP2_CAPABLE = bp_cap_info.IS_DP2_CAPABLE;
0196         enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN;
0197         enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN;
0198         enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN;
0199         enc10->base.features.flags.bits.DP_IS_USB_C =
0200                 bp_cap_info.DP_IS_USB_C;
0201     } else {
0202         DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
0203                 __func__,
0204                 result);
0205     }
0206     if (enc10->base.ctx->dc->debug.hdmi20_disable) {
0207         enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
0208     }
0209 }
0210
0211 #define AUX_REG(reg)\
0212     (enc10->aux_regs->reg)
0213
0214 #define AUX_REG_READ(reg_name) \
0215         dm_read_reg(CTX, AUX_REG(reg_name))
0216
0217 #define AUX_REG_WRITE(reg_name, val) \
0218             dm_write_reg(CTX, AUX_REG(reg_name), val)
0219 void enc3_hw_init(struct link_encoder *enc)
0220 {
0221     struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
0222
0223 /*
0224     00 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 : 1/2
0225     01 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 : 3/4
0226     02 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 : 7/8
0227     03 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 : 15/16
0228     04 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 : 31/32
0229     05 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 : 63/64
0230     06 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 : 127/128
0231     07 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 : 255/256
0232 */
0233
0234 /*
0235     AUX_REG_UPDATE_5(AUX_DPHY_RX_CONTROL0,
0236     AUX_RX_START_WINDOW = 1 [6:4]
0237     AUX_RX_RECEIVE_WINDOW = 1 default is 2 [10:8]
0238     AUX_RX_HALF_SYM_DETECT_LEN  = 1 [13:12] default is 1
0239     AUX_RX_TRANSITION_FILTER_EN = 1 [16] default is 1
0240     AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT [17] is 0  default is 0
0241     AUX_RX_ALLOW_BELOW_THRESHOLD_START [18] is 1  default is 1
0242     AUX_RX_ALLOW_BELOW_THRESHOLD_STOP [19] is 1  default is 1
0243     AUX_RX_PHASE_DETECT_LEN,  [21,20] = 0x3 default is 3
0244     AUX_RX_DETECTION_THRESHOLD [30:28] = 1
0245 */
0246     AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110);
0247
0248     AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a);
0249
0250     //AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32;
0251     // Set AUX_TX_REF_DIV Divider to generate 2 MHz reference from refclk
0252     // 27MHz -> 0xd
0253     // 100MHz -> 0x32
0254     // 48MHz -> 0x18
0255
0256     // Set TMDS_CTL0 to 1.  This is a legacy setting.
0257     REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1);
0258
0259     dcn10_aux_initialize(enc10);
0260 }