dc/dcn30/dcn30_dccg.h

0001 /*
0002  * Copyright 2020 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef __DCN30_DCCG_H__
0027 #define __DCN30_DCCG_H__
0028
0029 #include "dcn20/dcn20_dccg.h"
0030
0031
0032 #define DCCG_REG_LIST_DCN3AG() \
0033     DCCG_COMMON_REG_LIST_DCN_BASE(),\
0034     SR(PHYASYMCLK_CLOCK_CNTL),\
0035     SR(PHYBSYMCLK_CLOCK_CNTL),\
0036     SR(PHYCSYMCLK_CLOCK_CNTL)
0037
0038
0039 #define DCCG_REG_LIST_DCN30() \
0040     DCCG_REG_LIST_DCN2(),\
0041     DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
0042     DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
0043     DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\
0044     DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5),\
0045     SR(PHYASYMCLK_CLOCK_CNTL),\
0046     SR(PHYBSYMCLK_CLOCK_CNTL),\
0047     SR(PHYCSYMCLK_CLOCK_CNTL)
0048
0049 #define DCCG_MASK_SH_LIST_DCN3AG(mask_sh) \
0050     DCCG_MASK_SH_LIST_DCN2_1(mask_sh),\
0051     DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_EN, mask_sh),\
0052     DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_SRC_SEL, mask_sh),\
0053     DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\
0054     DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\
0055     DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\
0056     DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\
0057     DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\
0058     DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh)
0059
0060 #define DCCG_MASK_SH_LIST_DCN3(mask_sh) \
0061     DCCG_MASK_SH_LIST_DCN2(mask_sh),\
0062     DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\
0063     DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\
0064     DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\
0065     DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\
0066     DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\
0067     DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh),\
0068
0069 struct dccg *dccg3_create(
0070     struct dc_context *ctx,
0071     const struct dccg_registers *regs,
0072     const struct dccg_shift *dccg_shift,
0073     const struct dccg_mask *dccg_mask);
0074
0075 struct dccg *dccg30_create(
0076     struct dc_context *ctx,
0077     const struct dccg_registers *regs,
0078     const struct dccg_shift *dccg_shift,
0079     const struct dccg_mask *dccg_mask);
0080
0081 #endif //__DCN30_DCCG_H__