dc/dcn21/dcn21_link_encoder.c

0001 /*
0002  * Copyright 2012-15 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include "reg_helper.h"
0027
0028 #include <linux/delay.h>
0029 #include "core_types.h"
0030 #include "link_encoder.h"
0031 #include "dcn21_link_encoder.h"
0032 #include "stream_encoder.h"
0033
0034 #include "i2caux_interface.h"
0035 #include "dc_bios_types.h"
0036
0037 #include "gpio_service_interface.h"
0038
0039 #define CTX \
0040     enc10->base.ctx
0041 #define DC_LOGGER \
0042     enc10->base.ctx->logger
0043
0044 #define REG(reg)\
0045     (enc10->link_regs->reg)
0046
0047 #undef FN
0048 #define FN(reg_name, field_name) \
0049     enc10->link_shift->field_name, enc10->link_mask->field_name
0050
0051 #define IND_REG(index) \
0052     (enc10->link_regs->index)
0053
0054 static struct mpll_cfg dcn21_mpll_cfg_ref[] = {
0055     // RBR
0056     {
0057         .hdmimode_enable = 0,
0058         .ref_range = 1,
0059         .ref_clk_mpllb_div = 1,
0060         .mpllb_ssc_en = 1,
0061         .mpllb_div5_clk_en = 1,
0062         .mpllb_multiplier = 238,
0063         .mpllb_fracn_en = 0,
0064         .mpllb_fracn_quot = 0,
0065         .mpllb_fracn_rem = 0,
0066         .mpllb_fracn_den = 1,
0067         .mpllb_ssc_up_spread = 0,
0068         .mpllb_ssc_peak = 44237,
0069         .mpllb_ssc_stepsize = 59454,
0070         .mpllb_div_clk_en = 0,
0071         .mpllb_div_multiplier = 0,
0072         .mpllb_hdmi_div = 0,
0073         .mpllb_tx_clk_div = 2,
0074         .tx_vboost_lvl = 5,
0075         .mpllb_pmix_en = 1,
0076         .mpllb_word_div2_en = 0,
0077         .mpllb_ana_v2i = 2,
0078         .mpllb_ana_freq_vco = 2,
0079         .mpllb_ana_cp_int = 9,
0080         .mpllb_ana_cp_prop = 15,
0081         .hdmi_pixel_clk_div = 0,
0082     },
0083     // HBR
0084     {
0085         .hdmimode_enable = 0,
0086         .ref_range = 1,
0087         .ref_clk_mpllb_div = 1,
0088         .mpllb_ssc_en = 1,
0089         .mpllb_div5_clk_en = 1,
0090         .mpllb_multiplier = 192,
0091         .mpllb_fracn_en = 1,
0092         .mpllb_fracn_quot = 32768,
0093         .mpllb_fracn_rem = 0,
0094         .mpllb_fracn_den = 1,
0095         .mpllb_ssc_up_spread = 0,
0096         .mpllb_ssc_peak = 36864,
0097         .mpllb_ssc_stepsize = 49545,
0098         .mpllb_div_clk_en = 0,
0099         .mpllb_div_multiplier = 0,
0100         .mpllb_hdmi_div = 0,
0101         .mpllb_tx_clk_div = 1,
0102         .tx_vboost_lvl = 5,
0103         .mpllb_pmix_en = 1,
0104         .mpllb_word_div2_en = 0,
0105         .mpllb_ana_v2i = 2,
0106         .mpllb_ana_freq_vco = 3,
0107         .mpllb_ana_cp_int = 9,
0108         .mpllb_ana_cp_prop = 15,
0109         .hdmi_pixel_clk_div = 0,
0110     },
0111     //HBR2
0112     {
0113         .hdmimode_enable = 0,
0114         .ref_range = 1,
0115         .ref_clk_mpllb_div = 1,
0116         .mpllb_ssc_en = 1,
0117         .mpllb_div5_clk_en = 1,
0118         .mpllb_multiplier = 192,
0119         .mpllb_fracn_en = 1,
0120         .mpllb_fracn_quot = 32768,
0121         .mpllb_fracn_rem = 0,
0122         .mpllb_fracn_den = 1,
0123         .mpllb_ssc_up_spread = 0,
0124         .mpllb_ssc_peak = 36864,
0125         .mpllb_ssc_stepsize = 49545,
0126         .mpllb_div_clk_en = 0,
0127         .mpllb_div_multiplier = 0,
0128         .mpllb_hdmi_div = 0,
0129         .mpllb_tx_clk_div = 0,
0130         .tx_vboost_lvl = 5,
0131         .mpllb_pmix_en = 1,
0132         .mpllb_word_div2_en = 0,
0133         .mpllb_ana_v2i = 2,
0134         .mpllb_ana_freq_vco = 3,
0135         .mpllb_ana_cp_int = 9,
0136         .mpllb_ana_cp_prop = 15,
0137         .hdmi_pixel_clk_div = 0,
0138     },
0139     //HBR3
0140     {
0141         .hdmimode_enable = 0,
0142         .ref_range = 1,
0143         .ref_clk_mpllb_div = 1,
0144         .mpllb_ssc_en = 1,
0145         .mpllb_div5_clk_en = 1,
0146         .mpllb_multiplier = 304,
0147         .mpllb_fracn_en = 1,
0148         .mpllb_fracn_quot = 49152,
0149         .mpllb_fracn_rem = 0,
0150         .mpllb_fracn_den = 1,
0151         .mpllb_ssc_up_spread = 0,
0152         .mpllb_ssc_peak = 55296,
0153         .mpllb_ssc_stepsize = 74318,
0154         .mpllb_div_clk_en = 0,
0155         .mpllb_div_multiplier = 0,
0156         .mpllb_hdmi_div = 0,
0157         .mpllb_tx_clk_div = 0,
0158         .tx_vboost_lvl = 5,
0159         .mpllb_pmix_en = 1,
0160         .mpllb_word_div2_en = 0,
0161         .mpllb_ana_v2i = 2,
0162         .mpllb_ana_freq_vco = 1,
0163         .mpllb_ana_cp_int = 7,
0164         .mpllb_ana_cp_prop = 16,
0165         .hdmi_pixel_clk_div = 0,
0166     },
0167 };
0168
0169
0170 static bool update_cfg_data(
0171         struct dcn10_link_encoder *enc10,
0172         const struct dc_link_settings *link_settings,
0173         struct dpcssys_phy_seq_cfg *cfg)
0174 {
0175     int i;
0176
0177     cfg->load_sram_fw = false;
0178     cfg->use_calibration_setting = true;
0179
0180     //TODO: need to implement a proper lane mapping for Renoir.
0181     for (i = 0; i < 4; i++)
0182         cfg->lane_en[i] = true;
0183
0184     switch (link_settings->link_rate) {
0185     case LINK_RATE_LOW:
0186         cfg->mpll_cfg = dcn21_mpll_cfg_ref[0];
0187         break;
0188     case LINK_RATE_HIGH:
0189         cfg->mpll_cfg = dcn21_mpll_cfg_ref[1];
0190         break;
0191     case LINK_RATE_HIGH2:
0192         cfg->mpll_cfg = dcn21_mpll_cfg_ref[2];
0193         break;
0194     case LINK_RATE_HIGH3:
0195         cfg->mpll_cfg = dcn21_mpll_cfg_ref[3];
0196         break;
0197     default:
0198         DC_LOG_ERROR("%s: No supported link rate found %X!\n",
0199                 __func__, link_settings->link_rate);
0200         return false;
0201     }
0202
0203     return true;
0204 }
0205
0206 static bool dcn21_link_encoder_acquire_phy(struct link_encoder *enc)
0207 {
0208     struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
0209     int value;
0210
0211     if (enc->features.flags.bits.DP_IS_USB_C) {
0212         REG_GET(RDPCSTX_PHY_CNTL6,
0213                 RDPCS_PHY_DPALT_DISABLE, &value);
0214
0215         if (value == 1) {
0216             ASSERT(0);
0217             return false;
0218         }
0219         REG_UPDATE(RDPCSTX_PHY_CNTL6,
0220                 RDPCS_PHY_DPALT_DISABLE_ACK, 0);
0221
0222         udelay(40);
0223
0224         REG_GET(RDPCSTX_PHY_CNTL6,
0225                         RDPCS_PHY_DPALT_DISABLE, &value);
0226         if (value == 1) {
0227             ASSERT(0);
0228             REG_UPDATE(RDPCSTX_PHY_CNTL6,
0229                     RDPCS_PHY_DPALT_DISABLE_ACK, 1);
0230             return false;
0231         }
0232     }
0233
0234     REG_UPDATE(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_REF_CLK_EN, 1);
0235
0236     return true;
0237 }
0238
0239
0240
0241 static void dcn21_link_encoder_release_phy(struct link_encoder *enc)
0242 {
0243     struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
0244
0245     if (enc->features.flags.bits.DP_IS_USB_C) {
0246         REG_UPDATE(RDPCSTX_PHY_CNTL6,
0247                 RDPCS_PHY_DPALT_DISABLE_ACK, 1);
0248     }
0249
0250     REG_UPDATE(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_REF_CLK_EN, 0);
0251
0252 }
0253
0254 void dcn21_link_encoder_enable_dp_output(
0255     struct link_encoder *enc,
0256     const struct dc_link_settings *link_settings,
0257     enum clock_source_id clock_source)
0258 {
0259     struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
0260     struct dcn21_link_encoder *enc21 = (struct dcn21_link_encoder *) enc10;
0261     struct dpcssys_phy_seq_cfg *cfg = &enc21->phy_seq_cfg;
0262
0263     if (!dcn21_link_encoder_acquire_phy(enc))
0264         return;
0265
0266     if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
0267         dcn10_link_encoder_enable_dp_output(enc, link_settings, clock_source);
0268         return;
0269     }
0270
0271     if (!update_cfg_data(enc10, link_settings, cfg))
0272         return;
0273
0274     enc1_configure_encoder(enc10, link_settings);
0275
0276     dcn10_link_encoder_setup(enc, SIGNAL_TYPE_DISPLAY_PORT);
0277
0278 }
0279
0280 static void dcn21_link_encoder_enable_dp_mst_output(
0281     struct link_encoder *enc,
0282     const struct dc_link_settings *link_settings,
0283     enum clock_source_id clock_source)
0284 {
0285     if (!dcn21_link_encoder_acquire_phy(enc))
0286         return;
0287
0288     dcn10_link_encoder_enable_dp_mst_output(enc, link_settings, clock_source);
0289 }
0290
0291 static void dcn21_link_encoder_disable_output(struct link_encoder *enc,
0292                           enum signal_type signal)
0293 {
0294     dcn10_link_encoder_disable_output(enc, signal);
0295
0296     if (dc_is_dp_signal(signal))
0297         dcn21_link_encoder_release_phy(enc);
0298 }
0299
0300
0301 static const struct link_encoder_funcs dcn21_link_enc_funcs = {
0302     .read_state = link_enc2_read_state,
0303     .validate_output_with_stream =
0304         dcn10_link_encoder_validate_output_with_stream,
0305     .hw_init = enc2_hw_init,
0306     .setup = dcn10_link_encoder_setup,
0307     .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
0308     .enable_dp_output = dcn21_link_encoder_enable_dp_output,
0309     .enable_dp_mst_output = dcn21_link_encoder_enable_dp_mst_output,
0310     .disable_output = dcn21_link_encoder_disable_output,
0311     .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
0312     .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
0313     .update_mst_stream_allocation_table =
0314         dcn10_link_encoder_update_mst_stream_allocation_table,
0315     .psr_program_dp_dphy_fast_training =
0316             dcn10_psr_program_dp_dphy_fast_training,
0317     .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
0318     .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
0319     .enable_hpd = dcn10_link_encoder_enable_hpd,
0320     .disable_hpd = dcn10_link_encoder_disable_hpd,
0321     .is_dig_enabled = dcn10_is_dig_enabled,
0322     .destroy = dcn10_link_encoder_destroy,
0323     .fec_set_enable = enc2_fec_set_enable,
0324     .fec_set_ready = enc2_fec_set_ready,
0325     .fec_is_active = enc2_fec_is_active,
0326     .get_dig_frontend = dcn10_get_dig_frontend,
0327     .is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode,
0328     .get_max_link_cap = dcn20_link_encoder_get_max_link_cap,
0329 };
0330
0331 void dcn21_link_encoder_construct(
0332     struct dcn21_link_encoder *enc21,
0333     const struct encoder_init_data *init_data,
0334     const struct encoder_feature_support *enc_features,
0335     const struct dcn10_link_enc_registers *link_regs,
0336     const struct dcn10_link_enc_aux_registers *aux_regs,
0337     const struct dcn10_link_enc_hpd_registers *hpd_regs,
0338     const struct dcn10_link_enc_shift *link_shift,
0339     const struct dcn10_link_enc_mask *link_mask)
0340 {
0341     struct bp_encoder_cap_info bp_cap_info = {0};
0342     const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
0343     enum bp_result result = BP_RESULT_OK;
0344     struct dcn10_link_encoder *enc10 = &enc21->enc10;
0345
0346     enc10->base.funcs = &dcn21_link_enc_funcs;
0347     enc10->base.ctx = init_data->ctx;
0348     enc10->base.id = init_data->encoder;
0349
0350     enc10->base.hpd_source = init_data->hpd_source;
0351     enc10->base.connector = init_data->connector;
0352
0353     enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
0354
0355     enc10->base.features = *enc_features;
0356
0357     enc10->base.transmitter = init_data->transmitter;
0358
0359     /* set the flag to indicate whether driver poll the I2C data pin
0360      * while doing the DP sink detect
0361      */
0362
0363 /*  if (dal_adapter_service_is_feature_supported(as,
0364         FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
0365         enc10->base.features.flags.bits.
0366             DP_SINK_DETECT_POLL_DATA_PIN = true;*/
0367
0368     enc10->base.output_signals =
0369         SIGNAL_TYPE_DVI_SINGLE_LINK |
0370         SIGNAL_TYPE_DVI_DUAL_LINK |
0371         SIGNAL_TYPE_LVDS |
0372         SIGNAL_TYPE_DISPLAY_PORT |
0373         SIGNAL_TYPE_DISPLAY_PORT_MST |
0374         SIGNAL_TYPE_EDP |
0375         SIGNAL_TYPE_HDMI_TYPE_A;
0376
0377     /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
0378      * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
0379      * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
0380      * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
0381      * Prefer DIG assignment is decided by board design.
0382      * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
0383      * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
0384      * By this, adding DIGG should not hurt DCE 8.0.
0385      * This will let DCE 8.1 share DCE 8.0 as much as possible
0386      */
0387
0388     enc10->link_regs = link_regs;
0389     enc10->aux_regs = aux_regs;
0390     enc10->hpd_regs = hpd_regs;
0391     enc10->link_shift = link_shift;
0392     enc10->link_mask = link_mask;
0393
0394     switch (enc10->base.transmitter) {
0395     case TRANSMITTER_UNIPHY_A:
0396         enc10->base.preferred_engine = ENGINE_ID_DIGA;
0397     break;
0398     case TRANSMITTER_UNIPHY_B:
0399         enc10->base.preferred_engine = ENGINE_ID_DIGB;
0400     break;
0401     case TRANSMITTER_UNIPHY_C:
0402         enc10->base.preferred_engine = ENGINE_ID_DIGC;
0403     break;
0404     case TRANSMITTER_UNIPHY_D:
0405         enc10->base.preferred_engine = ENGINE_ID_DIGD;
0406     break;
0407     case TRANSMITTER_UNIPHY_E:
0408         enc10->base.preferred_engine = ENGINE_ID_DIGE;
0409     break;
0410     case TRANSMITTER_UNIPHY_F:
0411         enc10->base.preferred_engine = ENGINE_ID_DIGF;
0412     break;
0413     case TRANSMITTER_UNIPHY_G:
0414         enc10->base.preferred_engine = ENGINE_ID_DIGG;
0415     break;
0416     default:
0417         ASSERT_CRITICAL(false);
0418         enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
0419     }
0420
0421     /* default to one to mirror Windows behavior */
0422     enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
0423
0424     result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
0425                         enc10->base.id, &bp_cap_info);
0426
0427     /* Override features with DCE-specific values */
0428     if (result == BP_RESULT_OK) {
0429         enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
0430                 bp_cap_info.DP_HBR2_EN;
0431         enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
0432                 bp_cap_info.DP_HBR3_EN;
0433         enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
0434         enc10->base.features.flags.bits.DP_IS_USB_C =
0435                 bp_cap_info.DP_IS_USB_C;
0436     } else {
0437         DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
0438                 __func__,
0439                 result);
0440     }
0441     if (enc10->base.ctx->dc->debug.hdmi20_disable) {
0442         enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
0443     }
0444 }