dc/dcn21/dcn21_init.c

0001 /*
0002  * Copyright 2016-2020 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include "dce110/dce110_hw_sequencer.h"
0027 #include "dcn10/dcn10_hw_sequencer.h"
0028 #include "dcn20/dcn20_hwseq.h"
0029 #include "dcn21_hwseq.h"
0030
0031 #include "dcn21_init.h"
0032
0033 static const struct hw_sequencer_funcs dcn21_funcs = {
0034     .program_gamut_remap = dcn10_program_gamut_remap,
0035     .init_hw = dcn10_init_hw,
0036     .power_down_on_boot = dcn10_power_down_on_boot,
0037     .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
0038     .apply_ctx_for_surface = NULL,
0039     .program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
0040     .wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
0041     .post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
0042     .update_plane_addr = dcn20_update_plane_addr,
0043     .update_dchub = dcn10_update_dchub,
0044     .update_pending_status = dcn10_update_pending_status,
0045     .program_output_csc = dcn20_program_output_csc,
0046     .enable_accelerated_mode = dce110_enable_accelerated_mode,
0047     .enable_timing_synchronization = dcn10_enable_timing_synchronization,
0048     .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
0049     .update_info_frame = dce110_update_info_frame,
0050     .send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
0051     .enable_stream = dcn20_enable_stream,
0052     .disable_stream = dce110_disable_stream,
0053     .unblank_stream = dcn20_unblank_stream,
0054     .blank_stream = dce110_blank_stream,
0055     .enable_audio_stream = dce110_enable_audio_stream,
0056     .disable_audio_stream = dce110_disable_audio_stream,
0057     .disable_plane = dcn20_disable_plane,
0058     .pipe_control_lock = dcn20_pipe_control_lock,
0059     .interdependent_update_lock = dcn10_lock_all_pipes,
0060     .cursor_lock = dcn10_cursor_lock,
0061     .prepare_bandwidth = dcn20_prepare_bandwidth,
0062     .optimize_bandwidth = dcn20_optimize_bandwidth,
0063     .update_bandwidth = dcn20_update_bandwidth,
0064     .set_drr = dcn10_set_drr,
0065     .get_position = dcn10_get_position,
0066     .set_static_screen_control = dcn10_set_static_screen_control,
0067     .setup_stereo = dcn10_setup_stereo,
0068     .set_avmute = dce110_set_avmute,
0069     .log_hw_state = dcn10_log_hw_state,
0070     .get_hw_state = dcn10_get_hw_state,
0071     .clear_status_bits = dcn10_clear_status_bits,
0072     .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
0073     .edp_backlight_control = dce110_edp_backlight_control,
0074     .edp_power_control = dce110_edp_power_control,
0075     .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
0076     .set_cursor_position = dcn10_set_cursor_position,
0077     .set_cursor_attribute = dcn10_set_cursor_attribute,
0078     .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
0079     .setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
0080     .set_clock = dcn10_set_clock,
0081     .get_clock = dcn10_get_clock,
0082     .program_triplebuffer = dcn20_program_triple_buffer,
0083     .enable_writeback = dcn20_enable_writeback,
0084     .disable_writeback = dcn20_disable_writeback,
0085     .dmdata_status_done = dcn20_dmdata_status_done,
0086     .program_dmdata_engine = dcn20_program_dmdata_engine,
0087     .set_dmdata_attributes = dcn20_set_dmdata_attributes,
0088     .init_sys_ctx = dcn21_init_sys_ctx,
0089     .init_vm_ctx = dcn20_init_vm_ctx,
0090     .set_flip_control_gsl = dcn20_set_flip_control_gsl,
0091     .optimize_pwr_state = dcn21_optimize_pwr_state,
0092     .exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,
0093     .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
0094     .calc_vupdate_position = dcn10_calc_vupdate_position,
0095     .power_down = dce110_power_down,
0096     .set_backlight_level = dcn21_set_backlight_level,
0097     .set_abm_immediate_disable = dcn21_set_abm_immediate_disable,
0098     .set_pipe = dcn21_set_pipe,
0099 #ifndef TRIM_FSFT
0100     .optimize_timing_for_fsft = dcn20_optimize_timing_for_fsft,
0101 #endif
0102     .is_abm_supported = dcn21_is_abm_supported,
0103     .set_disp_pattern_generator = dcn20_set_disp_pattern_generator,
0104     .get_dcc_en_bits = dcn10_get_dcc_en_bits,
0105     .update_visual_confirm_color = dcn20_update_visual_confirm_color,
0106 };
0107
0108 static const struct hwseq_private_funcs dcn21_private_funcs = {
0109     .init_pipes = dcn10_init_pipes,
0110     .update_plane_addr = dcn20_update_plane_addr,
0111     .plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
0112     .update_mpcc = dcn20_update_mpcc,
0113     .set_input_transfer_func = dcn20_set_input_transfer_func,
0114     .set_output_transfer_func = dcn20_set_output_transfer_func,
0115     .power_down = dce110_power_down,
0116     .enable_display_power_gating = dcn10_dummy_display_power_gating,
0117     .blank_pixel_data = dcn20_blank_pixel_data,
0118     .reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap,
0119     .enable_stream_timing = dcn20_enable_stream_timing,
0120     .edp_backlight_control = dce110_edp_backlight_control,
0121     .disable_stream_gating = dcn20_disable_stream_gating,
0122     .enable_stream_gating = dcn20_enable_stream_gating,
0123     .setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,
0124     .did_underflow_occur = dcn10_did_underflow_occur,
0125     .init_blank = dcn20_init_blank,
0126     .disable_vga = dcn20_disable_vga,
0127     .bios_golden_init = dcn10_bios_golden_init,
0128     .plane_atomic_disable = dcn20_plane_atomic_disable,
0129     .plane_atomic_power_down = dcn10_plane_atomic_power_down,
0130     .enable_power_gating_plane = dcn20_enable_power_gating_plane,
0131     .dpp_pg_control = dcn20_dpp_pg_control,
0132     .hubp_pg_control = dcn20_hubp_pg_control,
0133     .update_odm = dcn20_update_odm,
0134     .dsc_pg_control = dcn20_dsc_pg_control,
0135     .set_hdr_multiplier = dcn10_set_hdr_multiplier,
0136     .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
0137     .s0i3_golden_init_wa = dcn21_s0i3_golden_init_wa,
0138     .wait_for_blank_complete = dcn20_wait_for_blank_complete,
0139     .dccg_init = dcn20_dccg_init,
0140     .set_blend_lut = dcn20_set_blend_lut,
0141     .set_shaper_3dlut = dcn20_set_shaper_3dlut,
0142     .PLAT_58856_wa = dcn21_PLAT_58856_wa,
0143 };
0144
0145 void dcn21_hw_sequencer_construct(struct dc *dc)
0146 {
0147     dc->hwss = dcn21_funcs;
0148     dc->hwseq->funcs = dcn21_private_funcs;
0149
0150     if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
0151         dc->hwss.init_hw = dcn20_fpga_init_hw;
0152         dc->hwseq->funcs.init_pipes = NULL;
0153     }
0154 }