dc/dcn21/dcn21_hubp.c

0001 /*
0002 * Copyright 2018 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include "dcn10/dcn10_hubp.h"
0027 #include "dcn21_hubp.h"
0028
0029 #include "dm_services.h"
0030 #include "reg_helper.h"
0031
0032 #include "dc_dmub_srv.h"
0033
0034 #define DC_LOGGER_INIT(logger)
0035
0036 #define REG(reg)\
0037     hubp21->hubp_regs->reg
0038
0039 #define CTX \
0040     hubp21->base.ctx
0041
0042 #undef FN
0043 #define FN(reg_name, field_name) \
0044     hubp21->hubp_shift->field_name, hubp21->hubp_mask->field_name
0045
0046 /*
0047  * In DCN2.1, the non-double buffered version of the following 4 DLG registers are used in RTL.
0048  * As a result, if S/W updates any of these registers during a mode change,
0049  * the current frame before the mode change will use the new value right away
0050  * and can lead to generating incorrect request deadlines and incorrect TTU/QoS behavior.
0051  *
0052  * REFCYC_PER_VM_GROUP_FLIP[22:0]
0053  * REFCYC_PER_VM_GROUP_VBLANK[22:0]
0054  * REFCYC_PER_VM_REQ_FLIP[22:0]
0055  * REFCYC_PER_VM_REQ_VBLANK[22:0]
0056  *
0057  * REFCYC_PER_VM_*_FLIP affects the deadline of the VM requests generated
0058  * when flipping to a new surface
0059  *
0060  * REFCYC_PER_VM_*_VBLANK affects the deadline of the VM requests generated
0061  * during prefetch  period of a frame. The prefetch starts at a pre-determined
0062  * number of lines before the display active per frame
0063  *
0064  * DCN may underflow due to incorrectly programming these registers
0065  * during VM stage of prefetch/iflip. First lines of display active
0066  * or a sub-region of active using a new surface will be corrupted
0067  * until the VM data returns at flip/mode change transitions
0068  *
0069  * Work around:
0070  * workaround is always opt to use the more aggressive settings.
0071  * On any mode switch, if the new reg values are smaller than the current values,
0072  * then update the regs with the new values.
0073  *
0074  * Link to the ticket: http://ontrack-internal.amd.com/browse/DEDCN21-142
0075  *
0076  */
0077 void apply_DEDCN21_142_wa_for_hostvm_deadline(
0078         struct hubp *hubp,
0079         struct _vcs_dpi_display_dlg_regs_st *dlg_attr)
0080 {
0081     struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
0082     uint32_t refcyc_per_vm_group_vblank;
0083     uint32_t refcyc_per_vm_req_vblank;
0084     uint32_t refcyc_per_vm_group_flip;
0085     uint32_t refcyc_per_vm_req_flip;
0086     const uint32_t uninitialized_hw_default = 0;
0087
0088     REG_GET(VBLANK_PARAMETERS_5,
0089             REFCYC_PER_VM_GROUP_VBLANK, &refcyc_per_vm_group_vblank);
0090
0091     if (refcyc_per_vm_group_vblank == uninitialized_hw_default ||
0092             refcyc_per_vm_group_vblank > dlg_attr->refcyc_per_vm_group_vblank)
0093         REG_SET(VBLANK_PARAMETERS_5, 0,
0094                 REFCYC_PER_VM_GROUP_VBLANK, dlg_attr->refcyc_per_vm_group_vblank);
0095
0096     REG_GET(VBLANK_PARAMETERS_6,
0097             REFCYC_PER_VM_REQ_VBLANK, &refcyc_per_vm_req_vblank);
0098
0099     if (refcyc_per_vm_req_vblank == uninitialized_hw_default ||
0100             refcyc_per_vm_req_vblank > dlg_attr->refcyc_per_vm_req_vblank)
0101         REG_SET(VBLANK_PARAMETERS_6, 0,
0102                 REFCYC_PER_VM_REQ_VBLANK, dlg_attr->refcyc_per_vm_req_vblank);
0103
0104     REG_GET(FLIP_PARAMETERS_3,
0105             REFCYC_PER_VM_GROUP_FLIP, &refcyc_per_vm_group_flip);
0106
0107     if (refcyc_per_vm_group_flip == uninitialized_hw_default ||
0108             refcyc_per_vm_group_flip > dlg_attr->refcyc_per_vm_group_flip)
0109         REG_SET(FLIP_PARAMETERS_3, 0,
0110                 REFCYC_PER_VM_GROUP_FLIP, dlg_attr->refcyc_per_vm_group_flip);
0111
0112     REG_GET(FLIP_PARAMETERS_4,
0113             REFCYC_PER_VM_REQ_FLIP, &refcyc_per_vm_req_flip);
0114
0115     if (refcyc_per_vm_req_flip == uninitialized_hw_default ||
0116             refcyc_per_vm_req_flip > dlg_attr->refcyc_per_vm_req_flip)
0117         REG_SET(FLIP_PARAMETERS_4, 0,
0118                     REFCYC_PER_VM_REQ_FLIP, dlg_attr->refcyc_per_vm_req_flip);
0119
0120     REG_SET(FLIP_PARAMETERS_5, 0,
0121             REFCYC_PER_PTE_GROUP_FLIP_C, dlg_attr->refcyc_per_pte_group_flip_c);
0122
0123     REG_SET(FLIP_PARAMETERS_6, 0,
0124             REFCYC_PER_META_CHUNK_FLIP_C, dlg_attr->refcyc_per_meta_chunk_flip_c);
0125 }
0126
0127 void hubp21_program_deadline(
0128         struct hubp *hubp,
0129         struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
0130         struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
0131 {
0132     hubp2_program_deadline(hubp, dlg_attr, ttu_attr);
0133
0134     apply_DEDCN21_142_wa_for_hostvm_deadline(hubp, dlg_attr);
0135 }
0136
0137 void hubp21_program_requestor(
0138         struct hubp *hubp,
0139         struct _vcs_dpi_display_rq_regs_st *rq_regs)
0140 {
0141     struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
0142
0143     REG_UPDATE(HUBPRET_CONTROL,
0144             DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
0145     REG_SET_4(DCN_EXPANSION_MODE, 0,
0146             DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
0147             PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
0148             MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
0149             CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
0150     REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0,
0151         CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
0152         MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
0153         META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
0154         MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size,
0155         DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size,
0156         VM_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size,
0157         SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height,
0158         PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);
0159     REG_SET_7(DCHUBP_REQ_SIZE_CONFIG_C, 0,
0160         CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size,
0161         MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size,
0162         META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size,
0163         MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size,
0164         DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size,
0165         SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height,
0166         PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear);
0167 }
0168
0169 static void hubp21_setup(
0170         struct hubp *hubp,
0171         struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
0172         struct _vcs_dpi_display_ttu_regs_st *ttu_attr,
0173         struct _vcs_dpi_display_rq_regs_st *rq_regs,
0174         struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
0175 {
0176     /* otg is locked when this func is called. Register are double buffered.
0177      * disable the requestors is not needed
0178      */
0179
0180     hubp2_vready_at_or_After_vsync(hubp, pipe_dest);
0181     hubp21_program_requestor(hubp, rq_regs);
0182     hubp21_program_deadline(hubp, dlg_attr, ttu_attr);
0183
0184 }
0185
0186 static void hubp21_set_viewport(
0187     struct hubp *hubp,
0188     const struct rect *viewport,
0189     const struct rect *viewport_c)
0190 {
0191     struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
0192
0193     REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0,
0194           PRI_VIEWPORT_WIDTH, viewport->width,
0195           PRI_VIEWPORT_HEIGHT, viewport->height);
0196
0197     REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0,
0198           PRI_VIEWPORT_X_START, viewport->x,
0199           PRI_VIEWPORT_Y_START, viewport->y);
0200
0201     /*for stereo*/
0202     REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0,
0203           SEC_VIEWPORT_WIDTH, viewport->width,
0204           SEC_VIEWPORT_HEIGHT, viewport->height);
0205
0206     REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0,
0207           SEC_VIEWPORT_X_START, viewport->x,
0208           SEC_VIEWPORT_Y_START, viewport->y);
0209
0210     /* DC supports NV12 only at the moment */
0211     REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0,
0212           PRI_VIEWPORT_WIDTH_C, viewport_c->width,
0213           PRI_VIEWPORT_HEIGHT_C, viewport_c->height);
0214
0215     REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0,
0216           PRI_VIEWPORT_X_START_C, viewport_c->x,
0217           PRI_VIEWPORT_Y_START_C, viewport_c->y);
0218
0219     REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0,
0220           SEC_VIEWPORT_WIDTH_C, viewport_c->width,
0221           SEC_VIEWPORT_HEIGHT_C, viewport_c->height);
0222
0223     REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0,
0224           SEC_VIEWPORT_X_START_C, viewport_c->x,
0225           SEC_VIEWPORT_Y_START_C, viewport_c->y);
0226 }
0227
0228 static void hubp21_set_vm_system_aperture_settings(struct hubp *hubp,
0229                            struct vm_system_aperture_param *apt)
0230 {
0231     struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
0232
0233     PHYSICAL_ADDRESS_LOC mc_vm_apt_low;
0234     PHYSICAL_ADDRESS_LOC mc_vm_apt_high;
0235
0236     // The format of high/low are 48:18 of the 48 bit addr
0237     mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18;
0238     mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18;
0239
0240     REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0,
0241             MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part);
0242
0243     REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0,
0244             MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part);
0245
0246     REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
0247             ENABLE_L1_TLB, 1,
0248             SYSTEM_ACCESS_MODE, 0x3);
0249 }
0250
0251 static void hubp21_validate_dml_output(struct hubp *hubp,
0252         struct dc_context *ctx,
0253         struct _vcs_dpi_display_rq_regs_st *dml_rq_regs,
0254         struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr,
0255         struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr)
0256 {
0257     struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
0258     struct _vcs_dpi_display_rq_regs_st rq_regs = {0};
0259     struct _vcs_dpi_display_dlg_regs_st dlg_attr = {0};
0260     struct _vcs_dpi_display_ttu_regs_st ttu_attr = {0};
0261     DC_LOGGER_INIT(ctx->logger);
0262     DC_LOG_DEBUG("DML Validation | Running Validation");
0263
0264     /* Requester - Per hubp */
0265     REG_GET(HUBPRET_CONTROL,
0266         DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs.plane1_base_address);
0267     REG_GET_4(DCN_EXPANSION_MODE,
0268         DRQ_EXPANSION_MODE, &rq_regs.drq_expansion_mode,
0269         PRQ_EXPANSION_MODE, &rq_regs.prq_expansion_mode,
0270         MRQ_EXPANSION_MODE, &rq_regs.mrq_expansion_mode,
0271         CRQ_EXPANSION_MODE, &rq_regs.crq_expansion_mode);
0272     REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,
0273         CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size,
0274         MIN_CHUNK_SIZE, &rq_regs.rq_regs_l.min_chunk_size,
0275         META_CHUNK_SIZE, &rq_regs.rq_regs_l.meta_chunk_size,
0276         MIN_META_CHUNK_SIZE, &rq_regs.rq_regs_l.min_meta_chunk_size,
0277         DPTE_GROUP_SIZE, &rq_regs.rq_regs_l.dpte_group_size,
0278         VM_GROUP_SIZE, &rq_regs.rq_regs_l.mpte_group_size,
0279         SWATH_HEIGHT, &rq_regs.rq_regs_l.swath_height,
0280         PTE_ROW_HEIGHT_LINEAR, &rq_regs.rq_regs_l.pte_row_height_linear);
0281     REG_GET_7(DCHUBP_REQ_SIZE_CONFIG_C,
0282         CHUNK_SIZE_C, &rq_regs.rq_regs_c.chunk_size,
0283         MIN_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_chunk_size,
0284         META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.meta_chunk_size,
0285         MIN_META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_meta_chunk_size,
0286         DPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.dpte_group_size,
0287         SWATH_HEIGHT_C, &rq_regs.rq_regs_c.swath_height,
0288         PTE_ROW_HEIGHT_LINEAR_C, &rq_regs.rq_regs_c.pte_row_height_linear);
0289
0290     if (rq_regs.plane1_base_address != dml_rq_regs->plane1_base_address)
0291         DC_LOG_DEBUG("DML Validation | HUBPRET_CONTROL:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u  Actual: %u\n",
0292                 dml_rq_regs->plane1_base_address, rq_regs.plane1_base_address);
0293     if (rq_regs.drq_expansion_mode != dml_rq_regs->drq_expansion_mode)
0294         DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DRQ_EXPANSION_MODE - Expected: %u  Actual: %u\n",
0295                 dml_rq_regs->drq_expansion_mode, rq_regs.drq_expansion_mode);
0296     if (rq_regs.prq_expansion_mode != dml_rq_regs->prq_expansion_mode)
0297         DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:MRQ_EXPANSION_MODE - Expected: %u  Actual: %u\n",
0298                 dml_rq_regs->prq_expansion_mode, rq_regs.prq_expansion_mode);
0299     if (rq_regs.mrq_expansion_mode != dml_rq_regs->mrq_expansion_mode)
0300         DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u  Actual: %u\n",
0301                 dml_rq_regs->mrq_expansion_mode, rq_regs.mrq_expansion_mode);
0302     if (rq_regs.crq_expansion_mode != dml_rq_regs->crq_expansion_mode)
0303         DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:CRQ_EXPANSION_MODE - Expected: %u  Actual: %u\n",
0304                 dml_rq_regs->crq_expansion_mode, rq_regs.crq_expansion_mode);
0305
0306     if (rq_regs.rq_regs_l.chunk_size != dml_rq_regs->rq_regs_l.chunk_size)
0307         DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:CHUNK_SIZE - Expected: %u  Actual: %u\n",
0308                 dml_rq_regs->rq_regs_l.chunk_size, rq_regs.rq_regs_l.chunk_size);
0309     if (rq_regs.rq_regs_l.min_chunk_size != dml_rq_regs->rq_regs_l.min_chunk_size)
0310         DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_CHUNK_SIZE - Expected: %u  Actual: %u\n",
0311                 dml_rq_regs->rq_regs_l.min_chunk_size, rq_regs.rq_regs_l.min_chunk_size);
0312     if (rq_regs.rq_regs_l.meta_chunk_size != dml_rq_regs->rq_regs_l.meta_chunk_size)
0313         DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:META_CHUNK_SIZE - Expected: %u  Actual: %u\n",
0314                 dml_rq_regs->rq_regs_l.meta_chunk_size, rq_regs.rq_regs_l.meta_chunk_size);
0315     if (rq_regs.rq_regs_l.min_meta_chunk_size != dml_rq_regs->rq_regs_l.min_meta_chunk_size)
0316         DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_META_CHUNK_SIZE - Expected: %u  Actual: %u\n",
0317                 dml_rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs.rq_regs_l.min_meta_chunk_size);
0318     if (rq_regs.rq_regs_l.dpte_group_size != dml_rq_regs->rq_regs_l.dpte_group_size)
0319         DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:DPTE_GROUP_SIZE - Expected: %u  Actual: %u\n",
0320                 dml_rq_regs->rq_regs_l.dpte_group_size, rq_regs.rq_regs_l.dpte_group_size);
0321     if (rq_regs.rq_regs_l.mpte_group_size != dml_rq_regs->rq_regs_l.mpte_group_size)
0322         DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:VM_GROUP_SIZE - Expected: %u  Actual: %u\n",
0323                 dml_rq_regs->rq_regs_l.mpte_group_size, rq_regs.rq_regs_l.mpte_group_size);
0324     if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height)
0325         DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:SWATH_HEIGHT - Expected: %u  Actual: %u\n",
0326                 dml_rq_regs->rq_regs_l.swath_height, rq_regs.rq_regs_l.swath_height);
0327     if (rq_regs.rq_regs_l.pte_row_height_linear != dml_rq_regs->rq_regs_l.pte_row_height_linear)
0328         DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:PTE_ROW_HEIGHT_LINEAR - Expected: %u  Actual: %u\n",
0329                 dml_rq_regs->rq_regs_l.pte_row_height_linear, rq_regs.rq_regs_l.pte_row_height_linear);
0330
0331     if (rq_regs.rq_regs_c.chunk_size != dml_rq_regs->rq_regs_c.chunk_size)
0332         DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:CHUNK_SIZE_C - Expected: %u  Actual: %u\n",
0333                 dml_rq_regs->rq_regs_c.chunk_size, rq_regs.rq_regs_c.chunk_size);
0334     if (rq_regs.rq_regs_c.min_chunk_size != dml_rq_regs->rq_regs_c.min_chunk_size)
0335         DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_CHUNK_SIZE_C - Expected: %u  Actual: %u\n",
0336                 dml_rq_regs->rq_regs_c.min_chunk_size, rq_regs.rq_regs_c.min_chunk_size);
0337     if (rq_regs.rq_regs_c.meta_chunk_size != dml_rq_regs->rq_regs_c.meta_chunk_size)
0338         DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:META_CHUNK_SIZE_C - Expected: %u  Actual: %u\n",
0339                 dml_rq_regs->rq_regs_c.meta_chunk_size, rq_regs.rq_regs_c.meta_chunk_size);
0340     if (rq_regs.rq_regs_c.min_meta_chunk_size != dml_rq_regs->rq_regs_c.min_meta_chunk_size)
0341         DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_META_CHUNK_SIZE_C - Expected: %u  Actual: %u\n",
0342                 dml_rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs.rq_regs_c.min_meta_chunk_size);
0343     if (rq_regs.rq_regs_c.dpte_group_size != dml_rq_regs->rq_regs_c.dpte_group_size)
0344         DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:DPTE_GROUP_SIZE_C - Expected: %u  Actual: %u\n",
0345                 dml_rq_regs->rq_regs_c.dpte_group_size, rq_regs.rq_regs_c.dpte_group_size);
0346     if (rq_regs.rq_regs_c.swath_height != dml_rq_regs->rq_regs_c.swath_height)
0347         DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:SWATH_HEIGHT_C - Expected: %u  Actual: %u\n",
0348                 dml_rq_regs->rq_regs_c.swath_height, rq_regs.rq_regs_c.swath_height);
0349     if (rq_regs.rq_regs_c.pte_row_height_linear != dml_rq_regs->rq_regs_c.pte_row_height_linear)
0350         DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:PTE_ROW_HEIGHT_LINEAR_C - Expected: %u  Actual: %u\n",
0351                 dml_rq_regs->rq_regs_c.pte_row_height_linear, rq_regs.rq_regs_c.pte_row_height_linear);
0352
0353
0354     /* DLG - Per hubp */
0355     REG_GET_2(BLANK_OFFSET_0,
0356         REFCYC_H_BLANK_END, &dlg_attr.refcyc_h_blank_end,
0357         DLG_V_BLANK_END, &dlg_attr.dlg_vblank_end);
0358     REG_GET(BLANK_OFFSET_1,
0359         MIN_DST_Y_NEXT_START, &dlg_attr.min_dst_y_next_start);
0360     REG_GET(DST_DIMENSIONS,
0361         REFCYC_PER_HTOTAL, &dlg_attr.refcyc_per_htotal);
0362     REG_GET_2(DST_AFTER_SCALER,
0363         REFCYC_X_AFTER_SCALER, &dlg_attr.refcyc_x_after_scaler,
0364         DST_Y_AFTER_SCALER, &dlg_attr.dst_y_after_scaler);
0365     REG_GET(REF_FREQ_TO_PIX_FREQ,
0366         REF_FREQ_TO_PIX_FREQ, &dlg_attr.ref_freq_to_pix_freq);
0367
0368     if (dlg_attr.refcyc_h_blank_end != dml_dlg_attr->refcyc_h_blank_end)
0369         DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:REFCYC_H_BLANK_END - Expected: %u  Actual: %u\n",
0370                 dml_dlg_attr->refcyc_h_blank_end, dlg_attr.refcyc_h_blank_end);
0371     if (dlg_attr.dlg_vblank_end != dml_dlg_attr->dlg_vblank_end)
0372         DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:DLG_V_BLANK_END - Expected: %u  Actual: %u\n",
0373                 dml_dlg_attr->dlg_vblank_end, dlg_attr.dlg_vblank_end);
0374     if (dlg_attr.min_dst_y_next_start != dml_dlg_attr->min_dst_y_next_start)
0375         DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_1:MIN_DST_Y_NEXT_START - Expected: %u  Actual: %u\n",
0376                 dml_dlg_attr->min_dst_y_next_start, dlg_attr.min_dst_y_next_start);
0377     if (dlg_attr.refcyc_per_htotal != dml_dlg_attr->refcyc_per_htotal)
0378         DC_LOG_DEBUG("DML Validation | DST_DIMENSIONS:REFCYC_PER_HTOTAL - Expected: %u  Actual: %u\n",
0379                 dml_dlg_attr->refcyc_per_htotal, dlg_attr.refcyc_per_htotal);
0380     if (dlg_attr.refcyc_x_after_scaler != dml_dlg_attr->refcyc_x_after_scaler)
0381         DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:REFCYC_X_AFTER_SCALER - Expected: %u  Actual: %u\n",
0382                 dml_dlg_attr->refcyc_x_after_scaler, dlg_attr.refcyc_x_after_scaler);
0383     if (dlg_attr.dst_y_after_scaler != dml_dlg_attr->dst_y_after_scaler)
0384         DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:DST_Y_AFTER_SCALER - Expected: %u  Actual: %u\n",
0385                 dml_dlg_attr->dst_y_after_scaler, dlg_attr.dst_y_after_scaler);
0386     if (dlg_attr.ref_freq_to_pix_freq != dml_dlg_attr->ref_freq_to_pix_freq)
0387         DC_LOG_DEBUG("DML Validation | REF_FREQ_TO_PIX_FREQ:REF_FREQ_TO_PIX_FREQ - Expected: %u  Actual: %u\n",
0388                 dml_dlg_attr->ref_freq_to_pix_freq, dlg_attr.ref_freq_to_pix_freq);
0389
0390     /* DLG - Per luma/chroma */
0391     REG_GET(VBLANK_PARAMETERS_1,
0392         REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr.refcyc_per_pte_group_vblank_l);
0393     if (REG(NOM_PARAMETERS_0))
0394         REG_GET(NOM_PARAMETERS_0,
0395             DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr.dst_y_per_pte_row_nom_l);
0396     if (REG(NOM_PARAMETERS_1))
0397         REG_GET(NOM_PARAMETERS_1,
0398             REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr.refcyc_per_pte_group_nom_l);
0399     REG_GET(NOM_PARAMETERS_4,
0400         DST_Y_PER_META_ROW_NOM_L, &dlg_attr.dst_y_per_meta_row_nom_l);
0401     REG_GET(NOM_PARAMETERS_5,
0402         REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr.refcyc_per_meta_chunk_nom_l);
0403     REG_GET_2(PER_LINE_DELIVERY,
0404         REFCYC_PER_LINE_DELIVERY_L, &dlg_attr.refcyc_per_line_delivery_l,
0405         REFCYC_PER_LINE_DELIVERY_C, &dlg_attr.refcyc_per_line_delivery_c);
0406     REG_GET_2(PER_LINE_DELIVERY_PRE,
0407         REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr.refcyc_per_line_delivery_pre_l,
0408         REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr.refcyc_per_line_delivery_pre_c);
0409     REG_GET(VBLANK_PARAMETERS_2,
0410         REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr.refcyc_per_pte_group_vblank_c);
0411     if (REG(NOM_PARAMETERS_2))
0412         REG_GET(NOM_PARAMETERS_2,
0413             DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr.dst_y_per_pte_row_nom_c);
0414     if (REG(NOM_PARAMETERS_3))
0415         REG_GET(NOM_PARAMETERS_3,
0416             REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr.refcyc_per_pte_group_nom_c);
0417     REG_GET(NOM_PARAMETERS_6,
0418         DST_Y_PER_META_ROW_NOM_C, &dlg_attr.dst_y_per_meta_row_nom_c);
0419     REG_GET(NOM_PARAMETERS_7,
0420         REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr.refcyc_per_meta_chunk_nom_c);
0421     REG_GET(VBLANK_PARAMETERS_3,
0422             REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l);
0423     REG_GET(VBLANK_PARAMETERS_4,
0424             REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr.refcyc_per_meta_chunk_vblank_c);
0425
0426     if (dlg_attr.refcyc_per_pte_group_vblank_l != dml_dlg_attr->refcyc_per_pte_group_vblank_l)
0427         DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_1:REFCYC_PER_PTE_GROUP_VBLANK_L - Expected: %u  Actual: %u\n",
0428                 dml_dlg_attr->refcyc_per_pte_group_vblank_l, dlg_attr.refcyc_per_pte_group_vblank_l);
0429     if (dlg_attr.dst_y_per_pte_row_nom_l != dml_dlg_attr->dst_y_per_pte_row_nom_l)
0430         DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_0:DST_Y_PER_PTE_ROW_NOM_L - Expected: %u  Actual: %u\n",
0431                 dml_dlg_attr->dst_y_per_pte_row_nom_l, dlg_attr.dst_y_per_pte_row_nom_l);
0432     if (dlg_attr.refcyc_per_pte_group_nom_l != dml_dlg_attr->refcyc_per_pte_group_nom_l)
0433         DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_1:REFCYC_PER_PTE_GROUP_NOM_L - Expected: %u  Actual: %u\n",
0434                 dml_dlg_attr->refcyc_per_pte_group_nom_l, dlg_attr.refcyc_per_pte_group_nom_l);
0435     if (dlg_attr.dst_y_per_meta_row_nom_l != dml_dlg_attr->dst_y_per_meta_row_nom_l)
0436         DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_4:DST_Y_PER_META_ROW_NOM_L - Expected: %u  Actual: %u\n",
0437                 dml_dlg_attr->dst_y_per_meta_row_nom_l, dlg_attr.dst_y_per_meta_row_nom_l);
0438     if (dlg_attr.refcyc_per_meta_chunk_nom_l != dml_dlg_attr->refcyc_per_meta_chunk_nom_l)
0439         DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_5:REFCYC_PER_META_CHUNK_NOM_L - Expected: %u  Actual: %u\n",
0440                 dml_dlg_attr->refcyc_per_meta_chunk_nom_l, dlg_attr.refcyc_per_meta_chunk_nom_l);
0441     if (dlg_attr.refcyc_per_line_delivery_l != dml_dlg_attr->refcyc_per_line_delivery_l)
0442         DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_L - Expected: %u  Actual: %u\n",
0443                 dml_dlg_attr->refcyc_per_line_delivery_l, dlg_attr.refcyc_per_line_delivery_l);
0444     if (dlg_attr.refcyc_per_line_delivery_c != dml_dlg_attr->refcyc_per_line_delivery_c)
0445         DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_C - Expected: %u  Actual: %u\n",
0446                 dml_dlg_attr->refcyc_per_line_delivery_c, dlg_attr.refcyc_per_line_delivery_c);
0447     if (dlg_attr.refcyc_per_pte_group_vblank_c != dml_dlg_attr->refcyc_per_pte_group_vblank_c)
0448         DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_2:REFCYC_PER_PTE_GROUP_VBLANK_C - Expected: %u  Actual: %u\n",
0449                 dml_dlg_attr->refcyc_per_pte_group_vblank_c, dlg_attr.refcyc_per_pte_group_vblank_c);
0450     if (dlg_attr.dst_y_per_pte_row_nom_c != dml_dlg_attr->dst_y_per_pte_row_nom_c)
0451         DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_2:DST_Y_PER_PTE_ROW_NOM_C - Expected: %u  Actual: %u\n",
0452                 dml_dlg_attr->dst_y_per_pte_row_nom_c, dlg_attr.dst_y_per_pte_row_nom_c);
0453     if (dlg_attr.refcyc_per_pte_group_nom_c != dml_dlg_attr->refcyc_per_pte_group_nom_c)
0454         DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_3:REFCYC_PER_PTE_GROUP_NOM_C - Expected: %u  Actual: %u\n",
0455                 dml_dlg_attr->refcyc_per_pte_group_nom_c, dlg_attr.refcyc_per_pte_group_nom_c);
0456     if (dlg_attr.dst_y_per_meta_row_nom_c != dml_dlg_attr->dst_y_per_meta_row_nom_c)
0457         DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_6:DST_Y_PER_META_ROW_NOM_C - Expected: %u  Actual: %u\n",
0458                 dml_dlg_attr->dst_y_per_meta_row_nom_c, dlg_attr.dst_y_per_meta_row_nom_c);
0459     if (dlg_attr.refcyc_per_meta_chunk_nom_c != dml_dlg_attr->refcyc_per_meta_chunk_nom_c)
0460         DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_7:REFCYC_PER_META_CHUNK_NOM_C - Expected: %u  Actual: %u\n",
0461                 dml_dlg_attr->refcyc_per_meta_chunk_nom_c, dlg_attr.refcyc_per_meta_chunk_nom_c);
0462     if (dlg_attr.refcyc_per_line_delivery_pre_l != dml_dlg_attr->refcyc_per_line_delivery_pre_l)
0463         DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_L - Expected: %u  Actual: %u\n",
0464                 dml_dlg_attr->refcyc_per_line_delivery_pre_l, dlg_attr.refcyc_per_line_delivery_pre_l);
0465     if (dlg_attr.refcyc_per_line_delivery_pre_c != dml_dlg_attr->refcyc_per_line_delivery_pre_c)
0466         DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_C - Expected: %u  Actual: %u\n",
0467                 dml_dlg_attr->refcyc_per_line_delivery_pre_c, dlg_attr.refcyc_per_line_delivery_pre_c);
0468     if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l)
0469         DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_3:REFCYC_PER_META_CHUNK_VBLANK_L - Expected: %u  Actual: %u\n",
0470                 dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l);
0471     if (dlg_attr.refcyc_per_meta_chunk_vblank_c != dml_dlg_attr->refcyc_per_meta_chunk_vblank_c)
0472         DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_4:REFCYC_PER_META_CHUNK_VBLANK_C - Expected: %u  Actual: %u\n",
0473                 dml_dlg_attr->refcyc_per_meta_chunk_vblank_c, dlg_attr.refcyc_per_meta_chunk_vblank_c);
0474
0475     /* TTU - per hubp */
0476     REG_GET_2(DCN_TTU_QOS_WM,
0477         QoS_LEVEL_LOW_WM, &ttu_attr.qos_level_low_wm,
0478         QoS_LEVEL_HIGH_WM, &ttu_attr.qos_level_high_wm);
0479
0480     if (ttu_attr.qos_level_low_wm != dml_ttu_attr->qos_level_low_wm)
0481         DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_LOW_WM - Expected: %u  Actual: %u\n",
0482                 dml_ttu_attr->qos_level_low_wm, ttu_attr.qos_level_low_wm);
0483     if (ttu_attr.qos_level_high_wm != dml_ttu_attr->qos_level_high_wm)
0484         DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_HIGH_WM - Expected: %u  Actual: %u\n",
0485                 dml_ttu_attr->qos_level_high_wm, ttu_attr.qos_level_high_wm);
0486
0487     /* TTU - per luma/chroma */
0488     /* Assumed surf0 is luma and 1 is chroma */
0489     REG_GET_3(DCN_SURF0_TTU_CNTL0,
0490         REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_l,
0491         QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_l,
0492         QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_l);
0493     REG_GET_3(DCN_SURF1_TTU_CNTL0,
0494         REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_c,
0495         QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_c,
0496         QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_c);
0497     REG_GET_3(DCN_CUR0_TTU_CNTL0,
0498         REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_cur0,
0499         QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_cur0,
0500         QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_cur0);
0501     REG_GET(FLIP_PARAMETERS_1,
0502         REFCYC_PER_PTE_GROUP_FLIP_L, &dlg_attr.refcyc_per_pte_group_flip_l);
0503     REG_GET(DCN_CUR0_TTU_CNTL1,
0504             REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur0);
0505     REG_GET(DCN_CUR1_TTU_CNTL1,
0506             REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur1);
0507     REG_GET(DCN_SURF0_TTU_CNTL1,
0508             REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_l);
0509     REG_GET(DCN_SURF1_TTU_CNTL1,
0510             REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_c);
0511
0512     if (ttu_attr.refcyc_per_req_delivery_l != dml_ttu_attr->refcyc_per_req_delivery_l)
0513         DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u  Actual: %u\n",
0514                 dml_ttu_attr->refcyc_per_req_delivery_l, ttu_attr.refcyc_per_req_delivery_l);
0515     if (ttu_attr.qos_level_fixed_l != dml_ttu_attr->qos_level_fixed_l)
0516         DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u  Actual: %u\n",
0517                 dml_ttu_attr->qos_level_fixed_l, ttu_attr.qos_level_fixed_l);
0518     if (ttu_attr.qos_ramp_disable_l != dml_ttu_attr->qos_ramp_disable_l)
0519         DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u  Actual: %u\n",
0520                 dml_ttu_attr->qos_ramp_disable_l, ttu_attr.qos_ramp_disable_l);
0521     if (ttu_attr.refcyc_per_req_delivery_c != dml_ttu_attr->refcyc_per_req_delivery_c)
0522         DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u  Actual: %u\n",
0523                 dml_ttu_attr->refcyc_per_req_delivery_c, ttu_attr.refcyc_per_req_delivery_c);
0524     if (ttu_attr.qos_level_fixed_c != dml_ttu_attr->qos_level_fixed_c)
0525         DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u  Actual: %u\n",
0526                 dml_ttu_attr->qos_level_fixed_c, ttu_attr.qos_level_fixed_c);
0527     if (ttu_attr.qos_ramp_disable_c != dml_ttu_attr->qos_ramp_disable_c)
0528         DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u  Actual: %u\n",
0529                 dml_ttu_attr->qos_ramp_disable_c, ttu_attr.qos_ramp_disable_c);
0530     if (ttu_attr.refcyc_per_req_delivery_cur0 != dml_ttu_attr->refcyc_per_req_delivery_cur0)
0531         DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u  Actual: %u\n",
0532                 dml_ttu_attr->refcyc_per_req_delivery_cur0, ttu_attr.refcyc_per_req_delivery_cur0);
0533     if (ttu_attr.qos_level_fixed_cur0 != dml_ttu_attr->qos_level_fixed_cur0)
0534         DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u  Actual: %u\n",
0535                 dml_ttu_attr->qos_level_fixed_cur0, ttu_attr.qos_level_fixed_cur0);
0536     if (ttu_attr.qos_ramp_disable_cur0 != dml_ttu_attr->qos_ramp_disable_cur0)
0537         DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u  Actual: %u\n",
0538                 dml_ttu_attr->qos_ramp_disable_cur0, ttu_attr.qos_ramp_disable_cur0);
0539     if (dlg_attr.refcyc_per_pte_group_flip_l != dml_dlg_attr->refcyc_per_pte_group_flip_l)
0540         DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_1:REFCYC_PER_PTE_GROUP_FLIP_L - Expected: %u  Actual: %u\n",
0541                 dml_dlg_attr->refcyc_per_pte_group_flip_l, dlg_attr.refcyc_per_pte_group_flip_l);
0542     if (ttu_attr.refcyc_per_req_delivery_pre_cur0 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur0)
0543         DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u  Actual: %u\n",
0544                 dml_ttu_attr->refcyc_per_req_delivery_pre_cur0, ttu_attr.refcyc_per_req_delivery_pre_cur0);
0545     if (ttu_attr.refcyc_per_req_delivery_pre_cur1 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur1)
0546         DC_LOG_DEBUG("DML Validation | DCN_CUR1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u  Actual: %u\n",
0547                 dml_ttu_attr->refcyc_per_req_delivery_pre_cur1, ttu_attr.refcyc_per_req_delivery_pre_cur1);
0548     if (ttu_attr.refcyc_per_req_delivery_pre_l != dml_ttu_attr->refcyc_per_req_delivery_pre_l)
0549         DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u  Actual: %u\n",
0550                 dml_ttu_attr->refcyc_per_req_delivery_pre_l, ttu_attr.refcyc_per_req_delivery_pre_l);
0551     if (ttu_attr.refcyc_per_req_delivery_pre_c != dml_ttu_attr->refcyc_per_req_delivery_pre_c)
0552         DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u  Actual: %u\n",
0553                 dml_ttu_attr->refcyc_per_req_delivery_pre_c, ttu_attr.refcyc_per_req_delivery_pre_c);
0554
0555     /* Host VM deadline regs */
0556     REG_GET(VBLANK_PARAMETERS_5,
0557         REFCYC_PER_VM_GROUP_VBLANK, &dlg_attr.refcyc_per_vm_group_vblank);
0558     REG_GET(VBLANK_PARAMETERS_6,
0559         REFCYC_PER_VM_REQ_VBLANK, &dlg_attr.refcyc_per_vm_req_vblank);
0560     REG_GET(FLIP_PARAMETERS_3,
0561         REFCYC_PER_VM_GROUP_FLIP, &dlg_attr.refcyc_per_vm_group_flip);
0562     REG_GET(FLIP_PARAMETERS_4,
0563         REFCYC_PER_VM_REQ_FLIP, &dlg_attr.refcyc_per_vm_req_flip);
0564     REG_GET(FLIP_PARAMETERS_5,
0565         REFCYC_PER_PTE_GROUP_FLIP_C, &dlg_attr.refcyc_per_pte_group_flip_c);
0566     REG_GET(FLIP_PARAMETERS_6,
0567         REFCYC_PER_META_CHUNK_FLIP_C, &dlg_attr.refcyc_per_meta_chunk_flip_c);
0568     REG_GET(FLIP_PARAMETERS_2,
0569         REFCYC_PER_META_CHUNK_FLIP_L, &dlg_attr.refcyc_per_meta_chunk_flip_l);
0570
0571     if (dlg_attr.refcyc_per_vm_group_vblank != dml_dlg_attr->refcyc_per_vm_group_vblank)
0572         DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_5:REFCYC_PER_VM_GROUP_VBLANK - Expected: %u  Actual: %u\n",
0573                 dml_dlg_attr->refcyc_per_vm_group_vblank, dlg_attr.refcyc_per_vm_group_vblank);
0574     if (dlg_attr.refcyc_per_vm_req_vblank != dml_dlg_attr->refcyc_per_vm_req_vblank)
0575         DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_6:REFCYC_PER_VM_REQ_VBLANK - Expected: %u  Actual: %u\n",
0576                 dml_dlg_attr->refcyc_per_vm_req_vblank, dlg_attr.refcyc_per_vm_req_vblank);
0577     if (dlg_attr.refcyc_per_vm_group_flip != dml_dlg_attr->refcyc_per_vm_group_flip)
0578         DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_3:REFCYC_PER_VM_GROUP_FLIP - Expected: %u  Actual: %u\n",
0579                 dml_dlg_attr->refcyc_per_vm_group_flip, dlg_attr.refcyc_per_vm_group_flip);
0580     if (dlg_attr.refcyc_per_vm_req_flip != dml_dlg_attr->refcyc_per_vm_req_flip)
0581         DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_4:REFCYC_PER_VM_REQ_FLIP - Expected: %u  Actual: %u\n",
0582                 dml_dlg_attr->refcyc_per_vm_req_flip, dlg_attr.refcyc_per_vm_req_flip);
0583     if (dlg_attr.refcyc_per_pte_group_flip_c != dml_dlg_attr->refcyc_per_pte_group_flip_c)
0584         DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_5:REFCYC_PER_PTE_GROUP_FLIP_C - Expected: %u  Actual: %u\n",
0585                 dml_dlg_attr->refcyc_per_pte_group_flip_c, dlg_attr.refcyc_per_pte_group_flip_c);
0586     if (dlg_attr.refcyc_per_meta_chunk_flip_c != dml_dlg_attr->refcyc_per_meta_chunk_flip_c)
0587         DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_6:REFCYC_PER_META_CHUNK_FLIP_C - Expected: %u  Actual: %u\n",
0588                 dml_dlg_attr->refcyc_per_meta_chunk_flip_c, dlg_attr.refcyc_per_meta_chunk_flip_c);
0589     if (dlg_attr.refcyc_per_meta_chunk_flip_l != dml_dlg_attr->refcyc_per_meta_chunk_flip_l)
0590         DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_2:REFCYC_PER_META_CHUNK_FLIP_L - Expected: %u  Actual: %u\n",
0591                 dml_dlg_attr->refcyc_per_meta_chunk_flip_l, dlg_attr.refcyc_per_meta_chunk_flip_l);
0592 }
0593
0594 static void program_surface_flip_and_addr(struct hubp *hubp, struct surface_flip_registers *flip_regs)
0595 {
0596     struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
0597
0598     REG_UPDATE_3(DCSURF_FLIP_CONTROL,
0599                     SURFACE_FLIP_TYPE, flip_regs->immediate,
0600                     SURFACE_FLIP_MODE_FOR_STEREOSYNC, flip_regs->grph_stereo,
0601                     SURFACE_FLIP_IN_STEREOSYNC, flip_regs->grph_stereo);
0602
0603     REG_UPDATE(VMID_SETTINGS_0,
0604                 VMID, flip_regs->vmid);
0605
0606     REG_UPDATE_8(DCSURF_SURFACE_CONTROL,
0607             PRIMARY_SURFACE_TMZ, flip_regs->tmz_surface,
0608             PRIMARY_SURFACE_TMZ_C, flip_regs->tmz_surface,
0609             PRIMARY_META_SURFACE_TMZ, flip_regs->tmz_surface,
0610             PRIMARY_META_SURFACE_TMZ_C, flip_regs->tmz_surface,
0611             SECONDARY_SURFACE_TMZ, flip_regs->tmz_surface,
0612             SECONDARY_SURFACE_TMZ_C, flip_regs->tmz_surface,
0613             SECONDARY_META_SURFACE_TMZ, flip_regs->tmz_surface,
0614             SECONDARY_META_SURFACE_TMZ_C, flip_regs->tmz_surface);
0615
0616     REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
0617             PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
0618             flip_regs->DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C);
0619
0620     REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
0621             PRIMARY_META_SURFACE_ADDRESS_C,
0622             flip_regs->DCSURF_PRIMARY_META_SURFACE_ADDRESS_C);
0623
0624     REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
0625             PRIMARY_META_SURFACE_ADDRESS_HIGH,
0626             flip_regs->DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH);
0627
0628     REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
0629             PRIMARY_META_SURFACE_ADDRESS,
0630             flip_regs->DCSURF_PRIMARY_META_SURFACE_ADDRESS);
0631
0632     REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0,
0633             SECONDARY_META_SURFACE_ADDRESS_HIGH,
0634             flip_regs->DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH);
0635
0636     REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0,
0637             SECONDARY_META_SURFACE_ADDRESS,
0638             flip_regs->DCSURF_SECONDARY_META_SURFACE_ADDRESS);
0639
0640
0641     REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0,
0642             SECONDARY_SURFACE_ADDRESS_HIGH,
0643             flip_regs->DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH);
0644
0645     REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0,
0646             SECONDARY_SURFACE_ADDRESS,
0647             flip_regs->DCSURF_SECONDARY_SURFACE_ADDRESS);
0648
0649
0650     REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
0651             PRIMARY_SURFACE_ADDRESS_HIGH_C,
0652             flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C);
0653
0654     REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
0655             PRIMARY_SURFACE_ADDRESS_C,
0656             flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_C);
0657
0658     REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
0659             PRIMARY_SURFACE_ADDRESS_HIGH,
0660             flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH);
0661
0662     REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
0663             PRIMARY_SURFACE_ADDRESS,
0664             flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS);
0665 }
0666
0667 static void dmcub_PLAT_54186_wa(struct hubp *hubp,
0668                 struct surface_flip_registers *flip_regs)
0669 {
0670     struct dc_dmub_srv *dmcub = hubp->ctx->dmub_srv;
0671     struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
0672     union dmub_rb_cmd cmd;
0673
0674     memset(&cmd, 0, sizeof(cmd));
0675
0676     cmd.PLAT_54186_wa.header.type = DMUB_CMD__PLAT_54186_WA;
0677     cmd.PLAT_54186_wa.header.payload_bytes = sizeof(cmd.PLAT_54186_wa.flip);
0678     cmd.PLAT_54186_wa.flip.DCSURF_PRIMARY_SURFACE_ADDRESS =
0679         flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS;
0680     cmd.PLAT_54186_wa.flip.DCSURF_PRIMARY_SURFACE_ADDRESS_C =
0681         flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_C;
0682     cmd.PLAT_54186_wa.flip.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH =
0683         flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH;
0684     cmd.PLAT_54186_wa.flip.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C =
0685         flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C;
0686     cmd.PLAT_54186_wa.flip.flip_params.grph_stereo = flip_regs->grph_stereo;
0687     cmd.PLAT_54186_wa.flip.flip_params.hubp_inst = hubp->inst;
0688     cmd.PLAT_54186_wa.flip.flip_params.immediate = flip_regs->immediate;
0689     cmd.PLAT_54186_wa.flip.flip_params.tmz_surface = flip_regs->tmz_surface;
0690     cmd.PLAT_54186_wa.flip.flip_params.vmid = flip_regs->vmid;
0691
0692     PERF_TRACE();  // TODO: remove after performance is stable.
0693     dc_dmub_srv_cmd_queue(dmcub, &cmd);
0694     PERF_TRACE();  // TODO: remove after performance is stable.
0695     dc_dmub_srv_cmd_execute(dmcub);
0696     PERF_TRACE();  // TODO: remove after performance is stable.
0697     dc_dmub_srv_wait_idle(dmcub);
0698     PERF_TRACE();  // TODO: remove after performance is stable.
0699 }
0700
0701 static bool hubp21_program_surface_flip_and_addr(
0702         struct hubp *hubp,
0703         const struct dc_plane_address *address,
0704         bool flip_immediate)
0705 {
0706     struct surface_flip_registers flip_regs = { 0 };
0707
0708     flip_regs.vmid = address->vmid;
0709
0710     switch (address->type) {
0711     case PLN_ADDR_TYPE_GRAPHICS:
0712         if (address->grph.addr.quad_part == 0) {
0713             BREAK_TO_DEBUGGER();
0714             break;
0715         }
0716
0717         if (address->grph.meta_addr.quad_part != 0) {
0718             flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS =
0719                     address->grph.meta_addr.low_part;
0720             flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH =
0721                     address->grph.meta_addr.high_part;
0722         }
0723
0724         flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS =
0725                 address->grph.addr.low_part;
0726         flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH =
0727                 address->grph.addr.high_part;
0728         break;
0729     case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
0730         if (address->video_progressive.luma_addr.quad_part == 0
0731                 || address->video_progressive.chroma_addr.quad_part == 0)
0732             break;
0733
0734         if (address->video_progressive.luma_meta_addr.quad_part != 0) {
0735             flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS =
0736                     address->video_progressive.luma_meta_addr.low_part;
0737             flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH =
0738                     address->video_progressive.luma_meta_addr.high_part;
0739
0740             flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_C =
0741                     address->video_progressive.chroma_meta_addr.low_part;
0742             flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C =
0743                     address->video_progressive.chroma_meta_addr.high_part;
0744         }
0745
0746         flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS =
0747                 address->video_progressive.luma_addr.low_part;
0748         flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH =
0749                 address->video_progressive.luma_addr.high_part;
0750
0751         flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_C =
0752                 address->video_progressive.chroma_addr.low_part;
0753
0754         flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C =
0755                 address->video_progressive.chroma_addr.high_part;
0756
0757         break;
0758     case PLN_ADDR_TYPE_GRPH_STEREO:
0759         if (address->grph_stereo.left_addr.quad_part == 0)
0760             break;
0761         if (address->grph_stereo.right_addr.quad_part == 0)
0762             break;
0763
0764         flip_regs.grph_stereo = true;
0765
0766         if (address->grph_stereo.right_meta_addr.quad_part != 0) {
0767             flip_regs.DCSURF_SECONDARY_META_SURFACE_ADDRESS =
0768                     address->grph_stereo.right_meta_addr.low_part;
0769             flip_regs.DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH =
0770                     address->grph_stereo.right_meta_addr.high_part;
0771         }
0772
0773         if (address->grph_stereo.left_meta_addr.quad_part != 0) {
0774             flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS =
0775                     address->grph_stereo.left_meta_addr.low_part;
0776             flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH =
0777                     address->grph_stereo.left_meta_addr.high_part;
0778         }
0779
0780         flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS =
0781                 address->grph_stereo.left_addr.low_part;
0782         flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH =
0783                 address->grph_stereo.left_addr.high_part;
0784
0785         flip_regs.DCSURF_SECONDARY_SURFACE_ADDRESS =
0786                 address->grph_stereo.right_addr.low_part;
0787         flip_regs.DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH =
0788                 address->grph_stereo.right_addr.high_part;
0789
0790         break;
0791     default:
0792         BREAK_TO_DEBUGGER();
0793         break;
0794     }
0795
0796     flip_regs.tmz_surface = address->tmz_surface;
0797     flip_regs.immediate = flip_immediate;
0798
0799     if (hubp->ctx->dc->debug.enable_dmcub_surface_flip && address->type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
0800         dmcub_PLAT_54186_wa(hubp, &flip_regs);
0801     else
0802         program_surface_flip_and_addr(hubp, &flip_regs);
0803
0804     hubp->request_address = *address;
0805
0806     return true;
0807 }
0808
0809 static void hubp21_init(struct hubp *hubp)
0810 {
0811     // DEDCN21-133: Inconsistent row starting line for flip between DPTE and Meta
0812     // This is a chicken bit to enable the ECO fix.
0813
0814     struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
0815     //hubp[i].HUBPREQ_DEBUG.HUBPREQ_DEBUG[26] = 1;
0816     REG_WRITE(HUBPREQ_DEBUG, 1 << 26);
0817 }
0818 static struct hubp_funcs dcn21_hubp_funcs = {
0819     .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
0820     .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
0821     .hubp_program_surface_flip_and_addr = hubp21_program_surface_flip_and_addr,
0822     .hubp_program_surface_config = hubp1_program_surface_config,
0823     .hubp_is_flip_pending = hubp1_is_flip_pending,
0824     .hubp_setup = hubp21_setup,
0825     .hubp_setup_interdependent = hubp2_setup_interdependent,
0826     .hubp_set_vm_system_aperture_settings = hubp21_set_vm_system_aperture_settings,
0827     .set_blank = hubp1_set_blank,
0828     .dcc_control = hubp1_dcc_control,
0829     .mem_program_viewport = hubp21_set_viewport,
0830     .set_cursor_attributes  = hubp2_cursor_set_attributes,
0831     .set_cursor_position    = hubp1_cursor_set_position,
0832     .hubp_clk_cntl = hubp1_clk_cntl,
0833     .hubp_vtg_sel = hubp1_vtg_sel,
0834     .dmdata_set_attributes = hubp2_dmdata_set_attributes,
0835     .dmdata_load = hubp2_dmdata_load,
0836     .dmdata_status_done = hubp2_dmdata_status_done,
0837     .hubp_read_state = hubp2_read_state,
0838     .hubp_clear_underflow = hubp1_clear_underflow,
0839     .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
0840     .hubp_init = hubp21_init,
0841     .validate_dml_output = hubp21_validate_dml_output,
0842     .hubp_set_flip_int = hubp1_set_flip_int,
0843 };
0844
0845 bool hubp21_construct(
0846     struct dcn21_hubp *hubp21,
0847     struct dc_context *ctx,
0848     uint32_t inst,
0849     const struct dcn_hubp2_registers *hubp_regs,
0850     const struct dcn_hubp2_shift *hubp_shift,
0851     const struct dcn_hubp2_mask *hubp_mask)
0852 {
0853     hubp21->base.funcs = &dcn21_hubp_funcs;
0854     hubp21->base.ctx = ctx;
0855     hubp21->hubp_regs = hubp_regs;
0856     hubp21->hubp_shift = hubp_shift;
0857     hubp21->hubp_mask = hubp_mask;
0858     hubp21->base.inst = inst;
0859     hubp21->base.opp_id = OPP_ID_INVALID;
0860     hubp21->base.mpcc_id = 0xf;
0861
0862     return true;
0863 }