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0001 /*
0002 * Copyright 2016 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 
0026 #include "dm_services.h"
0027 #include "dc.h"
0028 
0029 #include "dcn201_init.h"
0030 #include "dml/dcn20/dcn20_fpu.h"
0031 #include "resource.h"
0032 #include "include/irq_service_interface.h"
0033 #include "dcn201_resource.h"
0034 
0035 #include "dcn20/dcn20_resource.h"
0036 
0037 #include "dcn10/dcn10_hubp.h"
0038 #include "dcn10/dcn10_ipp.h"
0039 #include "dcn201_mpc.h"
0040 #include "dcn201_hubp.h"
0041 #include "irq/dcn201/irq_service_dcn201.h"
0042 #include "dcn201/dcn201_dpp.h"
0043 #include "dcn201/dcn201_hubbub.h"
0044 #include "dcn201_dccg.h"
0045 #include "dcn201_optc.h"
0046 #include "dcn201_hwseq.h"
0047 #include "dce110/dce110_hw_sequencer.h"
0048 #include "dcn201_opp.h"
0049 #include "dcn201/dcn201_link_encoder.h"
0050 #include "dcn20/dcn20_stream_encoder.h"
0051 #include "dce/dce_clock_source.h"
0052 #include "dce/dce_audio.h"
0053 #include "dce/dce_hwseq.h"
0054 #include "virtual/virtual_stream_encoder.h"
0055 #include "dce110/dce110_resource.h"
0056 #include "dce/dce_aux.h"
0057 #include "dce/dce_i2c.h"
0058 #include "dcn201_hubbub.h"
0059 #include "dcn10/dcn10_resource.h"
0060 
0061 #include "cyan_skillfish_ip_offset.h"
0062 
0063 #include "dcn/dcn_2_0_3_offset.h"
0064 #include "dcn/dcn_2_0_3_sh_mask.h"
0065 #include "dpcs/dpcs_2_0_3_offset.h"
0066 #include "dpcs/dpcs_2_0_3_sh_mask.h"
0067 
0068 #include "mmhub/mmhub_2_0_0_offset.h"
0069 #include "mmhub/mmhub_2_0_0_sh_mask.h"
0070 #include "nbio/nbio_7_4_offset.h"
0071 
0072 #include "reg_helper.h"
0073 
0074 #define MIN_DISP_CLK_KHZ 100000
0075 #define MIN_DPP_CLK_KHZ 100000
0076 
0077 struct _vcs_dpi_ip_params_st dcn201_ip = {
0078     .gpuvm_enable = 0,
0079     .hostvm_enable = 0,
0080     .gpuvm_max_page_table_levels = 4,
0081     .hostvm_max_page_table_levels = 4,
0082     .hostvm_cached_page_table_levels = 0,
0083     .pte_group_size_bytes = 2048,
0084     .rob_buffer_size_kbytes = 168,
0085     .det_buffer_size_kbytes = 164,
0086     .dpte_buffer_size_in_pte_reqs_luma = 84,
0087     .pde_proc_buffer_size_64k_reqs = 48,
0088     .dpp_output_buffer_pixels = 2560,
0089     .opp_output_buffer_lines = 1,
0090     .pixel_chunk_size_kbytes = 8,
0091     .pte_chunk_size_kbytes = 2,
0092     .meta_chunk_size_kbytes = 2,
0093     .writeback_chunk_size_kbytes = 2,
0094     .line_buffer_size_bits = 789504,
0095     .is_line_buffer_bpp_fixed = 0,
0096     .line_buffer_fixed_bpp = 0,
0097     .dcc_supported = true,
0098     .max_line_buffer_lines = 12,
0099     .writeback_luma_buffer_size_kbytes = 12,
0100     .writeback_chroma_buffer_size_kbytes = 8,
0101     .writeback_chroma_line_buffer_width_pixels = 4,
0102     .writeback_max_hscl_ratio = 1,
0103     .writeback_max_vscl_ratio = 1,
0104     .writeback_min_hscl_ratio = 1,
0105     .writeback_min_vscl_ratio = 1,
0106     .writeback_max_hscl_taps = 12,
0107     .writeback_max_vscl_taps = 12,
0108     .writeback_line_buffer_luma_buffer_size = 0,
0109     .writeback_line_buffer_chroma_buffer_size = 9600,
0110     .cursor_buffer_size = 8,
0111     .cursor_chunk_size = 2,
0112     .max_num_otg = 2,
0113     .max_num_dpp = 4,
0114     .max_num_wb = 0,
0115     .max_dchub_pscl_bw_pix_per_clk = 4,
0116     .max_pscl_lb_bw_pix_per_clk = 2,
0117     .max_lb_vscl_bw_pix_per_clk = 4,
0118     .max_vscl_hscl_bw_pix_per_clk = 4,
0119     .max_hscl_ratio = 8,
0120     .max_vscl_ratio = 8,
0121     .hscl_mults = 4,
0122     .vscl_mults = 4,
0123     .max_hscl_taps = 8,
0124     .max_vscl_taps = 8,
0125     .dispclk_ramp_margin_percent = 1,
0126     .underscan_factor = 1.10,
0127     .min_vblank_lines = 30,
0128     .dppclk_delay_subtotal = 77,
0129     .dppclk_delay_scl_lb_only = 16,
0130     .dppclk_delay_scl = 50,
0131     .dppclk_delay_cnvc_formatter = 8,
0132     .dppclk_delay_cnvc_cursor = 6,
0133     .dispclk_delay_subtotal = 87,
0134     .dcfclk_cstate_latency = 10,
0135     .max_inter_dcn_tile_repeaters = 8,
0136     .number_of_cursors = 1,
0137 };
0138 
0139 struct _vcs_dpi_soc_bounding_box_st dcn201_soc = {
0140     .clock_limits = {
0141             {
0142                 .state = 0,
0143                 .dscclk_mhz = 400.0,
0144                 .dcfclk_mhz = 1000.0,
0145                 .fabricclk_mhz = 200.0,
0146                 .dispclk_mhz = 300.0,
0147                 .dppclk_mhz = 300.0,
0148                 .phyclk_mhz = 810.0,
0149                 .socclk_mhz = 1254.0,
0150                 .dram_speed_mts = 2000.0,
0151             },
0152             {
0153                 .state = 1,
0154                 .dscclk_mhz = 400.0,
0155                 .dcfclk_mhz = 1000.0,
0156                 .fabricclk_mhz = 250.0,
0157                 .dispclk_mhz = 1200.0,
0158                 .dppclk_mhz = 1200.0,
0159                 .phyclk_mhz = 810.0,
0160                 .socclk_mhz = 1254.0,
0161                 .dram_speed_mts = 3600.0,
0162             },
0163             {
0164                 .state = 2,
0165                 .dscclk_mhz = 400.0,
0166                 .dcfclk_mhz = 1000.0,
0167                 .fabricclk_mhz = 750.0,
0168                 .dispclk_mhz = 1200.0,
0169                 .dppclk_mhz = 1200.0,
0170                 .phyclk_mhz = 810.0,
0171                 .socclk_mhz = 1254.0,
0172                 .dram_speed_mts = 6800.0,
0173             },
0174             {
0175                 .state = 3,
0176                 .dscclk_mhz = 400.0,
0177                 .dcfclk_mhz = 1000.0,
0178                 .fabricclk_mhz = 250.0,
0179                 .dispclk_mhz = 1200.0,
0180                 .dppclk_mhz = 1200.0,
0181                 .phyclk_mhz = 810.0,
0182                 .socclk_mhz = 1254.0,
0183                 .dram_speed_mts = 14000.0,
0184             },
0185             {
0186                 .state = 4,
0187                 .dscclk_mhz = 400.0,
0188                 .dcfclk_mhz = 1000.0,
0189                 .fabricclk_mhz = 750.0,
0190                 .dispclk_mhz = 1200.0,
0191                 .dppclk_mhz = 1200.0,
0192                 .phyclk_mhz = 810.0,
0193                 .socclk_mhz = 1254.0,
0194                 .dram_speed_mts = 14000.0,
0195             }
0196         },
0197     .num_states = 4,
0198     .sr_exit_time_us = 9.0,
0199     .sr_enter_plus_exit_time_us = 11.0,
0200     .urgent_latency_us = 4.0,
0201     .urgent_latency_pixel_data_only_us = 4.0,
0202     .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
0203     .urgent_latency_vm_data_only_us = 4.0,
0204     .urgent_out_of_order_return_per_channel_pixel_only_bytes = 256,
0205     .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 256,
0206     .urgent_out_of_order_return_per_channel_vm_only_bytes = 256,
0207     .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
0208     .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 80.0,
0209     .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 80.0,
0210     .max_avg_sdp_bw_use_normal_percent = 80.0,
0211     .max_avg_dram_bw_use_normal_percent = 69.0,
0212     .writeback_latency_us = 12.0,
0213     .ideal_dram_bw_after_urgent_percent = 80.0,
0214     .max_request_size_bytes = 256,
0215     .dram_channel_width_bytes = 2,
0216     .fabric_datapath_to_dcn_data_return_bytes = 64,
0217     .dcn_downspread_percent = 0.3,
0218     .downspread_percent = 0.3,
0219     .dram_page_open_time_ns = 50.0,
0220     .dram_rw_turnaround_time_ns = 17.5,
0221     .dram_return_buffer_per_channel_bytes = 8192,
0222     .round_trip_ping_latency_dcfclk_cycles = 128,
0223     .urgent_out_of_order_return_per_channel_bytes = 256,
0224     .channel_interleave_bytes = 256,
0225     .num_banks = 8,
0226     .num_chans = 16,
0227     .vmm_page_size_bytes = 4096,
0228     .dram_clock_change_latency_us = 250.0,
0229     .writeback_dram_clock_change_latency_us = 23.0,
0230     .return_bus_width_bytes = 64,
0231     .dispclk_dppclk_vco_speed_mhz = 3000,
0232     .use_urgent_burst_bw = 0,
0233 };
0234 
0235 enum dcn20_clk_src_array_id {
0236     DCN20_CLK_SRC_PLL0,
0237     DCN20_CLK_SRC_PLL1,
0238     DCN20_CLK_SRC_TOTAL_DCN201
0239 };
0240 
0241 /* begin *********************
0242  * macros to expend register list macro defined in HW object header file */
0243 
0244 /* DCN */
0245 
0246 #undef BASE_INNER
0247 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
0248 
0249 #define BASE(seg) BASE_INNER(seg)
0250 
0251 #define SR(reg_name)\
0252         .reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
0253                     mm ## reg_name
0254 
0255 #define SRI(reg_name, block, id)\
0256     .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0257                     mm ## block ## id ## _ ## reg_name
0258 
0259 #define SRIR(var_name, reg_name, block, id)\
0260     .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0261                     mm ## block ## id ## _ ## reg_name
0262 
0263 #define SRII(reg_name, block, id)\
0264     .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0265                     mm ## block ## id ## _ ## reg_name
0266 
0267 #define SRI_IX(reg_name, block, id)\
0268     .reg_name = ix ## block ## id ## _ ## reg_name
0269 
0270 #define DCCG_SRII(reg_name, block, id)\
0271     .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0272                     mm ## block ## id ## _ ## reg_name
0273 
0274 #define VUPDATE_SRII(reg_name, block, id)\
0275     .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
0276                     mm ## reg_name ## _ ## block ## id
0277 
0278 /* NBIO */
0279 #define NBIO_BASE_INNER(seg) \
0280     NBIO_BASE__INST0_SEG ## seg
0281 
0282 #define NBIO_BASE(seg) \
0283     NBIO_BASE_INNER(seg)
0284 
0285 #define NBIO_SR(reg_name)\
0286         .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
0287                     mm ## reg_name
0288 
0289 /* MMHUB */
0290 #define MMHUB_BASE_INNER(seg) \
0291     MMHUB_BASE__INST0_SEG ## seg
0292 
0293 #define MMHUB_BASE(seg) \
0294     MMHUB_BASE_INNER(seg)
0295 
0296 #define MMHUB_SR(reg_name)\
0297         .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
0298                     mmMM ## reg_name
0299 
0300 static const struct bios_registers bios_regs = {
0301         NBIO_SR(BIOS_SCRATCH_3),
0302         NBIO_SR(BIOS_SCRATCH_6)
0303 };
0304 
0305 #define clk_src_regs(index, pllid)\
0306 [index] = {\
0307     CS_COMMON_REG_LIST_DCN201(index, pllid),\
0308 }
0309 
0310 static const struct dce110_clk_src_regs clk_src_regs[] = {
0311     clk_src_regs(0, A),
0312     clk_src_regs(1, B)
0313 };
0314 
0315 static const struct dce110_clk_src_shift cs_shift = {
0316         CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
0317 };
0318 
0319 static const struct dce110_clk_src_mask cs_mask = {
0320         CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
0321 };
0322 
0323 #define audio_regs(id)\
0324 [id] = {\
0325         AUD_COMMON_REG_LIST(id)\
0326 }
0327 
0328 static const struct dce_audio_registers audio_regs[] = {
0329     audio_regs(0),
0330     audio_regs(1),
0331 };
0332 
0333 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
0334         SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
0335         SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
0336         AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
0337 
0338 static const struct dce_audio_shift audio_shift = {
0339         DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
0340 };
0341 
0342 static const struct dce_audio_mask audio_mask = {
0343         DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
0344 };
0345 
0346 #define stream_enc_regs(id)\
0347 [id] = {\
0348     SE_DCN2_REG_LIST(id)\
0349 }
0350 
0351 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
0352     stream_enc_regs(0),
0353     stream_enc_regs(1)
0354 };
0355 
0356 static const struct dcn10_stream_encoder_shift se_shift = {
0357         SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
0358 };
0359 
0360 static const struct dcn10_stream_encoder_mask se_mask = {
0361         SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
0362 };
0363 
0364 static const struct dce110_aux_registers_shift aux_shift = {
0365     DCN_AUX_MASK_SH_LIST(__SHIFT)
0366 };
0367 
0368 static const struct dce110_aux_registers_mask aux_mask = {
0369     DCN_AUX_MASK_SH_LIST(_MASK)
0370 };
0371 
0372 #define aux_regs(id)\
0373 [id] = {\
0374     DCN2_AUX_REG_LIST(id)\
0375 }
0376 
0377 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
0378         aux_regs(0),
0379         aux_regs(1),
0380 };
0381 
0382 #define hpd_regs(id)\
0383 [id] = {\
0384     HPD_REG_LIST(id)\
0385 }
0386 
0387 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
0388         hpd_regs(0),
0389         hpd_regs(1),
0390 };
0391 
0392 #define link_regs(id, phyid)\
0393 [id] = {\
0394     LE_DCN_COMMON_REG_LIST(id), \
0395     UNIPHY_DCN2_REG_LIST(phyid) \
0396 }
0397 
0398 static const struct dcn10_link_enc_registers link_enc_regs[] = {
0399     link_regs(0, A),
0400     link_regs(1, B),
0401 };
0402 
0403 #define LINK_ENCODER_MASK_SH_LIST_DCN201(mask_sh)\
0404     LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh)
0405 
0406 static const struct dcn10_link_enc_shift le_shift = {
0407         LINK_ENCODER_MASK_SH_LIST_DCN201(__SHIFT)
0408 };
0409 
0410 static const struct dcn10_link_enc_mask le_mask = {
0411         LINK_ENCODER_MASK_SH_LIST_DCN201(_MASK)
0412 };
0413 
0414 #define ipp_regs(id)\
0415 [id] = {\
0416         IPP_REG_LIST_DCN201(id),\
0417 }
0418 
0419 static const struct dcn10_ipp_registers ipp_regs[] = {
0420     ipp_regs(0),
0421     ipp_regs(1),
0422     ipp_regs(2),
0423     ipp_regs(3),
0424 };
0425 
0426 static const struct dcn10_ipp_shift ipp_shift = {
0427         IPP_MASK_SH_LIST_DCN201(__SHIFT)
0428 };
0429 
0430 static const struct dcn10_ipp_mask ipp_mask = {
0431         IPP_MASK_SH_LIST_DCN201(_MASK)
0432 };
0433 
0434 #define opp_regs(id)\
0435 [id] = {\
0436     OPP_REG_LIST_DCN201(id),\
0437 }
0438 
0439 static const struct dcn201_opp_registers opp_regs[] = {
0440     opp_regs(0),
0441     opp_regs(1),
0442 };
0443 
0444 static const struct dcn201_opp_shift opp_shift = {
0445         OPP_MASK_SH_LIST_DCN201(__SHIFT)
0446 };
0447 
0448 static const struct dcn201_opp_mask opp_mask = {
0449         OPP_MASK_SH_LIST_DCN201(_MASK)
0450 };
0451 
0452 #define aux_engine_regs(id)\
0453 [id] = {\
0454     AUX_COMMON_REG_LIST0(id), \
0455     .AUX_RESET_MASK = 0 \
0456 }
0457 
0458 static const struct dce110_aux_registers aux_engine_regs[] = {
0459         aux_engine_regs(0),
0460         aux_engine_regs(1)
0461 };
0462 
0463 #define tf_regs(id)\
0464 [id] = {\
0465     TF_REG_LIST_DCN201(id),\
0466 }
0467 
0468 static const struct dcn201_dpp_registers tf_regs[] = {
0469     tf_regs(0),
0470     tf_regs(1),
0471     tf_regs(2),
0472     tf_regs(3),
0473 };
0474 
0475 static const struct dcn201_dpp_shift tf_shift = {
0476         TF_REG_LIST_SH_MASK_DCN201(__SHIFT)
0477 };
0478 
0479 static const struct dcn201_dpp_mask tf_mask = {
0480         TF_REG_LIST_SH_MASK_DCN201(_MASK)
0481 };
0482 
0483 static const struct dcn201_mpc_registers mpc_regs = {
0484         MPC_REG_LIST_DCN201(0),
0485         MPC_REG_LIST_DCN201(1),
0486         MPC_REG_LIST_DCN201(2),
0487         MPC_REG_LIST_DCN201(3),
0488         MPC_REG_LIST_DCN201(4),
0489         MPC_OUT_MUX_REG_LIST_DCN201(0),
0490         MPC_OUT_MUX_REG_LIST_DCN201(1),
0491 };
0492 
0493 static const struct dcn201_mpc_shift mpc_shift = {
0494     MPC_COMMON_MASK_SH_LIST_DCN201(__SHIFT)
0495 };
0496 
0497 static const struct dcn201_mpc_mask mpc_mask = {
0498     MPC_COMMON_MASK_SH_LIST_DCN201(_MASK)
0499 };
0500 
0501 #define tg_regs_dcn201(id)\
0502 [id] = {TG_COMMON_REG_LIST_DCN201(id)}
0503 
0504 static const struct dcn_optc_registers tg_regs[] = {
0505     tg_regs_dcn201(0),
0506     tg_regs_dcn201(1)
0507 };
0508 
0509 static const struct dcn_optc_shift tg_shift = {
0510     TG_COMMON_MASK_SH_LIST_DCN201(__SHIFT)
0511 };
0512 
0513 static const struct dcn_optc_mask tg_mask = {
0514     TG_COMMON_MASK_SH_LIST_DCN201(_MASK)
0515 };
0516 
0517 #define hubp_regsDCN201(id)\
0518 [id] = {\
0519     HUBP_REG_LIST_DCN201(id)\
0520 }
0521 
0522 static const struct dcn201_hubp_registers hubp_regs[] = {
0523         hubp_regsDCN201(0),
0524         hubp_regsDCN201(1),
0525         hubp_regsDCN201(2),
0526         hubp_regsDCN201(3)
0527 };
0528 
0529 static const struct dcn201_hubp_shift hubp_shift = {
0530         HUBP_MASK_SH_LIST_DCN201(__SHIFT)
0531 };
0532 
0533 static const struct dcn201_hubp_mask hubp_mask = {
0534         HUBP_MASK_SH_LIST_DCN201(_MASK)
0535 };
0536 
0537 static const struct dcn_hubbub_registers hubbub_reg = {
0538         HUBBUB_REG_LIST_DCN201(0)
0539 };
0540 
0541 static const struct dcn_hubbub_shift hubbub_shift = {
0542         HUBBUB_MASK_SH_LIST_DCN201(__SHIFT)
0543 };
0544 
0545 static const struct dcn_hubbub_mask hubbub_mask = {
0546         HUBBUB_MASK_SH_LIST_DCN201(_MASK)
0547 };
0548 
0549 
0550 static const struct dccg_registers dccg_regs = {
0551         DCCG_COMMON_REG_LIST_DCN_BASE()
0552 };
0553 
0554 static const struct dccg_shift dccg_shift = {
0555         DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(__SHIFT)
0556 };
0557 
0558 static const struct dccg_mask dccg_mask = {
0559         DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(_MASK)
0560 };
0561 
0562 static const struct resource_caps res_cap_dnc201 = {
0563         .num_timing_generator = 2,
0564         .num_opp = 2,
0565         .num_video_plane = 4,
0566         .num_audio = 2,
0567         .num_stream_encoder = 2,
0568         .num_pll = 2,
0569         .num_ddc = 2,
0570 };
0571 
0572 static const struct dc_plane_cap plane_cap = {
0573     .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
0574     .blends_with_above = true,
0575     .blends_with_below = true,
0576     .per_pixel_alpha = true,
0577 
0578     .pixel_format_support = {
0579             .argb8888 = true,
0580             .nv12 = false,
0581             .fp16 = true,
0582             .p010 = false,
0583     },
0584 
0585     .max_upscale_factor = {
0586             .argb8888 = 16000,
0587             .nv12 = 16000,
0588             .fp16 = 1
0589     },
0590 
0591     .max_downscale_factor = {
0592             .argb8888 = 250,
0593             .nv12 = 250,
0594             .fp16 = 250
0595     },
0596     64,
0597     64
0598 };
0599 
0600 static const struct dc_debug_options debug_defaults_drv = {
0601         .disable_dmcu = true,
0602         .force_abm_enable = false,
0603         .timing_trace = false,
0604         .clock_trace = true,
0605         .disable_pplib_clock_request = true,
0606         .pipe_split_policy = MPC_SPLIT_DYNAMIC,
0607         .force_single_disp_pipe_split = false,
0608         .disable_dcc = DCC_ENABLE,
0609         .vsr_support = true,
0610         .performance_trace = false,
0611         .az_endpoint_mute_only = true,
0612         .max_downscale_src_width = 3840,
0613         .disable_pplib_wm_range = true,
0614         .scl_reset_length10 = true,
0615         .sanity_checks = false,
0616         .underflow_assert_delay_us = 0xFFFFFFFF,
0617         .enable_tri_buf = false,
0618 };
0619 
0620 static void dcn201_dpp_destroy(struct dpp **dpp)
0621 {
0622     kfree(TO_DCN201_DPP(*dpp));
0623     *dpp = NULL;
0624 }
0625 
0626 static struct dpp *dcn201_dpp_create(
0627     struct dc_context *ctx,
0628     uint32_t inst)
0629 {
0630     struct dcn201_dpp *dpp =
0631         kzalloc(sizeof(struct dcn201_dpp), GFP_ATOMIC);
0632 
0633     if (!dpp)
0634         return NULL;
0635 
0636     if (dpp201_construct(dpp, ctx, inst,
0637             &tf_regs[inst], &tf_shift, &tf_mask))
0638         return &dpp->base;
0639 
0640     kfree(dpp);
0641     return NULL;
0642 }
0643 
0644 static struct input_pixel_processor *dcn201_ipp_create(
0645     struct dc_context *ctx, uint32_t inst)
0646 {
0647     struct dcn10_ipp *ipp =
0648         kzalloc(sizeof(struct dcn10_ipp), GFP_ATOMIC);
0649 
0650     if (!ipp) {
0651         return NULL;
0652     }
0653 
0654     dcn20_ipp_construct(ipp, ctx, inst,
0655             &ipp_regs[inst], &ipp_shift, &ipp_mask);
0656     return &ipp->base;
0657 }
0658 
0659 
0660 static struct output_pixel_processor *dcn201_opp_create(
0661     struct dc_context *ctx, uint32_t inst)
0662 {
0663     struct dcn201_opp *opp =
0664         kzalloc(sizeof(struct dcn201_opp), GFP_ATOMIC);
0665 
0666     if (!opp) {
0667         return NULL;
0668     }
0669 
0670     dcn201_opp_construct(opp, ctx, inst,
0671             &opp_regs[inst], &opp_shift, &opp_mask);
0672     return &opp->base;
0673 }
0674 
0675 static struct dce_aux *dcn201_aux_engine_create(struct dc_context *ctx,
0676                         uint32_t inst)
0677 {
0678     struct aux_engine_dce110 *aux_engine =
0679         kzalloc(sizeof(struct aux_engine_dce110), GFP_ATOMIC);
0680 
0681     if (!aux_engine)
0682         return NULL;
0683 
0684     dce110_aux_engine_construct(aux_engine, ctx, inst,
0685                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
0686                     &aux_engine_regs[inst],
0687                     &aux_mask,
0688                     &aux_shift,
0689                     ctx->dc->caps.extended_aux_timeout_support);
0690 
0691     return &aux_engine->base;
0692 }
0693 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
0694 
0695 static const struct dce_i2c_registers i2c_hw_regs[] = {
0696         i2c_inst_regs(1),
0697         i2c_inst_regs(2),
0698 };
0699 
0700 static const struct dce_i2c_shift i2c_shifts = {
0701         I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
0702 };
0703 
0704 static const struct dce_i2c_mask i2c_masks = {
0705         I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
0706 };
0707 
0708 static struct dce_i2c_hw *dcn201_i2c_hw_create(struct dc_context *ctx,
0709                            uint32_t inst)
0710 {
0711     struct dce_i2c_hw *dce_i2c_hw =
0712         kzalloc(sizeof(struct dce_i2c_hw), GFP_ATOMIC);
0713 
0714     if (!dce_i2c_hw)
0715         return NULL;
0716 
0717     dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
0718                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
0719 
0720     return dce_i2c_hw;
0721 }
0722 
0723 static struct mpc *dcn201_mpc_create(struct dc_context *ctx, uint32_t num_mpcc)
0724 {
0725     struct dcn201_mpc *mpc201 = kzalloc(sizeof(struct dcn201_mpc),
0726                         GFP_ATOMIC);
0727 
0728     if (!mpc201)
0729         return NULL;
0730 
0731     dcn201_mpc_construct(mpc201, ctx,
0732             &mpc_regs,
0733             &mpc_shift,
0734             &mpc_mask,
0735             num_mpcc);
0736 
0737     return &mpc201->base;
0738 }
0739 
0740 static struct hubbub *dcn201_hubbub_create(struct dc_context *ctx)
0741 {
0742     struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
0743                       GFP_ATOMIC);
0744 
0745     if (!hubbub)
0746         return NULL;
0747 
0748     hubbub201_construct(hubbub, ctx,
0749             &hubbub_reg,
0750             &hubbub_shift,
0751             &hubbub_mask);
0752 
0753     return &hubbub->base;
0754 }
0755 
0756 static struct timing_generator *dcn201_timing_generator_create(
0757         struct dc_context *ctx,
0758         uint32_t instance)
0759 {
0760     struct optc *tgn10 =
0761         kzalloc(sizeof(struct optc), GFP_ATOMIC);
0762 
0763     if (!tgn10)
0764         return NULL;
0765 
0766     tgn10->base.inst = instance;
0767     tgn10->base.ctx = ctx;
0768 
0769     tgn10->tg_regs = &tg_regs[instance];
0770     tgn10->tg_shift = &tg_shift;
0771     tgn10->tg_mask = &tg_mask;
0772 
0773     dcn201_timing_generator_init(tgn10);
0774 
0775     return &tgn10->base;
0776 }
0777 
0778 static const struct encoder_feature_support link_enc_feature = {
0779         .max_hdmi_deep_color = COLOR_DEPTH_121212,
0780         .max_hdmi_pixel_clock = 600000,
0781         .hdmi_ycbcr420_supported = true,
0782         .dp_ycbcr420_supported = true,
0783         .fec_supported = true,
0784         .flags.bits.IS_HBR2_CAPABLE = true,
0785         .flags.bits.IS_HBR3_CAPABLE = true,
0786         .flags.bits.IS_TPS3_CAPABLE = true,
0787         .flags.bits.IS_TPS4_CAPABLE = true
0788 };
0789 
0790 static struct link_encoder *dcn201_link_encoder_create(
0791     struct dc_context *ctx,
0792     const struct encoder_init_data *enc_init_data)
0793 {
0794     struct dcn20_link_encoder *enc20 =
0795         kzalloc(sizeof(struct dcn20_link_encoder), GFP_ATOMIC);
0796     struct dcn10_link_encoder *enc10 = &enc20->enc10;
0797 
0798     if (!enc20)
0799         return NULL;
0800 
0801     dcn201_link_encoder_construct(enc20,
0802             enc_init_data,
0803             &link_enc_feature,
0804             &link_enc_regs[enc_init_data->transmitter],
0805             &link_enc_aux_regs[enc_init_data->channel - 1],
0806             &link_enc_hpd_regs[enc_init_data->hpd_source],
0807             &le_shift,
0808             &le_mask);
0809 
0810     return &enc10->base;
0811 }
0812 
0813 static struct clock_source *dcn201_clock_source_create(
0814     struct dc_context *ctx,
0815     struct dc_bios *bios,
0816     enum clock_source_id id,
0817     const struct dce110_clk_src_regs *regs,
0818     bool dp_clk_src)
0819 {
0820     struct dce110_clk_src *clk_src =
0821         kzalloc(sizeof(struct dce110_clk_src), GFP_ATOMIC);
0822 
0823     if (!clk_src)
0824         return NULL;
0825 
0826     if (dce112_clk_src_construct(clk_src, ctx, bios, id,
0827             regs, &cs_shift, &cs_mask)) {
0828         clk_src->base.dp_clk_src = dp_clk_src;
0829         return &clk_src->base;
0830     }
0831     kfree(clk_src);
0832     return NULL;
0833 }
0834 
0835 static void read_dce_straps(
0836     struct dc_context *ctx,
0837     struct resource_straps *straps)
0838 {
0839     generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
0840 
0841         FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
0842 }
0843 
0844 static struct audio *dcn201_create_audio(
0845         struct dc_context *ctx, unsigned int inst)
0846 {
0847     return dce_audio_create(ctx, inst,
0848             &audio_regs[inst], &audio_shift, &audio_mask);
0849 }
0850 
0851 static struct stream_encoder *dcn201_stream_encoder_create(
0852     enum engine_id eng_id,
0853     struct dc_context *ctx)
0854 {
0855     struct dcn10_stream_encoder *enc1 =
0856         kzalloc(sizeof(struct dcn10_stream_encoder), GFP_ATOMIC);
0857 
0858     if (!enc1)
0859         return NULL;
0860 
0861     dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
0862                     &stream_enc_regs[eng_id],
0863                     &se_shift, &se_mask);
0864 
0865     return &enc1->base;
0866 }
0867 
0868 static const struct dce_hwseq_registers hwseq_reg = {
0869         HWSEQ_DCN201_REG_LIST()
0870 };
0871 
0872 static const struct dce_hwseq_shift hwseq_shift = {
0873         HWSEQ_DCN201_MASK_SH_LIST(__SHIFT)
0874 };
0875 
0876 static const struct dce_hwseq_mask hwseq_mask = {
0877         HWSEQ_DCN201_MASK_SH_LIST(_MASK)
0878 };
0879 
0880 static struct dce_hwseq *dcn201_hwseq_create(
0881     struct dc_context *ctx)
0882 {
0883     struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_ATOMIC);
0884 
0885     if (hws) {
0886         hws->ctx = ctx;
0887         hws->regs = &hwseq_reg;
0888         hws->shifts = &hwseq_shift;
0889         hws->masks = &hwseq_mask;
0890     }
0891     return hws;
0892 }
0893 
0894 static const struct resource_create_funcs res_create_funcs = {
0895     .read_dce_straps = read_dce_straps,
0896     .create_audio = dcn201_create_audio,
0897     .create_stream_encoder = dcn201_stream_encoder_create,
0898     .create_hwseq = dcn201_hwseq_create,
0899 };
0900 
0901 static const struct resource_create_funcs res_create_maximus_funcs = {
0902     .read_dce_straps = NULL,
0903     .create_audio = NULL,
0904     .create_stream_encoder = NULL,
0905     .create_hwseq = dcn201_hwseq_create,
0906 };
0907 
0908 static void dcn201_clock_source_destroy(struct clock_source **clk_src)
0909 {
0910     kfree(TO_DCE110_CLK_SRC(*clk_src));
0911     *clk_src = NULL;
0912 }
0913 
0914 static void dcn201_resource_destruct(struct dcn201_resource_pool *pool)
0915 {
0916     unsigned int i;
0917 
0918     for (i = 0; i < pool->base.stream_enc_count; i++) {
0919         if (pool->base.stream_enc[i] != NULL) {
0920             kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
0921             pool->base.stream_enc[i] = NULL;
0922         }
0923     }
0924 
0925 
0926     if (pool->base.mpc != NULL) {
0927         kfree(TO_DCN201_MPC(pool->base.mpc));
0928         pool->base.mpc = NULL;
0929     }
0930 
0931     if (pool->base.hubbub != NULL) {
0932         kfree(pool->base.hubbub);
0933         pool->base.hubbub = NULL;
0934     }
0935 
0936     for (i = 0; i < pool->base.pipe_count; i++) {
0937         if (pool->base.dpps[i] != NULL)
0938             dcn201_dpp_destroy(&pool->base.dpps[i]);
0939 
0940         if (pool->base.ipps[i] != NULL)
0941             pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
0942 
0943         if (pool->base.hubps[i] != NULL) {
0944             kfree(TO_DCN10_HUBP(pool->base.hubps[i]));
0945             pool->base.hubps[i] = NULL;
0946         }
0947 
0948         if (pool->base.irqs != NULL) {
0949             dal_irq_service_destroy(&pool->base.irqs);
0950         }
0951     }
0952 
0953     for (i = 0; i < pool->base.res_cap->num_opp; i++) {
0954         if (pool->base.opps[i] != NULL)
0955             pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
0956     }
0957 
0958     for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
0959         if (pool->base.timing_generators[i] != NULL)    {
0960             kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
0961             pool->base.timing_generators[i] = NULL;
0962         }
0963     }
0964     for (i = 0; i < pool->base.audio_count; i++) {
0965         if (pool->base.audios[i])
0966             dce_aud_destroy(&pool->base.audios[i]);
0967     }
0968 
0969     for (i = 0; i < pool->base.clk_src_count; i++) {
0970         if (pool->base.clock_sources[i] != NULL) {
0971             dcn201_clock_source_destroy(&pool->base.clock_sources[i]);
0972             pool->base.clock_sources[i] = NULL;
0973         }
0974     }
0975 
0976     if (pool->base.dp_clock_source != NULL) {
0977         dcn201_clock_source_destroy(&pool->base.dp_clock_source);
0978         pool->base.dp_clock_source = NULL;
0979     }
0980 
0981     if (pool->base.dccg != NULL)
0982         dcn_dccg_destroy(&pool->base.dccg);
0983 }
0984 
0985 static struct hubp *dcn201_hubp_create(
0986     struct dc_context *ctx,
0987     uint32_t inst)
0988 {
0989     struct dcn201_hubp *hubp201 =
0990         kzalloc(sizeof(struct dcn201_hubp), GFP_ATOMIC);
0991 
0992     if (!hubp201)
0993         return NULL;
0994 
0995     if (dcn201_hubp_construct(hubp201, ctx, inst,
0996             &hubp_regs[inst], &hubp_shift, &hubp_mask))
0997         return &hubp201->base;
0998 
0999     kfree(hubp201);
1000     return NULL;
1001 }
1002 
1003 static struct pipe_ctx *dcn201_acquire_idle_pipe_for_layer(
1004         struct dc_state *context,
1005         const struct resource_pool *pool,
1006         struct dc_stream_state *stream)
1007 {
1008     struct resource_context *res_ctx = &context->res_ctx;
1009     struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
1010     struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe);
1011 
1012     if (!head_pipe)
1013         ASSERT(0);
1014 
1015     if (!idle_pipe)
1016         return NULL;
1017 
1018     idle_pipe->stream = head_pipe->stream;
1019     idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
1020     idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
1021 
1022     idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
1023     idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
1024     idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
1025     idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
1026 
1027     return idle_pipe;
1028 }
1029 
1030 static bool dcn201_get_dcc_compression_cap(const struct dc *dc,
1031         const struct dc_dcc_surface_param *input,
1032         struct dc_surface_dcc_cap *output)
1033 {
1034     return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
1035             dc->res_pool->hubbub,
1036             input,
1037             output);
1038 }
1039 
1040 static void dcn201_populate_dml_writeback_from_context(struct dc *dc,
1041                                struct resource_context *res_ctx,
1042                                display_e2e_pipe_params_st *pipes)
1043 {
1044     DC_FP_START();
1045     dcn201_populate_dml_writeback_from_context_fpu(dc, res_ctx, pipes);
1046     DC_FP_END();
1047 }
1048 
1049 static void dcn201_destroy_resource_pool(struct resource_pool **pool)
1050 {
1051     struct dcn201_resource_pool *dcn201_pool = TO_DCN201_RES_POOL(*pool);
1052 
1053     dcn201_resource_destruct(dcn201_pool);
1054     kfree(dcn201_pool);
1055     *pool = NULL;
1056 }
1057 
1058 static void dcn201_link_init(struct dc_link *link)
1059 {
1060     if (link->ctx->dc_bios->integrated_info)
1061         link->dp_ss_off = !link->ctx->dc_bios->integrated_info->dp_ss_control;
1062 }
1063 
1064 static struct dc_cap_funcs cap_funcs = {
1065     .get_dcc_compression_cap = dcn201_get_dcc_compression_cap,
1066 };
1067 
1068 static struct resource_funcs dcn201_res_pool_funcs = {
1069     .link_init = dcn201_link_init,
1070     .destroy = dcn201_destroy_resource_pool,
1071     .link_enc_create = dcn201_link_encoder_create,
1072     .panel_cntl_create = NULL,
1073     .validate_bandwidth = dcn20_validate_bandwidth,
1074     .populate_dml_pipes = dcn20_populate_dml_pipes_from_context,
1075     .add_stream_to_ctx = dcn20_add_stream_to_ctx,
1076     .add_dsc_to_stream_resource = NULL,
1077     .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1078     .acquire_idle_pipe_for_layer = dcn201_acquire_idle_pipe_for_layer,
1079     .populate_dml_writeback_from_context = dcn201_populate_dml_writeback_from_context,
1080     .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1081     .set_mcif_arb_params = dcn20_set_mcif_arb_params,
1082     .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link
1083 };
1084 
1085 static bool dcn201_resource_construct(
1086     uint8_t num_virtual_links,
1087     struct dc *dc,
1088     struct dcn201_resource_pool *pool)
1089 {
1090     int i;
1091     struct dc_context *ctx = dc->ctx;
1092 
1093     ctx->dc_bios->regs = &bios_regs;
1094 
1095     pool->base.res_cap = &res_cap_dnc201;
1096     pool->base.funcs = &dcn201_res_pool_funcs;
1097 
1098     /*************************************************
1099      *  Resource + asic cap harcoding                *
1100      *************************************************/
1101     pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1102 
1103     pool->base.pipe_count = 4;
1104     pool->base.mpcc_count = 5;
1105     dc->caps.max_downscale_ratio = 200;
1106     dc->caps.i2c_speed_in_khz = 100;
1107     dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.5 w/a applied by default*/
1108     dc->caps.max_cursor_size = 256;
1109     dc->caps.min_horizontal_blanking_period = 80;
1110     dc->caps.dmdata_alloc_size = 2048;
1111 
1112     dc->caps.max_slave_planes = 1;
1113     dc->caps.max_slave_yuv_planes = 1;
1114     dc->caps.max_slave_rgb_planes = 1;
1115     dc->caps.post_blend_color_processing = true;
1116     dc->caps.force_dp_tps4_for_cp2520 = true;
1117     dc->caps.extended_aux_timeout_support = true;
1118 
1119     /* Color pipeline capabilities */
1120     dc->caps.color.dpp.dcn_arch = 1;
1121     dc->caps.color.dpp.input_lut_shared = 0;
1122     dc->caps.color.dpp.icsc = 1;
1123     dc->caps.color.dpp.dgam_ram = 1;
1124     dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1125     dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1126     dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
1127     dc->caps.color.dpp.dgam_rom_caps.pq = 0;
1128     dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
1129     dc->caps.color.dpp.post_csc = 0;
1130     dc->caps.color.dpp.gamma_corr = 0;
1131     dc->caps.color.dpp.dgam_rom_for_yuv = 1;
1132 
1133     dc->caps.color.dpp.hw_3d_lut = 1;
1134     dc->caps.color.dpp.ogam_ram = 1;
1135     // no OGAM ROM on DCN2
1136     dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1137     dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1138     dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1139     dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1140     dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1141     dc->caps.color.dpp.ocsc = 0;
1142 
1143     dc->caps.color.mpc.gamut_remap = 0;
1144     dc->caps.color.mpc.num_3dluts = 0;
1145     dc->caps.color.mpc.shared_3d_lut = 0;
1146     dc->caps.color.mpc.ogam_ram = 1;
1147     dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1148     dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1149     dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1150     dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1151     dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1152     dc->caps.color.mpc.ocsc = 1;
1153 
1154     dc->debug = debug_defaults_drv;
1155 
1156     /*a0 only, remove later*/
1157     dc->work_arounds.no_connect_phy_config  = true;
1158     dc->work_arounds.dedcn20_305_wa = true;
1159     /*************************************************
1160      *  Create resources                             *
1161      *************************************************/
1162 
1163     pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
1164             dcn201_clock_source_create(ctx, ctx->dc_bios,
1165                 CLOCK_SOURCE_COMBO_PHY_PLL0,
1166                 &clk_src_regs[0], false);
1167     pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
1168             dcn201_clock_source_create(ctx, ctx->dc_bios,
1169                 CLOCK_SOURCE_COMBO_PHY_PLL1,
1170                 &clk_src_regs[1], false);
1171 
1172     pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN201;
1173 
1174     /* todo: not reuse phy_pll registers */
1175     pool->base.dp_clock_source =
1176             dcn201_clock_source_create(ctx, ctx->dc_bios,
1177                 CLOCK_SOURCE_ID_DP_DTO,
1178                 &clk_src_regs[0], true);
1179 
1180     for (i = 0; i < pool->base.clk_src_count; i++) {
1181         if (pool->base.clock_sources[i] == NULL) {
1182             dm_error("DC: failed to create clock sources!\n");
1183             goto create_fail;
1184         }
1185     }
1186 
1187     pool->base.dccg = dccg201_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1188     if (pool->base.dccg == NULL) {
1189         dm_error("DC: failed to create dccg!\n");
1190         goto create_fail;
1191     }
1192 
1193     dcn201_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
1194     dcn201_ip.max_num_dpp = pool->base.pipe_count;
1195     dml_init_instance(&dc->dml, &dcn201_soc, &dcn201_ip, DML_PROJECT_DCN201);
1196     {
1197         struct irq_service_init_data init_data;
1198         init_data.ctx = dc->ctx;
1199         pool->base.irqs = dal_irq_service_dcn201_create(&init_data);
1200         if (!pool->base.irqs)
1201             goto create_fail;
1202     }
1203 
1204     /* mem input -> ipp -> dpp -> opp -> TG */
1205     for (i = 0; i < pool->base.pipe_count; i++) {
1206         pool->base.hubps[i] = dcn201_hubp_create(ctx, i);
1207         if (pool->base.hubps[i] == NULL) {
1208             dm_error(
1209                 "DC: failed to create memory input!\n");
1210             goto create_fail;
1211         }
1212 
1213         pool->base.ipps[i] = dcn201_ipp_create(ctx, i);
1214         if (pool->base.ipps[i] == NULL) {
1215             dm_error(
1216                 "DC: failed to create input pixel processor!\n");
1217             goto create_fail;
1218         }
1219 
1220         pool->base.dpps[i] = dcn201_dpp_create(ctx, i);
1221         if (pool->base.dpps[i] == NULL) {
1222             dm_error(
1223                 "DC: failed to create dpps!\n");
1224             goto create_fail;
1225         }
1226     }
1227 
1228     for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1229         pool->base.opps[i] = dcn201_opp_create(ctx, i);
1230         if (pool->base.opps[i] == NULL) {
1231             dm_error(
1232                 "DC: failed to create output pixel processor!\n");
1233             goto create_fail;
1234         }
1235     }
1236 
1237     for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1238         pool->base.engines[i] = dcn201_aux_engine_create(ctx, i);
1239         if (pool->base.engines[i] == NULL) {
1240             dm_error(
1241                 "DC:failed to create aux engine!!\n");
1242             goto create_fail;
1243         }
1244         pool->base.hw_i2cs[i] = dcn201_i2c_hw_create(ctx, i);
1245         if (pool->base.hw_i2cs[i] == NULL) {
1246             dm_error(
1247                 "DC:failed to create hw i2c!!\n");
1248             goto create_fail;
1249         }
1250         pool->base.sw_i2cs[i] = NULL;
1251     }
1252 
1253     for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1254         pool->base.timing_generators[i] = dcn201_timing_generator_create(
1255                 ctx, i);
1256         if (pool->base.timing_generators[i] == NULL) {
1257             dm_error("DC: failed to create tg!\n");
1258             goto create_fail;
1259         }
1260     }
1261 
1262     pool->base.timing_generator_count = i;
1263 
1264     pool->base.mpc = dcn201_mpc_create(ctx, pool->base.mpcc_count);
1265     if (pool->base.mpc == NULL) {
1266         dm_error("DC: failed to create mpc!\n");
1267         goto create_fail;
1268     }
1269 
1270     pool->base.hubbub = dcn201_hubbub_create(ctx);
1271     if (pool->base.hubbub == NULL) {
1272         dm_error("DC: failed to create hubbub!\n");
1273         goto create_fail;
1274     }
1275 
1276     if (!resource_construct(num_virtual_links, dc, &pool->base,
1277             (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
1278             &res_create_funcs : &res_create_maximus_funcs)))
1279             goto create_fail;
1280 
1281     dcn201_hw_sequencer_construct(dc);
1282 
1283     dc->caps.max_planes =  pool->base.pipe_count;
1284 
1285     for (i = 0; i < dc->caps.max_planes; ++i)
1286         dc->caps.planes[i] = plane_cap;
1287 
1288     dc->cap_funcs = cap_funcs;
1289 
1290     return true;
1291 
1292 create_fail:
1293 
1294     dcn201_resource_destruct(pool);
1295 
1296     return false;
1297 }
1298 
1299 struct resource_pool *dcn201_create_resource_pool(
1300         const struct dc_init_data *init_data,
1301         struct dc *dc)
1302 {
1303     struct dcn201_resource_pool *pool =
1304         kzalloc(sizeof(struct dcn201_resource_pool), GFP_ATOMIC);
1305 
1306     if (!pool)
1307         return NULL;
1308 
1309     if (dcn201_resource_construct(init_data->num_virtual_links, dc, pool))
1310         return &pool->base;
1311 
1312     kfree(pool);
1313     return NULL;
1314 }
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