dc/dcn201/dcn201_opp.h

0001 /* Copyright 2012-15 Advanced Micro Devices, Inc.
0002  *
0003  * Permission is hereby granted, free of charge, to any person obtaining a
0004  * copy of this software and associated documentation files (the "Software"),
0005  * to deal in the Software without restriction, including without limitation
0006  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0007  * and/or sell copies of the Software, and to permit persons to whom the
0008  * Software is furnished to do so, subject to the following conditions:
0009  *
0010  * The above copyright notice and this permission notice shall be included in
0011  * all copies or substantial portions of the Software.
0012  *
0013  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0014  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0015  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0016  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0017  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0018  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0019  * OTHER DEALINGS IN THE SOFTWARE.
0020  *
0021  * Authors: AMD
0022  *
0023  */
0024
0025 #ifndef __DC_OPP_DCN201_H__
0026 #define __DC_OPP_DCN201_H__
0027
0028 #include "dcn20/dcn20_opp.h"
0029
0030 #define TO_DCN201_OPP(opp)\
0031     container_of(opp, struct dcn201_opp, base)
0032
0033 #define OPP_SF(reg_name, field_name, post_fix)\
0034     .field_name = reg_name ## __ ## field_name ## post_fix
0035
0036 #define OPP_REG_LIST_DCN201(id) \
0037     OPP_REG_LIST_DCN10(id), \
0038     OPP_DPG_REG_LIST(id), \
0039     SRI(FMT_422_CONTROL, FMT, id)
0040
0041 #define OPP_MASK_SH_LIST_DCN201(mask_sh) \
0042     OPP_MASK_SH_LIST_DCN20(mask_sh)
0043
0044 #define OPP_DCN201_REG_FIELD_LIST(type) \
0045     OPP_DCN20_REG_FIELD_LIST(type);
0046
0047 struct dcn201_opp_shift {
0048     OPP_DCN201_REG_FIELD_LIST(uint8_t);
0049 };
0050
0051 struct dcn201_opp_mask {
0052     OPP_DCN201_REG_FIELD_LIST(uint32_t);
0053 };
0054
0055 struct dcn201_opp_registers {
0056     OPP_REG_VARIABLE_LIST_DCN2_0;
0057 };
0058
0059 struct dcn201_opp {
0060     struct output_pixel_processor base;
0061     const struct  dcn201_opp_registers *regs;
0062     const struct  dcn201_opp_shift *opp_shift;
0063     const struct  dcn201_opp_mask *opp_mask;
0064     bool is_write_to_ram_a_safe;
0065 };
0066
0067 void dcn201_opp_construct(struct dcn201_opp *oppn201,
0068     struct dc_context *ctx,
0069     uint32_t inst,
0070     const struct dcn201_opp_registers *regs,
0071     const struct dcn201_opp_shift *opp_shift,
0072     const struct dcn201_opp_mask *opp_mask);
0073
0074 #endif