dc/dcn201/dcn201_mpc.h

0001 /* Copyright 2012-15 Advanced Micro Devices, Inc.
0002  *
0003  * Permission is hereby granted, free of charge, to any person obtaining a
0004  * copy of this software and associated documentation files (the "Software"),
0005  * to deal in the Software without restriction, including without limitation
0006  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0007  * and/or sell copies of the Software, and to permit persons to whom the
0008  * Software is furnished to do so, subject to the following conditions:
0009  *
0010  * The above copyright notice and this permission notice shall be included in
0011  * all copies or substantial portions of the Software.
0012  *
0013  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0014  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0015  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0016  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0017  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0018  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0019  * OTHER DEALINGS IN THE SOFTWARE.
0020  *
0021  * Authors: AMD
0022  *
0023  */
0024
0025 #ifndef __DC_MPCC_DCN201_H__
0026 #define __DC_MPCC_DCN201_H__
0027
0028 #include "dcn20/dcn20_mpc.h"
0029
0030 #define TO_DCN201_MPC(mpc_base) \
0031     container_of(mpc_base, struct dcn201_mpc, base)
0032
0033 #define MPC_REG_LIST_DCN201(inst) \
0034     MPC_REG_LIST_DCN2_0(inst)
0035
0036 #define MPC_OUT_MUX_REG_LIST_DCN201(inst) \
0037     MPC_OUT_MUX_REG_LIST_DCN2_0(inst)
0038
0039 #define MPC_REG_VARIABLE_LIST_DCN201 \
0040     MPC_REG_VARIABLE_LIST_DCN2_0
0041
0042 #define MPC_COMMON_MASK_SH_LIST_DCN201(mask_sh) \
0043     MPC_COMMON_MASK_SH_LIST_DCN2_0(mask_sh),\
0044     SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL, mask_sh),\
0045     SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL_DISABLE, mask_sh),\
0046     SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_MODE, mask_sh),\
0047     SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT0, mask_sh),\
0048     SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT1, mask_sh)
0049
0050 #define MPC_REG_FIELD_LIST_DCN201(type) \
0051     MPC_REG_FIELD_LIST_DCN2_0(type) \
0052     type MPC_OUT_RATE_CONTROL;\
0053     type MPC_OUT_RATE_CONTROL_DISABLE;\
0054     type MPC_OUT_FLOW_CONTROL_MODE;\
0055     type MPC_OUT_FLOW_CONTROL_COUNT0;\
0056     type MPC_OUT_FLOW_CONTROL_COUNT1;
0057
0058 struct dcn201_mpc_registers {
0059     MPC_REG_VARIABLE_LIST_DCN201
0060 };
0061
0062 struct dcn201_mpc_shift {
0063     MPC_REG_FIELD_LIST_DCN201(uint8_t)
0064 };
0065
0066 struct dcn201_mpc_mask {
0067     MPC_REG_FIELD_LIST_DCN201(uint32_t)
0068 };
0069
0070 struct dcn201_mpc {
0071     struct mpc base;
0072     int mpcc_in_use_mask;
0073     int num_mpcc;
0074     const struct dcn201_mpc_registers *mpc_regs;
0075     const struct dcn201_mpc_shift *mpc_shift;
0076     const struct dcn201_mpc_mask *mpc_mask;
0077 };
0078
0079 void dcn201_mpc_construct(struct dcn201_mpc *mpc201,
0080     struct dc_context *ctx,
0081     const struct dcn201_mpc_registers *mpc_regs,
0082     const struct dcn201_mpc_shift *mpc_shift,
0083     const struct dcn201_mpc_mask *mpc_mask,
0084     int num_mpcc);
0085
0086 #endif