dc/dcn201/dcn201_mpc.c

0001 /*
0002  * Copyright 2012-15 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include "reg_helper.h"
0027 #include "dcn201_mpc.h"
0028
0029 #define REG(reg)\
0030     mpc201->mpc_regs->reg
0031
0032 #define CTX \
0033     mpc201->base.ctx
0034
0035 #define DC_LOGGER \
0036     mpc201->base.ctx->logger
0037
0038 #undef FN
0039 #define FN(reg_name, field_name) \
0040     mpc201->mpc_shift->field_name, mpc201->mpc_mask->field_name
0041
0042 static void mpc201_set_out_rate_control(
0043     struct mpc *mpc,
0044     int opp_id,
0045     bool enable,
0046     bool rate_2x_mode,
0047     struct mpc_dwb_flow_control *flow_control)
0048 {
0049     struct dcn201_mpc *mpc201 = TO_DCN201_MPC(mpc);
0050
0051     REG_UPDATE_2(MUX[opp_id],
0052             MPC_OUT_RATE_CONTROL_DISABLE, !enable,
0053             MPC_OUT_RATE_CONTROL, rate_2x_mode);
0054
0055     if (flow_control)
0056         REG_UPDATE_3(MUX[opp_id],
0057             MPC_OUT_FLOW_CONTROL_MODE, flow_control->flow_ctrl_mode,
0058             MPC_OUT_FLOW_CONTROL_COUNT0, flow_control->flow_ctrl_cnt0,
0059             MPC_OUT_FLOW_CONTROL_COUNT1, flow_control->flow_ctrl_cnt1);
0060 }
0061
0062 static void mpc201_init_mpcc(struct mpcc *mpcc, int mpcc_inst)
0063 {
0064     mpcc->mpcc_id = mpcc_inst;
0065     mpcc->dpp_id = 0xf;
0066     mpcc->mpcc_bot = NULL;
0067     mpcc->blnd_cfg.overlap_only = false;
0068     mpcc->blnd_cfg.global_alpha = 0xff;
0069     mpcc->blnd_cfg.global_gain = 0xff;
0070     mpcc->blnd_cfg.background_color_bpc = 4;
0071     mpcc->blnd_cfg.bottom_gain_mode = 0;
0072     mpcc->blnd_cfg.top_gain = 0x1f000;
0073     mpcc->blnd_cfg.bottom_inside_gain = 0x1f000;
0074     mpcc->blnd_cfg.bottom_outside_gain = 0x1f000;
0075     mpcc->sm_cfg.enable = false;
0076     mpcc->shared_bottom = false;
0077 }
0078
0079 const struct mpc_funcs dcn201_mpc_funcs = {
0080     .read_mpcc_state = mpc1_read_mpcc_state,
0081     .insert_plane = mpc1_insert_plane,
0082     .remove_mpcc = mpc1_remove_mpcc,
0083     .mpc_init = mpc1_mpc_init,
0084     .mpc_init_single_inst = mpc1_mpc_init_single_inst,
0085     .update_blending = mpc2_update_blending,
0086     .cursor_lock = mpc1_cursor_lock,
0087     .get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp,
0088     .get_mpcc_for_dpp_from_secondary = NULL,
0089     .wait_for_idle = mpc2_assert_idle_mpcc,
0090     .assert_mpcc_idle_before_connect = mpc2_assert_mpcc_idle_before_connect,
0091     .init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw,
0092     .set_denorm = mpc2_set_denorm,
0093     .set_denorm_clamp = mpc2_set_denorm_clamp,
0094     .set_output_csc = mpc2_set_output_csc,
0095     .set_ocsc_default = mpc2_set_ocsc_default,
0096     .set_output_gamma = mpc2_set_output_gamma,
0097     .set_out_rate_control = mpc201_set_out_rate_control,
0098     .power_on_mpc_mem_pwr = mpc20_power_on_ogam_lut,
0099     .get_mpc_out_mux = mpc1_get_mpc_out_mux,
0100     .set_bg_color = mpc1_set_bg_color,
0101 };
0102
0103 void dcn201_mpc_construct(struct dcn201_mpc *mpc201,
0104     struct dc_context *ctx,
0105     const struct dcn201_mpc_registers *mpc_regs,
0106     const struct dcn201_mpc_shift *mpc_shift,
0107     const struct dcn201_mpc_mask *mpc_mask,
0108     int num_mpcc)
0109 {
0110     int i;
0111
0112     mpc201->base.ctx = ctx;
0113
0114     mpc201->base.funcs = &dcn201_mpc_funcs;
0115
0116     mpc201->mpc_regs = mpc_regs;
0117     mpc201->mpc_shift = mpc_shift;
0118     mpc201->mpc_mask = mpc_mask;
0119
0120     mpc201->mpcc_in_use_mask = 0;
0121     mpc201->num_mpcc = num_mpcc;
0122
0123     for (i = 0; i < MAX_MPCC; i++)
0124         mpc201_init_mpcc(&mpc201->base.mpcc_array[i], i);
0125 }