dc/dcn201/dcn201_link_encoder.c

0001 /*
0002  * Copyright 2012-15 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include "reg_helper.h"
0027
0028 #include "core_types.h"
0029 #include "link_encoder.h"
0030 #include "dcn201_link_encoder.h"
0031 #include "stream_encoder.h"
0032 #include "i2caux_interface.h"
0033 #include "dc_bios_types.h"
0034
0035 #include "gpio_service_interface.h"
0036
0037 #define CTX \
0038     enc10->base.ctx
0039
0040 #define DC_LOGGER \
0041     enc10->base.ctx->logger
0042
0043 #define REG(reg)\
0044     (enc10->link_regs->reg)
0045
0046 #undef FN
0047 #define FN(reg_name, field_name) \
0048     enc10->link_shift->field_name, enc10->link_mask->field_name
0049
0050 #define IND_REG(index) \
0051     (enc10->link_regs->index)
0052
0053 static void dcn201_link_encoder_get_max_link_cap(struct link_encoder *enc,
0054                          struct dc_link_settings *link_settings)
0055 {
0056     uint32_t value1, value2;
0057     struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
0058
0059     dcn10_link_encoder_get_max_link_cap(enc, link_settings);
0060     REG_GET_2(RDPCSTX_PHY_CNTL2, RDPCS_PHY_DPALT_DISABLE, &value1,
0061          RDPCS_PHY_DPALT_DP4, &value2);
0062     /*limit to combo_phy*/
0063     if (enc->usbc_combo_phy) {
0064         if (!value1 && !value2 && link_settings->lane_count > LANE_COUNT_TWO)
0065             link_settings->lane_count = LANE_COUNT_TWO;
0066     }
0067 }
0068
0069 static bool dcn201_link_encoder_is_in_alt_mode(struct link_encoder *enc)
0070 {
0071     uint32_t value;
0072     struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
0073
0074     REG_GET(RDPCSTX_PHY_CNTL2, RDPCS_PHY_DPALT_DISABLE, &value);
0075
0076     // if value == 1 alt mode is disabled, otherwise it is enabled
0077     return !value;
0078 }
0079
0080 static const struct link_encoder_funcs dcn201_link_enc_funcs = {
0081     .read_state = link_enc2_read_state,
0082     .validate_output_with_stream =
0083         dcn10_link_encoder_validate_output_with_stream,
0084     .hw_init = enc2_hw_init,
0085     .setup = dcn10_link_encoder_setup,
0086     .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
0087     .enable_dp_output = dcn10_link_encoder_enable_dp_output,
0088     .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
0089     .disable_output = dcn10_link_encoder_disable_output,
0090     .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
0091     .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
0092     .update_mst_stream_allocation_table =
0093         dcn10_link_encoder_update_mst_stream_allocation_table,
0094     .psr_program_dp_dphy_fast_training =
0095             dcn10_psr_program_dp_dphy_fast_training,
0096     .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
0097     .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
0098     .enable_hpd = dcn10_link_encoder_enable_hpd,
0099     .disable_hpd = dcn10_link_encoder_disable_hpd,
0100     .is_dig_enabled = dcn10_is_dig_enabled,
0101     .destroy = dcn10_link_encoder_destroy,
0102     .fec_set_enable = enc2_fec_set_enable,
0103     .fec_set_ready = enc2_fec_set_ready,
0104     .get_dig_frontend = dcn10_get_dig_frontend,
0105     .fec_is_active = enc2_fec_is_active,
0106     .is_in_alt_mode = dcn201_link_encoder_is_in_alt_mode,
0107     .get_max_link_cap = dcn201_link_encoder_get_max_link_cap,
0108 };
0109
0110 void dcn201_link_encoder_construct(
0111     struct dcn20_link_encoder *enc20,
0112     const struct encoder_init_data *init_data,
0113     const struct encoder_feature_support *enc_features,
0114     const struct dcn10_link_enc_registers *link_regs,
0115     const struct dcn10_link_enc_aux_registers *aux_regs,
0116     const struct dcn10_link_enc_hpd_registers *hpd_regs,
0117     const struct dcn10_link_enc_shift *link_shift,
0118     const struct dcn10_link_enc_mask *link_mask)
0119 {
0120     struct bp_encoder_cap_info bp_cap_info = {0};
0121     const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
0122     enum bp_result result = BP_RESULT_OK;
0123     struct dcn10_link_encoder *enc10 = &enc20->enc10;
0124
0125     enc10->base.funcs = &dcn201_link_enc_funcs;
0126     enc10->base.ctx = init_data->ctx;
0127     enc10->base.id = init_data->encoder;
0128
0129     enc10->base.hpd_source = init_data->hpd_source;
0130     enc10->base.connector = init_data->connector;
0131
0132     enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
0133
0134     enc10->base.features = *enc_features;
0135
0136     enc10->base.transmitter = init_data->transmitter;
0137
0138     /* set the flag to indicate whether driver poll the I2C data pin
0139      * while doing the DP sink detect
0140      */
0141
0142     /* if (dal_adapter_service_is_feature_supported(as,
0143      * FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
0144      * enc10->base.features.flags.bits.
0145      * DP_SINK_DETECT_POLL_DATA_PIN = true;
0146      */
0147
0148     enc10->base.output_signals =
0149         SIGNAL_TYPE_DVI_SINGLE_LINK |
0150         SIGNAL_TYPE_DVI_DUAL_LINK |
0151         SIGNAL_TYPE_LVDS |
0152         SIGNAL_TYPE_DISPLAY_PORT |
0153         SIGNAL_TYPE_DISPLAY_PORT_MST |
0154         SIGNAL_TYPE_EDP |
0155         SIGNAL_TYPE_HDMI_TYPE_A;
0156
0157     /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
0158      * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
0159      * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
0160      * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
0161      * Prefer DIG assignment is decided by board design.
0162      * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
0163      * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
0164      * By this, adding DIGG should not hurt DCE 8.0.
0165      * This will let DCE 8.1 share DCE 8.0 as much as possible
0166      */
0167
0168     enc10->link_regs = link_regs;
0169     enc10->aux_regs = aux_regs;
0170     enc10->hpd_regs = hpd_regs;
0171     enc10->link_shift = link_shift;
0172     enc10->link_mask = link_mask;
0173
0174     switch (enc10->base.transmitter) {
0175     case TRANSMITTER_UNIPHY_A:
0176         enc10->base.preferred_engine = ENGINE_ID_DIGA;
0177     break;
0178     case TRANSMITTER_UNIPHY_B:
0179         enc10->base.preferred_engine = ENGINE_ID_DIGB;
0180     break;
0181     default:
0182         ASSERT_CRITICAL(false);
0183         enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
0184     }
0185
0186     /* default to one to mirror Windows behavior */
0187     enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
0188
0189     result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
0190                         enc10->base.id, &bp_cap_info);
0191
0192     /* Override features with DCE-specific values */
0193     if (result == BP_RESULT_OK) {
0194         enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
0195                 bp_cap_info.DP_HBR2_EN;
0196         enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
0197                 bp_cap_info.DP_HBR3_EN;
0198         enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
0199         enc10->base.features.flags.bits.DP_IS_USB_C =
0200                 bp_cap_info.DP_IS_USB_C;
0201     } else {
0202         DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
0203                 __func__,
0204                 result);
0205     }
0206     if (enc10->base.ctx->dc->debug.hdmi20_disable) {
0207         enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
0208     }
0209 }