dc/dcn201/dcn201_hubp.c

0001 /*
0002  * Copyright 2012-17 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 #include "dcn201_hubp.h"
0026
0027 #include "dm_services.h"
0028 #include "dce_calcs.h"
0029 #include "reg_helper.h"
0030 #include "basics/conversion.h"
0031
0032 #define REG(reg)\
0033     hubp201->hubp_regs->reg
0034
0035 #define CTX \
0036     hubp201->base.ctx
0037
0038 #undef FN
0039 #define FN(reg_name, field_name) \
0040     hubp201->hubp_shift->field_name, hubp201->hubp_mask->field_name
0041
0042 static void hubp201_program_surface_config(
0043     struct hubp *hubp,
0044     enum surface_pixel_format format,
0045     union dc_tiling_info *tiling_info,
0046     struct plane_size *plane_size,
0047     enum dc_rotation_angle rotation,
0048     struct dc_plane_dcc_param *dcc,
0049     bool horizontal_mirror,
0050     unsigned int compat_level)
0051 {
0052     hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks);
0053     hubp1_program_tiling(hubp, tiling_info, format);
0054     hubp1_program_size(hubp, format, plane_size, dcc);
0055     hubp1_program_pixel_format(hubp, format);
0056 }
0057
0058 static void hubp201_program_deadline(
0059         struct hubp *hubp,
0060         struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
0061         struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
0062 {
0063     hubp1_program_deadline(hubp, dlg_attr, ttu_attr);
0064 }
0065
0066 static void hubp201_program_requestor(struct hubp *hubp,
0067                       struct _vcs_dpi_display_rq_regs_st *rq_regs)
0068 {
0069     struct dcn201_hubp *hubp201 = TO_DCN201_HUBP(hubp);
0070
0071     REG_UPDATE(HUBPRET_CONTROL,
0072             DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
0073
0074     REG_SET_4(DCN_EXPANSION_MODE, 0,
0075             DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
0076             PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
0077             MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
0078             CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
0079
0080     REG_SET_5(DCHUBP_REQ_SIZE_CONFIG, 0,
0081         CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
0082         MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
0083         META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
0084         MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size,
0085         SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height);
0086
0087     REG_SET_5(DCHUBP_REQ_SIZE_CONFIG_C, 0,
0088         CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size,
0089         MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size,
0090         META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size,
0091         MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size,
0092         SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height);
0093 }
0094
0095 static void hubp201_setup(
0096         struct hubp *hubp,
0097         struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
0098         struct _vcs_dpi_display_ttu_regs_st *ttu_attr,
0099         struct _vcs_dpi_display_rq_regs_st *rq_regs,
0100         struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
0101 {
0102     hubp2_vready_at_or_After_vsync(hubp, pipe_dest);
0103     hubp201_program_requestor(hubp, rq_regs);
0104     hubp201_program_deadline(hubp, dlg_attr, ttu_attr);
0105 }
0106
0107 static struct hubp_funcs dcn201_hubp_funcs = {
0108     .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
0109     .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
0110     .hubp_program_surface_flip_and_addr = hubp1_program_surface_flip_and_addr,
0111     .hubp_program_surface_config = hubp201_program_surface_config,
0112     .hubp_is_flip_pending = hubp1_is_flip_pending,
0113     .hubp_setup = hubp201_setup,
0114     .hubp_setup_interdependent = hubp2_setup_interdependent,
0115     .set_cursor_attributes  = hubp2_cursor_set_attributes,
0116     .set_cursor_position    = hubp1_cursor_set_position,
0117     .set_blank = hubp1_set_blank,
0118     .dcc_control = hubp1_dcc_control,
0119     .mem_program_viewport = min_set_viewport,
0120     .hubp_clk_cntl = hubp1_clk_cntl,
0121     .hubp_vtg_sel = hubp1_vtg_sel,
0122     .dmdata_set_attributes = hubp2_dmdata_set_attributes,
0123     .dmdata_load = hubp2_dmdata_load,
0124     .dmdata_status_done = hubp2_dmdata_status_done,
0125     .hubp_read_state = hubp2_read_state,
0126     .hubp_clear_underflow = hubp1_clear_underflow,
0127     .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
0128     .hubp_init = hubp1_init,
0129 };
0130
0131 bool dcn201_hubp_construct(
0132     struct dcn201_hubp *hubp201,
0133     struct dc_context *ctx,
0134     uint32_t inst,
0135     const struct dcn201_hubp_registers *hubp_regs,
0136     const struct dcn201_hubp_shift *hubp_shift,
0137     const struct dcn201_hubp_mask *hubp_mask)
0138 {
0139     hubp201->base.funcs = &dcn201_hubp_funcs;
0140     hubp201->base.ctx = ctx;
0141     hubp201->hubp_regs = hubp_regs;
0142     hubp201->hubp_shift = hubp_shift;
0143     hubp201->hubp_mask = hubp_mask;
0144     hubp201->base.inst = inst;
0145     hubp201->base.opp_id = OPP_ID_INVALID;
0146     hubp201->base.mpcc_id = 0xf;
0147
0148     return true;
0149 }