dc/dcn201/dcn201_dpp.h

0001 /* Copyright 2016 Advanced Micro Devices, Inc.
0002  *
0003  * Permission is hereby granted, free of charge, to any person obtaining a
0004  * copy of this software and associated documentation files (the "Software"),
0005  * to deal in the Software without restriction, including without limitation
0006  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0007  * and/or sell copies of the Software, and to permit persons to whom the
0008  * Software is furnished to do so, subject to the following conditions:
0009  *
0010  * The above copyright notice and this permission notice shall be included in
0011  * all copies or substantial portions of the Software.
0012  *
0013  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0014  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0015  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0016  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0017  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0018  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0019  * OTHER DEALINGS IN THE SOFTWARE.
0020  *
0021  * Authors: AMD
0022  *
0023  */
0024
0025 #ifndef __DCN201_DPP_H__
0026 #define __DCN201_DPP_H__
0027
0028 #include "dcn20/dcn20_dpp.h"
0029
0030 #define TO_DCN201_DPP(dpp)\
0031     container_of(dpp, struct dcn201_dpp, base)
0032
0033 #define TF_REG_LIST_DCN201(id) \
0034     TF_REG_LIST_DCN20(id)
0035
0036 #define TF_REG_LIST_SH_MASK_DCN201(mask_sh)\
0037     TF_REG_LIST_SH_MASK_DCN20(mask_sh)
0038
0039 #define TF_REG_FIELD_LIST_DCN201(type) \
0040     TF_REG_FIELD_LIST_DCN2_0(type)
0041
0042 struct dcn201_dpp_shift {
0043     TF_REG_FIELD_LIST_DCN201(uint8_t);
0044 };
0045
0046 struct dcn201_dpp_mask {
0047     TF_REG_FIELD_LIST_DCN201(uint32_t);
0048 };
0049
0050 #define DPP_DCN201_REG_VARIABLE_LIST \
0051     DPP_DCN2_REG_VARIABLE_LIST
0052
0053 struct dcn201_dpp_registers {
0054     DPP_DCN201_REG_VARIABLE_LIST;
0055 };
0056
0057 struct dcn201_dpp {
0058     struct dpp base;
0059
0060     const struct dcn201_dpp_registers *tf_regs;
0061     const struct dcn201_dpp_shift *tf_shift;
0062     const struct dcn201_dpp_mask *tf_mask;
0063
0064     const uint16_t *filter_v;
0065     const uint16_t *filter_h;
0066     const uint16_t *filter_v_c;
0067     const uint16_t *filter_h_c;
0068     int lb_pixel_depth_supported;
0069     int lb_memory_size;
0070     int lb_bits_per_entry;
0071     bool is_write_to_ram_a_safe;
0072     struct scaler_data scl_data;
0073     struct pwl_params pwl_data;
0074 };
0075
0076 bool dpp201_construct(struct dcn201_dpp *dpp2,
0077     struct dc_context *ctx,
0078     uint32_t inst,
0079     const struct dcn201_dpp_registers *tf_regs,
0080     const struct dcn201_dpp_shift *tf_shift,
0081     const struct dcn201_dpp_mask *tf_mask);
0082
0083 #endif /* __DC_HWSS_DCN201_H__ */