dc/dcn201/dcn201_dccg.c

0001 /*
0002  * Copyright 2018 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include "dcn201_dccg.h"
0027
0028 #include "reg_helper.h"
0029 #include "core_types.h"
0030
0031 #define TO_DCN_DCCG(dccg)\
0032     container_of(dccg, struct dcn_dccg, base)
0033
0034 #define REG(reg) \
0035     (dccg_dcn->regs->reg)
0036
0037 #undef FN
0038 #define FN(reg_name, field_name) \
0039     dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
0040
0041 #define CTX \
0042     dccg_dcn->base.ctx
0043
0044 #define DC_LOGGER \
0045     dccg->ctx->logger
0046
0047 static void dccg201_update_dpp_dto(struct dccg *dccg, int dpp_inst,
0048                    int req_dppclk)
0049 {
0050     /* vbios handles it */
0051 }
0052
0053 static const struct dccg_funcs dccg201_funcs = {
0054     .update_dpp_dto = dccg201_update_dpp_dto,
0055     .get_dccg_ref_freq = dccg2_get_dccg_ref_freq,
0056     .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
0057     .otg_add_pixel = dccg2_otg_add_pixel,
0058     .otg_drop_pixel = dccg2_otg_drop_pixel,
0059     .dccg_init = dccg2_init
0060 };
0061
0062 struct dccg *dccg201_create(
0063     struct dc_context *ctx,
0064     const struct dccg_registers *regs,
0065     const struct dccg_shift *dccg_shift,
0066     const struct dccg_mask *dccg_mask)
0067 {
0068     struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL);
0069     struct dccg *base;
0070
0071     if (dccg_dcn == NULL) {
0072         BREAK_TO_DEBUGGER();
0073         return NULL;
0074     }
0075
0076     base = &dccg_dcn->base;
0077     base->ctx = ctx;
0078     base->funcs = &dccg201_funcs;
0079
0080     dccg_dcn->regs = regs;
0081     dccg_dcn->dccg_shift = dccg_shift;
0082     dccg_dcn->dccg_mask = dccg_mask;
0083
0084     return &dccg_dcn->base;
0085 }