dc/dcn20/dcn20_vmid.h

0001 /*
0002  * Copyright 2018 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef DAL_DC_DCN20_DCN20_VMID_H_
0027 #define DAL_DC_DCN20_DCN20_VMID_H_
0028
0029 #include "vmid.h"
0030
0031 #define BASE_INNER(seg) \
0032     DCE_BASE__INST0_SEG ## seg
0033
0034 #define BASE(seg) \
0035     BASE_INNER(seg)
0036
0037 #define DCN20_VMID_REG_LIST(id)\
0038     SRI(CNTL, DCN_VM_CONTEXT, id),\
0039     SRI(PAGE_TABLE_BASE_ADDR_HI32, DCN_VM_CONTEXT, id),\
0040     SRI(PAGE_TABLE_BASE_ADDR_LO32, DCN_VM_CONTEXT, id),\
0041     SRI(PAGE_TABLE_START_ADDR_HI32, DCN_VM_CONTEXT, id),\
0042     SRI(PAGE_TABLE_START_ADDR_LO32, DCN_VM_CONTEXT, id),\
0043     SRI(PAGE_TABLE_END_ADDR_HI32, DCN_VM_CONTEXT, id),\
0044     SRI(PAGE_TABLE_END_ADDR_LO32, DCN_VM_CONTEXT, id)
0045
0046 #define DCN20_VMID_MASK_SH_LIST(mask_sh)\
0047     SF(DCN_VM_CONTEXT0_CNTL, VM_CONTEXT0_PAGE_TABLE_DEPTH, mask_sh),\
0048     SF(DCN_VM_CONTEXT0_CNTL, VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE, mask_sh),\
0049     SF(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\
0050     SF(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\
0051     SF(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4, mask_sh),\
0052     SF(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32, mask_sh),\
0053     SF(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4, mask_sh),\
0054     SF(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32, mask_sh)
0055
0056 #define DCN20_VMID_REG_FIELD_LIST(type)\
0057     type VM_CONTEXT0_PAGE_TABLE_DEPTH;\
0058     type VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE;\
0059     type VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32;\
0060     type VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32;\
0061     type VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4;\
0062     type VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32;\
0063     type VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4;\
0064     type VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32
0065
0066 struct dcn20_vmid_shift {
0067     DCN20_VMID_REG_FIELD_LIST(uint8_t);
0068 };
0069
0070 struct dcn20_vmid_mask {
0071     DCN20_VMID_REG_FIELD_LIST(uint32_t);
0072 };
0073
0074 struct dcn20_vmid {
0075     struct dc_context *ctx;
0076     const struct dcn_vmid_registers *regs;
0077     const struct dcn20_vmid_shift *shifts;
0078     const struct dcn20_vmid_mask *masks;
0079 };
0080
0081 void dcn20_vmid_setup(struct dcn20_vmid *vmid, const struct dcn_vmid_page_table_config *config);
0082
0083 #endif /* DAL_DC_DCN20_DCN20_VMID_H_ */