dc/dcn20/dcn20_vmid.c

0001 /*
0002  * Copyright 2018 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include <linux/delay.h>
0027
0028 #include "dcn20_vmid.h"
0029 #include "reg_helper.h"
0030
0031 #define REG(reg)\
0032     vmid->regs->reg
0033
0034 #define CTX \
0035     vmid->ctx
0036
0037 #undef FN
0038 #define FN(reg_name, field_name) \
0039     vmid->shifts->field_name, vmid->masks->field_name
0040
0041 static void dcn20_wait_for_vmid_ready(struct dcn20_vmid *vmid)
0042 {
0043     /* According the hardware spec, we need to poll for the lowest
0044      * bit of PAGE_TABLE_BASE_ADDR_LO32 = 1 any time a GPUVM
0045      * context is updated. We can't use REG_WAIT here since we
0046      * don't have a seperate field to wait on.
0047      *
0048      * TODO: Confirm timeout / poll interval with hardware team
0049      */
0050
0051     int max_times = 10000;
0052     int delay_us  = 5;
0053     int i;
0054
0055     for (i = 0; i < max_times; ++i) {
0056         uint32_t entry_lo32;
0057
0058         REG_GET(PAGE_TABLE_BASE_ADDR_LO32,
0059             VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32,
0060             &entry_lo32);
0061
0062         if (entry_lo32 & 0x1)
0063             return;
0064
0065         udelay(delay_us);
0066     }
0067
0068     /* VM setup timed out */
0069     DC_LOG_WARNING("Timeout while waiting for GPUVM context update\n");
0070     ASSERT(0);
0071 }
0072
0073 void dcn20_vmid_setup(struct dcn20_vmid *vmid, const struct dcn_vmid_page_table_config *config)
0074 {
0075     REG_SET(PAGE_TABLE_START_ADDR_HI32, 0,
0076             VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4, (config->page_table_start_addr >> 32) & 0xF);
0077     REG_SET(PAGE_TABLE_START_ADDR_LO32, 0,
0078             VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32, config->page_table_start_addr & 0xFFFFFFFF);
0079
0080     REG_SET(PAGE_TABLE_END_ADDR_HI32, 0,
0081             VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4, (config->page_table_end_addr >> 32) & 0xF);
0082     REG_SET(PAGE_TABLE_END_ADDR_LO32, 0,
0083             VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32, config->page_table_end_addr & 0xFFFFFFFF);
0084
0085     REG_SET_2(CNTL, 0,
0086             VM_CONTEXT0_PAGE_TABLE_DEPTH, config->depth,
0087             VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE, config->block_size);
0088
0089     REG_SET(PAGE_TABLE_BASE_ADDR_HI32, 0,
0090             VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32, (config->page_table_base_addr >> 32) & 0xFFFFFFFF);
0091     /* Note: per hardware spec PAGE_TABLE_BASE_ADDR_LO32 must be programmed last in sequence */
0092     REG_SET(PAGE_TABLE_BASE_ADDR_LO32, 0,
0093             VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32, config->page_table_base_addr & 0xFFFFFFFF);
0094
0095     dcn20_wait_for_vmid_ready(vmid);
0096 }