dc/dcn20/dcn20_stream_encoder.h

0001 /*
0002  * Copyright 2012-15 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  *  and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef __DC_STREAM_ENCODER_DCN20_H__
0027 #define __DC_STREAM_ENCODER_DCN20_H__
0028
0029 #include "stream_encoder.h"
0030 #include "dcn10/dcn10_stream_encoder.h"
0031
0032
0033 #define SE_DCN2_REG_LIST(id)\
0034     SE_COMMON_DCN_REG_LIST(id),\
0035     SRI(HDMI_GENERIC_PACKET_CONTROL4, DIG, id), \
0036     SRI(HDMI_GENERIC_PACKET_CONTROL5, DIG, id), \
0037     SRI(DP_DSC_CNTL, DP, id), \
0038     SRI(DP_DSC_BYTES_PER_PIXEL, DP, id), \
0039     SRI(DME_CONTROL, DIG, id),\
0040     SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \
0041     SRI(HDMI_METADATA_PACKET_CONTROL, DIG, id), \
0042     SRI(DP_SEC_FRAMING4, DP, id)
0043
0044 #define SE_COMMON_MASK_SH_LIST_DCN20(mask_sh)\
0045     SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\
0046     SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\
0047     SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\
0048     SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\
0049     SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\
0050     SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC2_CONT, mask_sh),\
0051     SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC2_SEND, mask_sh),\
0052     SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC3_CONT, mask_sh),\
0053     SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC3_SEND, mask_sh),\
0054     SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC4_CONT, mask_sh),\
0055     SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC4_SEND, mask_sh),\
0056     SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC5_CONT, mask_sh),\
0057     SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC5_SEND, mask_sh),\
0058     SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC6_CONT, mask_sh),\
0059     SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC6_SEND, mask_sh),\
0060     SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC7_CONT, mask_sh),\
0061     SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC7_SEND, mask_sh),\
0062     SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC0_LINE, mask_sh),\
0063     SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC1_LINE, mask_sh),\
0064     SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL2, HDMI_GENERIC2_LINE, mask_sh),\
0065     SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL2, HDMI_GENERIC3_LINE, mask_sh),\
0066     SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL3, HDMI_GENERIC4_LINE, mask_sh),\
0067     SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL3, HDMI_GENERIC5_LINE, mask_sh),\
0068     SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL4, HDMI_GENERIC6_LINE, mask_sh),\
0069     SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL4, HDMI_GENERIC7_LINE, mask_sh),\
0070     SE_SF(DP0_DP_DSC_CNTL, DP_DSC_MODE, mask_sh),\
0071     SE_SF(DP0_DP_DSC_CNTL, DP_DSC_SLICE_WIDTH, mask_sh),\
0072     SE_SF(DP0_DP_DSC_BYTES_PER_PIXEL, DP_DSC_BYTES_PER_PIXEL, mask_sh),\
0073     SE_SF(DP0_DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, mask_sh),\
0074     SE_SF(DP0_DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, mask_sh),\
0075     SE_SF(DIG0_DME_CONTROL, METADATA_ENGINE_EN, mask_sh),\
0076     SE_SF(DIG0_DME_CONTROL, METADATA_HUBP_REQUESTOR_ID, mask_sh),\
0077     SE_SF(DIG0_DME_CONTROL, METADATA_STREAM_TYPE, mask_sh),\
0078     SE_SF(DP0_DP_SEC_METADATA_TRANSMISSION, DP_SEC_METADATA_PACKET_ENABLE, mask_sh),\
0079     SE_SF(DP0_DP_SEC_METADATA_TRANSMISSION, DP_SEC_METADATA_PACKET_LINE_REFERENCE, mask_sh),\
0080     SE_SF(DP0_DP_SEC_METADATA_TRANSMISSION, DP_SEC_METADATA_PACKET_LINE, mask_sh),\
0081     SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_ENABLE, mask_sh),\
0082     SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_LINE_REFERENCE, mask_sh),\
0083     SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_LINE, mask_sh),\
0084     SE_SF(DIG0_DIG_FE_CNTL, DOLBY_VISION_EN, mask_sh),\
0085     SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_COMBINE, mask_sh),\
0086     SE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP5_LINE_REFERENCE, mask_sh),\
0087     SE_SF(DP0_DP_SEC_CNTL5, DP_SEC_GSP5_LINE_NUM, mask_sh),\
0088     SE_SF(DP0_DP_SEC_FRAMING4, DP_SST_SDP_SPLITTING, mask_sh)
0089
0090 void dcn20_stream_encoder_construct(
0091     struct dcn10_stream_encoder *enc1,
0092     struct dc_context *ctx,
0093     struct dc_bios *bp,
0094     enum engine_id eng_id,
0095     const struct dcn10_stream_enc_registers *regs,
0096     const struct dcn10_stream_encoder_shift *se_shift,
0097     const struct dcn10_stream_encoder_mask *se_mask);
0098
0099 void enc2_stream_encoder_dp_set_stream_attribute(
0100     struct stream_encoder *enc,
0101     struct dc_crtc_timing *crtc_timing,
0102     enum dc_color_space output_color_space,
0103     bool use_vsc_sdp_for_colorimetry,
0104     uint32_t enable_sdp_splitting);
0105
0106 void enc2_stream_encoder_dp_unblank(
0107     struct dc_link *link,
0108     struct stream_encoder *enc,
0109     const struct encoder_unblank_param *param);
0110
0111 void enc2_set_dynamic_metadata(struct stream_encoder *enc,
0112         bool enable_dme,
0113         uint32_t hubp_requestor_id,
0114         enum dynamic_metadata_mode dmdata_mode);
0115
0116 uint32_t enc2_get_fifo_cal_average_level(
0117         struct stream_encoder *enc);
0118
0119 #endif /* __DC_STREAM_ENCODER_DCN20_H__ */