dc/dcn20/dcn20_optc.h

0001 /*
0002  * Copyright 2012-15 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef __DC_OPTC_DCN20_H__
0027 #define __DC_OPTC_DCN20_H__
0028
0029 #include "../dcn10/dcn10_optc.h"
0030
0031 #define TG_COMMON_REG_LIST_DCN2_0(inst) \
0032     TG_COMMON_REG_LIST_DCN(inst),\
0033     SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
0034     SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
0035     SRI(OTG_GSL_WINDOW_X, OTG, inst),\
0036     SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
0037     SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
0038     SRI(OTG_DSC_START_POSITION, OTG, inst),\
0039     SRI(OTG_CRC_CNTL2, OTG, inst),\
0040     SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\
0041     SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\
0042     SRI(OPTC_WIDTH_CONTROL, ODM, inst),\
0043     SRI(OPTC_MEMORY_CONFIG, ODM, inst),\
0044     SR(DWB_SOURCE_SELECT),\
0045     SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst), \
0046     SRI(OTG_DRR_CONTROL, OTG, inst)
0047
0048 #define TG_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\
0049     TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\
0050     SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_X, mask_sh),\
0051     SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_Y, mask_sh),\
0052     SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
0053     SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
0054     SF(OTG0_OTG_GLOBAL_CONTROL2, DIG_UPDATE_LOCATION, mask_sh),\
0055     SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\
0056     SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
0057     SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
0058     SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
0059     SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
0060     SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \
0061     SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \
0062     SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \
0063     SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\
0064     SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DSC_MODE, mask_sh),\
0065     SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_COMBINE_MODE, mask_sh),\
0066     SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_SPLIT_MODE, mask_sh),\
0067     SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh),\
0068     SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\
0069     SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\
0070     SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\
0071     SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\
0072     SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\
0073     SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\
0074     SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\
0075     SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\
0076     SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\
0077     SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\
0078     SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh),\
0079     SF(OTG0_OTG_MANUAL_FLOW_CONTROL, MANUAL_FLOW_CONTROL, mask_sh), \
0080     SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh)
0081
0082 void dcn20_timing_generator_init(struct optc *optc);
0083
0084 void optc2_get_last_used_drr_vtotal(struct timing_generator *optc,
0085         uint32_t *refresh_rate);
0086
0087 bool optc2_enable_crtc(struct timing_generator *optc);
0088
0089 void optc2_set_gsl(struct timing_generator *optc,
0090         const struct gsl_params *params);
0091
0092 void optc2_set_gsl_source_select(struct timing_generator *optc,
0093         int group_idx,
0094         uint32_t gsl_ready_signal);
0095
0096 void optc2_set_dsc_config(struct timing_generator *optc,
0097                     enum optc_dsc_mode dsc_mode,
0098                     uint32_t dsc_bytes_per_pixel,
0099                     uint32_t dsc_slice_width);
0100
0101 void optc2_get_dsc_status(struct timing_generator *optc,
0102                     uint32_t *dsc_mode);
0103
0104 void optc2_set_odm_bypass(struct timing_generator *optc,
0105         const struct dc_crtc_timing *dc_crtc_timing);
0106
0107 void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
0108         struct dc_crtc_timing *timing);
0109
0110 void optc2_get_optc_source(struct timing_generator *optc,
0111         uint32_t *num_of_src_opp,
0112         uint32_t *src_opp_id_0,
0113         uint32_t *src_opp_id_1);
0114
0115 void optc2_triplebuffer_lock(struct timing_generator *optc);
0116 void optc2_triplebuffer_unlock(struct timing_generator *optc);
0117 void optc2_lock_doublebuffer_disable(struct timing_generator *optc);
0118 void optc2_lock_doublebuffer_enable(struct timing_generator *optc);
0119 void optc2_setup_manual_trigger(struct timing_generator *optc);
0120 void optc2_program_manual_trigger(struct timing_generator *optc);
0121 bool optc2_is_two_pixels_per_containter(const struct dc_crtc_timing *timing);
0122 bool optc2_configure_crc(struct timing_generator *optc,
0123               const struct crc_params *params);
0124 #endif /* __DC_OPTC_DCN20_H__ */