dc/dcn20/dcn20_optc.c

0001 /*
0002  * Copyright 2012-15 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include "reg_helper.h"
0027 #include "dcn20_optc.h"
0028 #include "dc.h"
0029
0030 #define REG(reg)\
0031     optc1->tg_regs->reg
0032
0033 #define CTX \
0034     optc1->base.ctx
0035
0036 #undef FN
0037 #define FN(reg_name, field_name) \
0038     optc1->tg_shift->field_name, optc1->tg_mask->field_name
0039
0040 /**
0041  * Enable CRTC
0042  * Enable CRTC - call ASIC Control Object to enable Timing generator.
0043  */
0044 bool optc2_enable_crtc(struct timing_generator *optc)
0045 {
0046     /* TODO FPGA wait for answer
0047      * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE
0048      * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK
0049      */
0050     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0051
0052     /* opp instance for OTG. For DCN1.0, ODM is remoed.
0053      * OPP and OPTC should 1:1 mapping
0054      */
0055     REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
0056             OPTC_SEG0_SRC_SEL, optc->inst);
0057
0058     /* VTG enable first is for HW workaround */
0059     REG_UPDATE(CONTROL,
0060             VTG0_ENABLE, 1);
0061
0062     REG_SEQ_START();
0063
0064     /* Enable CRTC */
0065     REG_UPDATE_2(OTG_CONTROL,
0066             OTG_DISABLE_POINT_CNTL, 3,
0067             OTG_MASTER_EN, 1);
0068
0069     REG_SEQ_SUBMIT();
0070     REG_SEQ_WAIT_DONE();
0071
0072     return true;
0073 }
0074
0075 /**
0076  *For the below, I'm not sure how your GSL parameters are stored in your env,
0077  * so I will assume a gsl_params struct for now
0078  */
0079 void optc2_set_gsl(struct timing_generator *optc,
0080            const struct gsl_params *params)
0081 {
0082     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0083
0084 /**
0085  * There are (MAX_OPTC+1)/2 gsl groups available for use.
0086  * In each group (assign an OTG to a group by setting OTG_GSLX_EN = 1,
0087  * set one of the OTGs to be the master (OTG_GSL_MASTER_EN = 1) and the rest are slaves.
0088  */
0089     REG_UPDATE_5(OTG_GSL_CONTROL,
0090         OTG_GSL0_EN, params->gsl0_en,
0091         OTG_GSL1_EN, params->gsl1_en,
0092         OTG_GSL2_EN, params->gsl2_en,
0093         OTG_GSL_MASTER_EN, params->gsl_master_en,
0094         OTG_GSL_MASTER_MODE, params->gsl_master_mode);
0095 }
0096
0097
0098 void optc2_set_gsl_source_select(
0099         struct timing_generator *optc,
0100         int group_idx,
0101         uint32_t gsl_ready_signal)
0102 {
0103     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0104
0105     switch (group_idx) {
0106     case 1:
0107         REG_UPDATE(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, gsl_ready_signal);
0108         break;
0109     case 2:
0110         REG_UPDATE(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, gsl_ready_signal);
0111         break;
0112     case 3:
0113         REG_UPDATE(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, gsl_ready_signal);
0114         break;
0115     default:
0116         break;
0117     }
0118 }
0119
0120 /* Set DSC-related configuration.
0121  *   dsc_mode: 0 disables DSC, other values enable DSC in specified format
0122  *   sc_bytes_per_pixel: Bytes per pixel in u3.28 format
0123  *   dsc_slice_width: Slice width in pixels
0124  */
0125 void optc2_set_dsc_config(struct timing_generator *optc,
0126                     enum optc_dsc_mode dsc_mode,
0127                     uint32_t dsc_bytes_per_pixel,
0128                     uint32_t dsc_slice_width)
0129 {
0130     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0131
0132     REG_UPDATE(OPTC_DATA_FORMAT_CONTROL,
0133         OPTC_DSC_MODE, dsc_mode);
0134
0135     REG_SET(OPTC_BYTES_PER_PIXEL, 0,
0136         OPTC_DSC_BYTES_PER_PIXEL, dsc_bytes_per_pixel);
0137
0138     REG_UPDATE(OPTC_WIDTH_CONTROL,
0139         OPTC_DSC_SLICE_WIDTH, dsc_slice_width);
0140 }
0141
0142 /* Get DSC-related configuration.
0143  *   dsc_mode: 0 disables DSC, other values enable DSC in specified format
0144  */
0145 void optc2_get_dsc_status(struct timing_generator *optc,
0146                     uint32_t *dsc_mode)
0147 {
0148     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0149
0150     REG_GET(OPTC_DATA_FORMAT_CONTROL,
0151         OPTC_DSC_MODE, dsc_mode);
0152 }
0153
0154
0155 /*TEMP: Need to figure out inheritance model here.*/
0156 bool optc2_is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
0157 {
0158     return optc1_is_two_pixels_per_containter(timing);
0159 }
0160
0161 void optc2_set_odm_bypass(struct timing_generator *optc,
0162         const struct dc_crtc_timing *dc_crtc_timing)
0163 {
0164     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0165     uint32_t h_div_2 = 0;
0166
0167     REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
0168             OPTC_NUM_OF_INPUT_SEGMENT, 0,
0169             OPTC_SEG0_SRC_SEL, optc->inst,
0170             OPTC_SEG1_SRC_SEL, 0xf);
0171     REG_WRITE(OTG_H_TIMING_CNTL, 0);
0172
0173     h_div_2 = optc2_is_two_pixels_per_containter(dc_crtc_timing);
0174     REG_UPDATE(OTG_H_TIMING_CNTL,
0175             OTG_H_TIMING_DIV_BY2, h_div_2);
0176     REG_SET(OPTC_MEMORY_CONFIG, 0,
0177             OPTC_MEM_SEL, 0);
0178     optc1->opp_count = 1;
0179 }
0180
0181 void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
0182         struct dc_crtc_timing *timing)
0183 {
0184     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0185     int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right)
0186             / opp_cnt;
0187     uint32_t memory_mask;
0188
0189     ASSERT(opp_cnt == 2);
0190
0191     /* TODO: In pseudocode but does not affect maximus, delete comment if we dont need on asic
0192      * REG_SET(OTG_GLOBAL_CONTROL2, 0, GLOBAL_UPDATE_LOCK_EN, 1);
0193      * Program OTG register MASTER_UPDATE_LOCK_DB_X/Y to the position before DP frame start
0194      * REG_SET_2(OTG_GLOBAL_CONTROL1, 0,
0195      *      MASTER_UPDATE_LOCK_DB_X, 160,
0196      *      MASTER_UPDATE_LOCK_DB_Y, 240);
0197      */
0198
0199     /* 2 pieces of memory required for up to 5120 displays, 4 for up to 8192,
0200      * however, for ODM combine we can simplify by always using 4.
0201      * To make sure there's no overlap, each instance "reserves" 2 memories and
0202      * they are uniquely combined here.
0203      */
0204     memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
0205
0206     if (REG(OPTC_MEMORY_CONFIG))
0207         REG_SET(OPTC_MEMORY_CONFIG, 0,
0208             OPTC_MEM_SEL, memory_mask);
0209
0210     REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
0211             OPTC_NUM_OF_INPUT_SEGMENT, 1,
0212             OPTC_SEG0_SRC_SEL, opp_id[0],
0213             OPTC_SEG1_SRC_SEL, opp_id[1]);
0214
0215     REG_UPDATE(OPTC_WIDTH_CONTROL,
0216             OPTC_SEGMENT_WIDTH, mpcc_hactive);
0217
0218     REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_BY2, 1);
0219     optc1->opp_count = opp_cnt;
0220 }
0221
0222 void optc2_get_optc_source(struct timing_generator *optc,
0223         uint32_t *num_of_src_opp,
0224         uint32_t *src_opp_id_0,
0225         uint32_t *src_opp_id_1)
0226 {
0227     uint32_t num_of_input_segments;
0228     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0229
0230     REG_GET_3(OPTC_DATA_SOURCE_SELECT,
0231             OPTC_NUM_OF_INPUT_SEGMENT, &num_of_input_segments,
0232             OPTC_SEG0_SRC_SEL, src_opp_id_0,
0233             OPTC_SEG1_SRC_SEL, src_opp_id_1);
0234
0235     if (num_of_input_segments == 1)
0236         *num_of_src_opp = 2;
0237     else
0238         *num_of_src_opp = 1;
0239
0240     /* Work around VBIOS not updating OPTC_NUM_OF_INPUT_SEGMENT */
0241     if (*src_opp_id_1 == 0xf)
0242         *num_of_src_opp = 1;
0243 }
0244
0245 static void optc2_set_dwb_source(struct timing_generator *optc,
0246                  uint32_t dwb_pipe_inst)
0247 {
0248     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0249
0250     if (dwb_pipe_inst == 0)
0251         REG_UPDATE(DWB_SOURCE_SELECT,
0252                 OPTC_DWB0_SOURCE_SELECT, optc->inst);
0253     else if (dwb_pipe_inst == 1)
0254         REG_UPDATE(DWB_SOURCE_SELECT,
0255                 OPTC_DWB1_SOURCE_SELECT, optc->inst);
0256 }
0257
0258 static void optc2_align_vblanks(
0259     struct timing_generator *optc_master,
0260     struct timing_generator *optc_slave,
0261     uint32_t master_pixel_clock_100Hz,
0262     uint32_t slave_pixel_clock_100Hz,
0263     uint8_t master_clock_divider,
0264     uint8_t slave_clock_divider)
0265 {
0266     /* accessing slave OTG registers */
0267     struct optc *optc1 = DCN10TG_FROM_TG(optc_slave);
0268
0269     uint32_t master_v_active = 0;
0270     uint32_t master_h_total = 0;
0271     uint32_t slave_h_total = 0;
0272     uint64_t L, XY;
0273     uint32_t X, Y, p = 10000;
0274     uint32_t master_update_lock;
0275
0276     /* disable slave OTG */
0277     REG_UPDATE(OTG_CONTROL, OTG_MASTER_EN, 0);
0278     /* wait until disabled */
0279     REG_WAIT(OTG_CONTROL,
0280              OTG_CURRENT_MASTER_EN_STATE,
0281              0, 10, 5000);
0282
0283     REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &slave_h_total);
0284
0285     /* assign slave OTG to be controlled by master update lock */
0286     REG_SET(OTG_GLOBAL_CONTROL0, 0,
0287             OTG_MASTER_UPDATE_LOCK_SEL, optc_master->inst);
0288
0289     /* accessing master OTG registers */
0290     optc1 = DCN10TG_FROM_TG(optc_master);
0291
0292     /* saving update lock state, not sure if it's needed */
0293     REG_GET(OTG_MASTER_UPDATE_LOCK,
0294             OTG_MASTER_UPDATE_LOCK, &master_update_lock);
0295     /* unlocking master OTG */
0296     REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
0297             OTG_MASTER_UPDATE_LOCK, 0);
0298
0299     REG_GET(OTG_V_BLANK_START_END,
0300             OTG_V_BLANK_START, &master_v_active);
0301     REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &master_h_total);
0302
0303     /* calculate when to enable slave OTG */
0304     L = (uint64_t)p * slave_h_total * master_pixel_clock_100Hz;
0305     L = div_u64(L, master_h_total);
0306     L = div_u64(L, slave_pixel_clock_100Hz);
0307     XY = div_u64(L, p);
0308     Y = master_v_active - XY - 1;
0309     X = div_u64(((XY + 1) * p - L) * master_h_total, p * master_clock_divider);
0310
0311     /*
0312      * set master OTG to unlock when V/H
0313      * counters reach calculated values
0314      */
0315     REG_UPDATE(OTG_GLOBAL_CONTROL1,
0316                MASTER_UPDATE_LOCK_DB_EN, 1);
0317     REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
0318                  MASTER_UPDATE_LOCK_DB_X,
0319                  X,
0320                  MASTER_UPDATE_LOCK_DB_Y,
0321                  Y);
0322
0323     /* lock master OTG */
0324     REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
0325             OTG_MASTER_UPDATE_LOCK, 1);
0326     REG_WAIT(OTG_MASTER_UPDATE_LOCK,
0327              UPDATE_LOCK_STATUS, 1, 1, 10);
0328
0329     /* accessing slave OTG registers */
0330     optc1 = DCN10TG_FROM_TG(optc_slave);
0331
0332     /*
0333      * enable slave OTG, the OTG is locked with
0334      * master's update lock, so it will not run
0335      */
0336     REG_UPDATE(OTG_CONTROL,
0337                OTG_MASTER_EN, 1);
0338
0339     /* accessing master OTG registers */
0340     optc1 = DCN10TG_FROM_TG(optc_master);
0341
0342     /*
0343      * unlock master OTG. When master H/V counters reach
0344      * DB_XY point, slave OTG will start
0345      */
0346     REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
0347             OTG_MASTER_UPDATE_LOCK, 0);
0348
0349     /* accessing slave OTG registers */
0350     optc1 = DCN10TG_FROM_TG(optc_slave);
0351
0352     /* wait for slave OTG to start running*/
0353     REG_WAIT(OTG_CONTROL,
0354              OTG_CURRENT_MASTER_EN_STATE,
0355              1, 10, 5000);
0356
0357     /* accessing master OTG registers */
0358     optc1 = DCN10TG_FROM_TG(optc_master);
0359
0360     /* disable the XY point*/
0361     REG_UPDATE(OTG_GLOBAL_CONTROL1,
0362                MASTER_UPDATE_LOCK_DB_EN, 0);
0363     REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
0364                  MASTER_UPDATE_LOCK_DB_X,
0365                  0,
0366                  MASTER_UPDATE_LOCK_DB_Y,
0367                  0);
0368
0369     /*restore master update lock*/
0370     REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
0371             OTG_MASTER_UPDATE_LOCK, master_update_lock);
0372
0373     /* accessing slave OTG registers */
0374     optc1 = DCN10TG_FROM_TG(optc_slave);
0375     /* restore slave to be controlled by it's own */
0376     REG_SET(OTG_GLOBAL_CONTROL0, 0,
0377             OTG_MASTER_UPDATE_LOCK_SEL, optc_slave->inst);
0378
0379 }
0380
0381 void optc2_triplebuffer_lock(struct timing_generator *optc)
0382 {
0383     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0384
0385     REG_SET(OTG_GLOBAL_CONTROL0, 0,
0386         OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
0387
0388     REG_SET(OTG_VUPDATE_KEEPOUT, 0,
0389         OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1);
0390
0391     REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
0392         OTG_MASTER_UPDATE_LOCK, 1);
0393
0394     if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
0395         REG_WAIT(OTG_MASTER_UPDATE_LOCK,
0396                 UPDATE_LOCK_STATUS, 1,
0397                 1, 10);
0398 }
0399
0400 void optc2_triplebuffer_unlock(struct timing_generator *optc)
0401 {
0402     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0403
0404     REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
0405         OTG_MASTER_UPDATE_LOCK, 0);
0406
0407     REG_SET(OTG_VUPDATE_KEEPOUT, 0,
0408         OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 0);
0409
0410 }
0411
0412 void optc2_lock_doublebuffer_enable(struct timing_generator *optc)
0413 {
0414     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0415     uint32_t v_blank_start = 0;
0416     uint32_t h_blank_start = 0;
0417
0418     REG_UPDATE(OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, 1);
0419
0420     REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1,
0421             DIG_UPDATE_LOCATION, 20);
0422
0423     REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_START, &v_blank_start);
0424
0425     REG_GET(OTG_H_BLANK_START_END, OTG_H_BLANK_START, &h_blank_start);
0426
0427     REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
0428             MASTER_UPDATE_LOCK_DB_X,
0429             (h_blank_start - 200 - 1) / optc1->opp_count,
0430             MASTER_UPDATE_LOCK_DB_Y,
0431             v_blank_start - 1);
0432
0433     REG_SET_3(OTG_VUPDATE_KEEPOUT, 0,
0434         MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, 0,
0435         MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, 100,
0436         OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1);
0437 }
0438
0439 void optc2_lock_doublebuffer_disable(struct timing_generator *optc)
0440 {
0441     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0442
0443     REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
0444                 MASTER_UPDATE_LOCK_DB_X,
0445                 0,
0446                 MASTER_UPDATE_LOCK_DB_Y,
0447                 0);
0448
0449     REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0,
0450                 DIG_UPDATE_LOCATION, 0);
0451
0452     REG_UPDATE(OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, 0);
0453 }
0454
0455 void optc2_setup_manual_trigger(struct timing_generator *optc)
0456 {
0457     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0458
0459     REG_SET_8(OTG_TRIGA_CNTL, 0,
0460             OTG_TRIGA_SOURCE_SELECT, 21,
0461             OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,
0462             OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1,
0463             OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0,
0464             OTG_TRIGA_POLARITY_SELECT, 0,
0465             OTG_TRIGA_FREQUENCY_SELECT, 0,
0466             OTG_TRIGA_DELAY, 0,
0467             OTG_TRIGA_CLEAR, 1);
0468 }
0469
0470 void optc2_program_manual_trigger(struct timing_generator *optc)
0471 {
0472     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0473
0474     REG_SET(OTG_TRIGA_MANUAL_TRIG, 0,
0475             OTG_TRIGA_MANUAL_TRIG, 1);
0476 }
0477
0478 bool optc2_configure_crc(struct timing_generator *optc,
0479               const struct crc_params *params)
0480 {
0481     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0482
0483     REG_SET_2(OTG_CRC_CNTL2, 0,
0484             OTG_CRC_DSC_MODE, params->dsc_mode,
0485             OTG_CRC_DATA_STREAM_COMBINE_MODE, params->odm_mode);
0486
0487     return optc1_configure_crc(optc, params);
0488 }
0489
0490
0491 void optc2_get_last_used_drr_vtotal(struct timing_generator *optc, uint32_t *refresh_rate)
0492 {
0493     struct optc *optc1 = DCN10TG_FROM_TG(optc);
0494
0495     REG_GET(OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, refresh_rate);
0496 }
0497
0498 static struct timing_generator_funcs dcn20_tg_funcs = {
0499         .validate_timing = optc1_validate_timing,
0500         .program_timing = optc1_program_timing,
0501         .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
0502         .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
0503         .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
0504         .program_global_sync = optc1_program_global_sync,
0505         .enable_crtc = optc2_enable_crtc,
0506         .disable_crtc = optc1_disable_crtc,
0507         /* used by enable_timing_synchronization. Not need for FPGA */
0508         .is_counter_moving = optc1_is_counter_moving,
0509         .get_position = optc1_get_position,
0510         .get_frame_count = optc1_get_vblank_counter,
0511         .get_scanoutpos = optc1_get_crtc_scanoutpos,
0512         .get_otg_active_size = optc1_get_otg_active_size,
0513         .set_early_control = optc1_set_early_control,
0514         /* used by enable_timing_synchronization. Not need for FPGA */
0515         .wait_for_state = optc1_wait_for_state,
0516         .set_blank = optc1_set_blank,
0517         .is_blanked = optc1_is_blanked,
0518         .set_blank_color = optc1_program_blank_color,
0519         .enable_reset_trigger = optc1_enable_reset_trigger,
0520         .enable_crtc_reset = optc1_enable_crtc_reset,
0521         .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
0522         .triplebuffer_lock = optc2_triplebuffer_lock,
0523         .triplebuffer_unlock = optc2_triplebuffer_unlock,
0524         .disable_reset_trigger = optc1_disable_reset_trigger,
0525         .lock = optc1_lock,
0526         .unlock = optc1_unlock,
0527         .lock_doublebuffer_enable = optc2_lock_doublebuffer_enable,
0528         .lock_doublebuffer_disable = optc2_lock_doublebuffer_disable,
0529         .enable_optc_clock = optc1_enable_optc_clock,
0530         .set_drr = optc1_set_drr,
0531         .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
0532         .set_static_screen_control = optc1_set_static_screen_control,
0533         .program_stereo = optc1_program_stereo,
0534         .is_stereo_left_eye = optc1_is_stereo_left_eye,
0535         .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer,
0536         .tg_init = optc1_tg_init,
0537         .is_tg_enabled = optc1_is_tg_enabled,
0538         .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
0539         .clear_optc_underflow = optc1_clear_optc_underflow,
0540         .setup_global_swap_lock = NULL,
0541         .get_crc = optc1_get_crc,
0542         .configure_crc = optc2_configure_crc,
0543         .set_dsc_config = optc2_set_dsc_config,
0544         .get_dsc_status = optc2_get_dsc_status,
0545         .set_dwb_source = optc2_set_dwb_source,
0546         .set_odm_bypass = optc2_set_odm_bypass,
0547         .set_odm_combine = optc2_set_odm_combine,
0548         .get_optc_source = optc2_get_optc_source,
0549         .set_gsl = optc2_set_gsl,
0550         .set_gsl_source_select = optc2_set_gsl_source_select,
0551         .set_vtg_params = optc1_set_vtg_params,
0552         .program_manual_trigger = optc2_program_manual_trigger,
0553         .setup_manual_trigger = optc2_setup_manual_trigger,
0554         .get_hw_timing = optc1_get_hw_timing,
0555         .align_vblanks = optc2_align_vblanks,
0556 };
0557
0558 void dcn20_timing_generator_init(struct optc *optc1)
0559 {
0560     optc1->base.funcs = &dcn20_tg_funcs;
0561
0562     optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
0563     optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
0564
0565     optc1->min_h_blank = 32;
0566     optc1->min_v_blank = 3;
0567     optc1->min_v_blank_interlace = 5;
0568     optc1->min_h_sync_width = 4;//  Minimum HSYNC = 8 pixels asked By HW in the first place for no actual reason. Oculus Rift S will not light up with 8 as it's hsyncWidth is 6. Changing it to 4 to fix that issue.
0569     optc1->min_v_sync_width = 1;
0570 }