dc/dcn20/dcn20_opp.h

0001 /* Copyright 2012-15 Advanced Micro Devices, Inc.
0002  *
0003  * Permission is hereby granted, free of charge, to any person obtaining a
0004  * copy of this software and associated documentation files (the "Software"),
0005  * to deal in the Software without restriction, including without limitation
0006  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0007  * and/or sell copies of the Software, and to permit persons to whom the
0008  * Software is furnished to do so, subject to the following conditions:
0009  *
0010  * The above copyright notice and this permission notice shall be included in
0011  * all copies or substantial portions of the Software.
0012  *
0013  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0014  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0015  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0016  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0017  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0018  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0019  * OTHER DEALINGS IN THE SOFTWARE.
0020  *
0021  * Authors: AMD
0022  *
0023  */
0024
0025 #ifndef __DC_OPP_DCN20_H__
0026 #define __DC_OPP_DCN20_H__
0027
0028 #include "dcn10/dcn10_opp.h"
0029
0030 #define TO_DCN20_OPP(opp)\
0031     container_of(opp, struct dcn20_opp, base)
0032
0033 #define OPP_SF(reg_name, field_name, post_fix)\
0034     .field_name = reg_name ## __ ## field_name ## post_fix
0035
0036 #define OPP_DPG_REG_LIST(id) \
0037     SRI(DPG_CONTROL, DPG, id), \
0038     SRI(DPG_DIMENSIONS, DPG, id), \
0039     SRI(DPG_OFFSET_SEGMENT, DPG, id), \
0040     SRI(DPG_COLOUR_B_CB, DPG, id), \
0041     SRI(DPG_COLOUR_G_Y, DPG, id), \
0042     SRI(DPG_COLOUR_R_CR, DPG, id), \
0043     SRI(DPG_RAMP_CONTROL, DPG, id), \
0044     SRI(DPG_STATUS, DPG, id)
0045
0046 #define OPP_REG_LIST_DCN20(id) \
0047     OPP_REG_LIST_DCN10(id), \
0048     OPP_DPG_REG_LIST(id), \
0049     SRI(FMT_422_CONTROL, FMT, id), \
0050     SRI(OPPBUF_CONTROL1, OPPBUF, id)
0051
0052 #define OPP_REG_VARIABLE_LIST_DCN2_0 \
0053     OPP_COMMON_REG_VARIABLE_LIST; \
0054     uint32_t FMT_422_CONTROL; \
0055     uint32_t DPG_CONTROL; \
0056     uint32_t DPG_DIMENSIONS; \
0057     uint32_t DPG_OFFSET_SEGMENT; \
0058     uint32_t DPG_COLOUR_B_CB; \
0059     uint32_t DPG_COLOUR_G_Y; \
0060     uint32_t DPG_COLOUR_R_CR; \
0061     uint32_t DPG_RAMP_CONTROL; \
0062     uint32_t DPG_STATUS
0063
0064 #define OPP_DPG_MASK_SH_LIST(mask_sh) \
0065     OPP_SF(DPG0_DPG_CONTROL, DPG_EN, mask_sh), \
0066     OPP_SF(DPG0_DPG_CONTROL, DPG_MODE, mask_sh), \
0067     OPP_SF(DPG0_DPG_CONTROL, DPG_DYNAMIC_RANGE, mask_sh), \
0068     OPP_SF(DPG0_DPG_CONTROL, DPG_BIT_DEPTH, mask_sh), \
0069     OPP_SF(DPG0_DPG_CONTROL, DPG_VRES, mask_sh), \
0070     OPP_SF(DPG0_DPG_CONTROL, DPG_HRES, mask_sh), \
0071     OPP_SF(DPG0_DPG_DIMENSIONS, DPG_ACTIVE_WIDTH, mask_sh), \
0072     OPP_SF(DPG0_DPG_DIMENSIONS, DPG_ACTIVE_HEIGHT, mask_sh), \
0073     OPP_SF(DPG0_DPG_OFFSET_SEGMENT, DPG_X_OFFSET, mask_sh), \
0074     OPP_SF(DPG0_DPG_OFFSET_SEGMENT, DPG_SEGMENT_WIDTH, mask_sh), \
0075     OPP_SF(DPG0_DPG_COLOUR_R_CR, DPG_COLOUR0_R_CR, mask_sh), \
0076     OPP_SF(DPG0_DPG_COLOUR_R_CR, DPG_COLOUR1_R_CR, mask_sh), \
0077     OPP_SF(DPG0_DPG_COLOUR_B_CB, DPG_COLOUR0_B_CB, mask_sh), \
0078     OPP_SF(DPG0_DPG_COLOUR_B_CB, DPG_COLOUR1_B_CB, mask_sh), \
0079     OPP_SF(DPG0_DPG_COLOUR_G_Y, DPG_COLOUR0_G_Y, mask_sh), \
0080     OPP_SF(DPG0_DPG_COLOUR_G_Y, DPG_COLOUR1_G_Y, mask_sh), \
0081     OPP_SF(DPG0_DPG_RAMP_CONTROL, DPG_RAMP0_OFFSET, mask_sh), \
0082     OPP_SF(DPG0_DPG_RAMP_CONTROL, DPG_INC0, mask_sh), \
0083     OPP_SF(DPG0_DPG_RAMP_CONTROL, DPG_INC1, mask_sh), \
0084     OPP_SF(DPG0_DPG_STATUS, DPG_DOUBLE_BUFFER_PENDING, mask_sh)
0085
0086 #define OPP_MASK_SH_LIST_DCN20(mask_sh) \
0087     OPP_MASK_SH_LIST_DCN(mask_sh), \
0088     OPP_DPG_MASK_SH_LIST(mask_sh), \
0089     OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_DISPLAY_SEGMENTATION, mask_sh),\
0090     OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_OVERLAP_PIXEL_NUM, mask_sh), \
0091     OPP_SF(FMT0_FMT_422_CONTROL, FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT, mask_sh)
0092
0093 #define OPP_DCN20_REG_FIELD_LIST(type) \
0094     OPP_DCN10_REG_FIELD_LIST(type); \
0095     type FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT; \
0096     type DPG_EN; \
0097     type DPG_MODE; \
0098     type DPG_DYNAMIC_RANGE; \
0099     type DPG_BIT_DEPTH; \
0100     type DPG_VRES; \
0101     type DPG_HRES; \
0102     type DPG_ACTIVE_WIDTH; \
0103     type DPG_ACTIVE_HEIGHT; \
0104     type DPG_X_OFFSET; \
0105     type DPG_SEGMENT_WIDTH; \
0106     type DPG_COLOUR0_R_CR; \
0107     type DPG_COLOUR1_R_CR; \
0108     type DPG_COLOUR0_B_CB; \
0109     type DPG_COLOUR1_B_CB; \
0110     type DPG_COLOUR0_G_Y; \
0111     type DPG_COLOUR1_G_Y; \
0112     type DPG_RAMP0_OFFSET; \
0113     type DPG_INC0; \
0114     type DPG_INC1; \
0115     type DPG_DOUBLE_BUFFER_PENDING
0116
0117 struct dcn20_opp_registers {
0118     OPP_REG_VARIABLE_LIST_DCN2_0;
0119 };
0120
0121 struct dcn20_opp_shift {
0122     OPP_DCN20_REG_FIELD_LIST(uint8_t);
0123 };
0124
0125 struct dcn20_opp_mask {
0126     OPP_DCN20_REG_FIELD_LIST(uint32_t);
0127 };
0128
0129 struct dcn20_opp {
0130     struct output_pixel_processor base;
0131
0132     const struct dcn20_opp_registers *regs;
0133     const struct dcn20_opp_shift *opp_shift;
0134     const struct dcn20_opp_mask *opp_mask;
0135
0136     bool is_write_to_ram_a_safe;
0137 };
0138
0139 void dcn20_opp_construct(struct dcn20_opp *oppn20,
0140     struct dc_context *ctx,
0141     uint32_t inst,
0142     const struct dcn20_opp_registers *regs,
0143     const struct dcn20_opp_shift *opp_shift,
0144     const struct dcn20_opp_mask *opp_mask);
0145
0146 void opp2_set_disp_pattern_generator(
0147     struct output_pixel_processor *opp,
0148     enum controller_dp_test_pattern test_pattern,
0149     enum controller_dp_color_space color_space,
0150     enum dc_color_depth color_depth,
0151     const struct tg_color *solid_color,
0152     int width,
0153     int height,
0154     int offset);
0155
0156 void opp2_program_dpg_dimensions(
0157         struct output_pixel_processor *opp,
0158         int width, int height);
0159
0160 bool opp2_dpg_is_blanked(struct output_pixel_processor *opp);
0161
0162 void opp2_dpg_set_blank_color(
0163         struct output_pixel_processor *opp,
0164         const struct tg_color *color);
0165
0166 void opp2_program_left_edge_extra_pixel (
0167         struct output_pixel_processor *opp,
0168         bool count);
0169
0170 #endif