dc/dcn20/dcn20_mpc.h

0001 /* Copyright 2012-15 Advanced Micro Devices, Inc.
0002  *
0003  * Permission is hereby granted, free of charge, to any person obtaining a
0004  * copy of this software and associated documentation files (the "Software"),
0005  * to deal in the Software without restriction, including without limitation
0006  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0007  * and/or sell copies of the Software, and to permit persons to whom the
0008  * Software is furnished to do so, subject to the following conditions:
0009  *
0010  * The above copyright notice and this permission notice shall be included in
0011  * all copies or substantial portions of the Software.
0012  *
0013  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0014  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0015  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0016  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0017  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0018  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0019  * OTHER DEALINGS IN THE SOFTWARE.
0020  *
0021  * Authors: AMD
0022  *
0023  */
0024
0025 #ifndef __DC_MPCC_DCN20_H__
0026 #define __DC_MPCC_DCN20_H__
0027
0028 #include "dcn10/dcn10_mpc.h"
0029
0030 #define TO_DCN20_MPC(mpc_base) \
0031     container_of(mpc_base, struct dcn20_mpc, base)
0032
0033 #define MPC_REG_LIST_DCN2_0(inst)\
0034     MPC_COMMON_REG_LIST_DCN1_0(inst),\
0035     SRII(MPCC_TOP_GAIN, MPCC, inst),\
0036     SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\
0037     SRII(MPCC_BOT_GAIN_OUTSIDE, MPCC, inst),\
0038     SRII(MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM, inst),\
0039     SRII(MPCC_OGAM_RAMA_START_CNTL_G, MPCC_OGAM, inst),\
0040     SRII(MPCC_OGAM_RAMA_START_CNTL_R, MPCC_OGAM, inst),\
0041     SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_B, MPCC_OGAM, inst),\
0042     SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_G, MPCC_OGAM, inst),\
0043     SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_R, MPCC_OGAM, inst),\
0044     SRII(MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM, inst),\
0045     SRII(MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM, inst),\
0046     SRII(MPCC_OGAM_RAMA_END_CNTL1_G, MPCC_OGAM, inst),\
0047     SRII(MPCC_OGAM_RAMA_END_CNTL2_G, MPCC_OGAM, inst),\
0048     SRII(MPCC_OGAM_RAMA_END_CNTL1_R, MPCC_OGAM, inst),\
0049     SRII(MPCC_OGAM_RAMA_END_CNTL2_R, MPCC_OGAM, inst),\
0050     SRII(MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM, inst),\
0051     SRII(MPCC_OGAM_RAMA_REGION_32_33, MPCC_OGAM, inst),\
0052     SRII(MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM, inst),\
0053     SRII(MPCC_OGAM_RAMB_START_CNTL_G, MPCC_OGAM, inst),\
0054     SRII(MPCC_OGAM_RAMB_START_CNTL_R, MPCC_OGAM, inst),\
0055     SRII(MPCC_OGAM_RAMB_SLOPE_CNTL_B, MPCC_OGAM, inst),\
0056     SRII(MPCC_OGAM_RAMB_SLOPE_CNTL_G, MPCC_OGAM, inst),\
0057     SRII(MPCC_OGAM_RAMB_SLOPE_CNTL_R, MPCC_OGAM, inst),\
0058     SRII(MPCC_OGAM_RAMB_END_CNTL1_B, MPCC_OGAM, inst),\
0059     SRII(MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM, inst),\
0060     SRII(MPCC_OGAM_RAMB_END_CNTL1_G, MPCC_OGAM, inst),\
0061     SRII(MPCC_OGAM_RAMB_END_CNTL2_G, MPCC_OGAM, inst),\
0062     SRII(MPCC_OGAM_RAMB_END_CNTL1_R, MPCC_OGAM, inst),\
0063     SRII(MPCC_OGAM_RAMB_END_CNTL2_R, MPCC_OGAM, inst),\
0064     SRII(MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM, inst),\
0065     SRII(MPCC_OGAM_RAMB_REGION_32_33, MPCC_OGAM, inst),\
0066     SRII(MPCC_MEM_PWR_CTRL, MPCC, inst),\
0067     SRII(MPCC_OGAM_LUT_INDEX, MPCC_OGAM, inst),\
0068     SRII(MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM, inst),\
0069     SRII(MPCC_OGAM_LUT_DATA, MPCC_OGAM, inst),\
0070     SRII(MPCC_OGAM_MODE, MPCC_OGAM, inst)
0071
0072 #define MPC_OUT_MUX_REG_LIST_DCN2_0(inst) \
0073     MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(inst),\
0074     SRII(CSC_MODE, MPC_OUT, inst),\
0075     SRII(CSC_C11_C12_A, MPC_OUT, inst),\
0076     SRII(CSC_C33_C34_A, MPC_OUT, inst),\
0077     SRII(CSC_C11_C12_B, MPC_OUT, inst),\
0078     SRII(CSC_C33_C34_B, MPC_OUT, inst),\
0079     SRII(DENORM_CONTROL, MPC_OUT, inst),\
0080     SRII(DENORM_CLAMP_G_Y, MPC_OUT, inst),\
0081     SRII(DENORM_CLAMP_B_CB, MPC_OUT, inst)
0082
0083 #define MPC_DBG_REG_LIST_DCN2_0() \
0084     SR(MPC_OCSC_TEST_DEBUG_DATA),\
0085     SR(MPC_OCSC_TEST_DEBUG_INDEX)
0086
0087 #define MPC_REG_VARIABLE_LIST_DCN2_0 \
0088     MPC_COMMON_REG_VARIABLE_LIST \
0089     uint32_t MPCC_TOP_GAIN[MAX_MPCC]; \
0090     uint32_t MPCC_BOT_GAIN_INSIDE[MAX_MPCC]; \
0091     uint32_t MPCC_BOT_GAIN_OUTSIDE[MAX_MPCC]; \
0092     uint32_t MPCC_OGAM_RAMA_START_CNTL_B[MAX_MPCC]; \
0093     uint32_t MPCC_OGAM_RAMA_START_CNTL_G[MAX_MPCC]; \
0094     uint32_t MPCC_OGAM_RAMA_START_CNTL_R[MAX_MPCC]; \
0095     uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_B[MAX_MPCC]; \
0096     uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_G[MAX_MPCC]; \
0097     uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_R[MAX_MPCC]; \
0098     uint32_t MPCC_OGAM_RAMA_END_CNTL1_B[MAX_MPCC]; \
0099     uint32_t MPCC_OGAM_RAMA_END_CNTL2_B[MAX_MPCC]; \
0100     uint32_t MPCC_OGAM_RAMA_END_CNTL1_G[MAX_MPCC]; \
0101     uint32_t MPCC_OGAM_RAMA_END_CNTL2_G[MAX_MPCC]; \
0102     uint32_t MPCC_OGAM_RAMA_END_CNTL1_R[MAX_MPCC]; \
0103     uint32_t MPCC_OGAM_RAMA_END_CNTL2_R[MAX_MPCC]; \
0104     uint32_t MPCC_OGAM_RAMA_REGION_0_1[MAX_MPCC]; \
0105     uint32_t MPCC_OGAM_RAMA_REGION_32_33[MAX_MPCC]; \
0106     uint32_t MPCC_OGAM_RAMB_START_CNTL_B[MAX_MPCC]; \
0107     uint32_t MPCC_OGAM_RAMB_START_CNTL_G[MAX_MPCC]; \
0108     uint32_t MPCC_OGAM_RAMB_START_CNTL_R[MAX_MPCC]; \
0109     uint32_t MPCC_OGAM_RAMB_SLOPE_CNTL_B[MAX_MPCC]; \
0110     uint32_t MPCC_OGAM_RAMB_SLOPE_CNTL_G[MAX_MPCC]; \
0111     uint32_t MPCC_OGAM_RAMB_SLOPE_CNTL_R[MAX_MPCC]; \
0112     uint32_t MPCC_OGAM_RAMB_END_CNTL1_B[MAX_MPCC]; \
0113     uint32_t MPCC_OGAM_RAMB_END_CNTL2_B[MAX_MPCC]; \
0114     uint32_t MPCC_OGAM_RAMB_END_CNTL1_G[MAX_MPCC]; \
0115     uint32_t MPCC_OGAM_RAMB_END_CNTL2_G[MAX_MPCC]; \
0116     uint32_t MPCC_OGAM_RAMB_END_CNTL1_R[MAX_MPCC]; \
0117     uint32_t MPCC_OGAM_RAMB_END_CNTL2_R[MAX_MPCC]; \
0118     uint32_t MPCC_OGAM_RAMB_REGION_0_1[MAX_MPCC]; \
0119     uint32_t MPCC_OGAM_RAMB_REGION_32_33[MAX_MPCC];\
0120     uint32_t MPCC_MEM_PWR_CTRL[MAX_MPCC];\
0121     uint32_t MPCC_OGAM_LUT_INDEX[MAX_MPCC];\
0122     uint32_t MPCC_OGAM_LUT_RAM_CONTROL[MAX_MPCC];\
0123     uint32_t MPCC_OGAM_LUT_DATA[MAX_MPCC];\
0124     uint32_t MPCC_OGAM_MODE[MAX_MPCC];\
0125     uint32_t MPC_OCSC_TEST_DEBUG_DATA;\
0126     uint32_t MPC_OCSC_TEST_DEBUG_INDEX;\
0127     uint32_t CSC_MODE[MAX_OPP]; \
0128     uint32_t CSC_C11_C12_A[MAX_OPP]; \
0129     uint32_t CSC_C33_C34_A[MAX_OPP]; \
0130     uint32_t CSC_C11_C12_B[MAX_OPP]; \
0131     uint32_t CSC_C33_C34_B[MAX_OPP]; \
0132     uint32_t DENORM_CONTROL[MAX_OPP]; \
0133     uint32_t DENORM_CLAMP_G_Y[MAX_OPP]; \
0134     uint32_t DENORM_CLAMP_B_CB[MAX_OPP];
0135
0136 #define MPC_COMMON_MASK_SH_LIST_DCN2_0(mask_sh) \
0137     MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh),\
0138     SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
0139     SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\
0140     SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\
0141     SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\
0142     SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\
0143     SF(MPC_OCSC_TEST_DEBUG_INDEX, MPC_OCSC_TEST_DEBUG_INDEX, mask_sh),\
0144     SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
0145     SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\
0146     SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\
0147     SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\
0148     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\
0149     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
0150     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\
0151     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
0152     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM_RAMA_EXP_REGION_END_B, mask_sh),\
0153     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\
0154     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh),\
0155     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh),\
0156     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_B, mask_sh),\
0157     SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\
0158     SF(MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh),\
0159     SF(MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
0160     SF(MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh),\
0161     SF(MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
0162     SF(MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B, MPCC_OGAM_RAMB_EXP_REGION_END_B, mask_sh),\
0163     SF(MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh),\
0164     SF(MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh),\
0165     SF(MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B, MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh),\
0166     SF(MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM_RAMB_EXP_REGION_START_B, mask_sh),\
0167     SF(MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh),\
0168     SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\
0169     SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\
0170     SF(MPCC_OGAM0_MPCC_OGAM_LUT_INDEX, MPCC_OGAM_LUT_INDEX, mask_sh),\
0171     SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_LUT_WRITE_EN_MASK, mask_sh),\
0172     SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_LUT_RAM_SEL, mask_sh),\
0173     SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_CONFIG_STATUS, mask_sh),\
0174     SF(MPCC_OGAM0_MPCC_OGAM_LUT_DATA, MPCC_OGAM_LUT_DATA, mask_sh),\
0175     SF(MPCC_OGAM0_MPCC_OGAM_MODE, MPCC_OGAM_MODE, mask_sh),\
0176     SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_MODE, mask_sh),\
0177     SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MAX_R_CR, mask_sh),\
0178     SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MIN_R_CR, mask_sh),\
0179     SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MAX_G_Y, mask_sh),\
0180     SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MIN_G_Y, mask_sh),\
0181     SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\
0182     SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh),\
0183     SF(CUR_VUPDATE_LOCK_SET0, CUR_VUPDATE_LOCK_SET, mask_sh)
0184
0185 /*
0186  *  DCN2 MPC_OCSC debug status register:
0187  *
0188  *      Status index including current OCSC Mode is 1
0189  *          OCSC Mode: [1..0]
0190  */
0191 #define MPC_OCSC_TEST_DEBUG_DATA_STATUS_IDX 1
0192
0193 #define MPC_DEBUG_REG_LIST_SH_DCN20 \
0194     .MPC_OCSC_TEST_DEBUG_DATA_OCSC_MODE = 0
0195
0196 #define MPC_DEBUG_REG_LIST_MASK_DCN20 \
0197     .MPC_OCSC_TEST_DEBUG_DATA_OCSC_MODE = 0x3
0198
0199 #define MPC_REG_FIELD_LIST_DCN2_0(type) \
0200     MPC_REG_FIELD_LIST(type)\
0201     type MPCC_BG_BPC;\
0202     type MPCC_BOT_GAIN_MODE;\
0203     type MPCC_TOP_GAIN;\
0204     type MPCC_BOT_GAIN_INSIDE;\
0205     type MPCC_BOT_GAIN_OUTSIDE;\
0206     type MPC_OCSC_TEST_DEBUG_DATA_OCSC_MODE;\
0207     type MPC_OCSC_TEST_DEBUG_INDEX;\
0208     type MPC_OCSC_MODE;\
0209     type MPC_OCSC_C11_A;\
0210     type MPC_OCSC_C12_A;\
0211     type MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;\
0212     type MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;\
0213     type MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;\
0214     type MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;\
0215     type MPCC_OGAM_RAMA_EXP_REGION_END_B;\
0216     type MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B;\
0217     type MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B;\
0218     type MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B;\
0219     type MPCC_OGAM_RAMA_EXP_REGION_START_B;\
0220     type MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;\
0221     type MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET;\
0222     type MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS;\
0223     type MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET;\
0224     type MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS;\
0225     type MPCC_OGAM_RAMB_EXP_REGION_END_B;\
0226     type MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B;\
0227     type MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B;\
0228     type MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;\
0229     type MPCC_OGAM_RAMB_EXP_REGION_START_B;\
0230     type MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B;\
0231     type MPCC_OGAM_MEM_PWR_FORCE;\
0232     type MPCC_OGAM_LUT_INDEX;\
0233     type MPCC_OGAM_LUT_WRITE_EN_MASK;\
0234     type MPCC_OGAM_LUT_RAM_SEL;\
0235     type MPCC_OGAM_CONFIG_STATUS;\
0236     type MPCC_OGAM_LUT_DATA;\
0237     type MPCC_OGAM_MODE;\
0238     type MPC_OUT_DENORM_MODE;\
0239     type MPC_OUT_DENORM_CLAMP_MAX_R_CR;\
0240     type MPC_OUT_DENORM_CLAMP_MIN_R_CR;\
0241     type MPC_OUT_DENORM_CLAMP_MAX_G_Y;\
0242     type MPC_OUT_DENORM_CLAMP_MIN_G_Y;\
0243     type MPC_OUT_DENORM_CLAMP_MAX_B_CB;\
0244     type MPC_OUT_DENORM_CLAMP_MIN_B_CB;\
0245     type MPCC_DISABLED;\
0246     type MPCC_OGAM_MEM_PWR_DIS;
0247
0248 struct dcn20_mpc_registers {
0249     MPC_REG_VARIABLE_LIST_DCN2_0
0250 };
0251
0252 struct dcn20_mpc_shift {
0253     MPC_REG_FIELD_LIST_DCN2_0(uint8_t)
0254 };
0255
0256 struct dcn20_mpc_mask {
0257     MPC_REG_FIELD_LIST_DCN2_0(uint32_t)
0258 };
0259
0260 struct dcn20_mpc {
0261     struct mpc base;
0262
0263     int mpcc_in_use_mask;
0264     int num_mpcc;
0265     const struct dcn20_mpc_registers *mpc_regs;
0266     const struct dcn20_mpc_shift *mpc_shift;
0267     const struct dcn20_mpc_mask *mpc_mask;
0268 };
0269
0270 void dcn20_mpc_construct(struct dcn20_mpc *mpcc20,
0271     struct dc_context *ctx,
0272     const struct dcn20_mpc_registers *mpc_regs,
0273     const struct dcn20_mpc_shift *mpc_shift,
0274     const struct dcn20_mpc_mask *mpc_mask,
0275     int num_mpcc);
0276
0277 void mpc2_update_blending(
0278     struct mpc *mpc,
0279     struct mpcc_blnd_cfg *blnd_cfg,
0280     int mpcc_id);
0281
0282 void mpc2_set_denorm(
0283     struct mpc *mpc,
0284     int opp_id,
0285     enum dc_color_depth output_depth);
0286
0287 void mpc2_set_denorm_clamp(
0288     struct mpc *mpc,
0289     int opp_id,
0290     struct mpc_denorm_clamp denorm_clamp);
0291
0292 void mpc2_set_output_csc(
0293     struct mpc *mpc,
0294     int opp_id,
0295     const uint16_t *regval,
0296     enum mpc_output_csc_mode ocsc_mode);
0297
0298 void mpc2_set_ocsc_default(
0299     struct mpc *mpc,
0300     int opp_id,
0301     enum dc_color_space color_space,
0302     enum mpc_output_csc_mode ocsc_mode);
0303
0304 void mpc2_set_output_gamma(
0305     struct mpc *mpc,
0306     int mpcc_id,
0307     const struct pwl_params *params);
0308
0309 void mpc2_assert_idle_mpcc(struct mpc *mpc, int id);
0310 void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id);
0311 void mpc20_power_on_ogam_lut(struct mpc *mpc, int mpcc_id, bool power_on);
0312 #endif