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0001 /*
0002  * Copyright 2012-15 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 
0026 #include "dcn20_mpc.h"
0027 
0028 #include "reg_helper.h"
0029 #include "dc.h"
0030 #include "mem_input.h"
0031 #include "dcn10/dcn10_cm_common.h"
0032 
0033 #define REG(reg)\
0034     mpc20->mpc_regs->reg
0035 
0036 #define IND_REG(index) \
0037     (index)
0038 
0039 #define CTX \
0040     mpc20->base.ctx
0041 
0042 #undef FN
0043 #define FN(reg_name, field_name) \
0044     mpc20->mpc_shift->field_name, mpc20->mpc_mask->field_name
0045 
0046 #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
0047 
0048 void mpc2_update_blending(
0049     struct mpc *mpc,
0050     struct mpcc_blnd_cfg *blnd_cfg,
0051     int mpcc_id)
0052 {
0053     struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
0054 
0055     struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id);
0056 
0057     REG_UPDATE_7(MPCC_CONTROL[mpcc_id],
0058             MPCC_ALPHA_BLND_MODE,       blnd_cfg->alpha_mode,
0059             MPCC_ALPHA_MULTIPLIED_MODE, blnd_cfg->pre_multiplied_alpha,
0060             MPCC_BLND_ACTIVE_OVERLAP_ONLY,  blnd_cfg->overlap_only,
0061             MPCC_GLOBAL_ALPHA,      blnd_cfg->global_alpha,
0062             MPCC_GLOBAL_GAIN,       blnd_cfg->global_gain,
0063             MPCC_BG_BPC,            blnd_cfg->background_color_bpc,
0064             MPCC_BOT_GAIN_MODE,     blnd_cfg->bottom_gain_mode);
0065 
0066     REG_SET(MPCC_TOP_GAIN[mpcc_id], 0, MPCC_TOP_GAIN, blnd_cfg->top_gain);
0067     REG_SET(MPCC_BOT_GAIN_INSIDE[mpcc_id], 0, MPCC_BOT_GAIN_INSIDE, blnd_cfg->bottom_inside_gain);
0068     REG_SET(MPCC_BOT_GAIN_OUTSIDE[mpcc_id], 0, MPCC_BOT_GAIN_OUTSIDE, blnd_cfg->bottom_outside_gain);
0069 
0070     mpcc->blnd_cfg = *blnd_cfg;
0071 }
0072 
0073 void mpc2_set_denorm(
0074         struct mpc *mpc,
0075         int opp_id,
0076         enum dc_color_depth output_depth)
0077 {
0078     struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
0079     int denorm_mode = 0;
0080 
0081     switch (output_depth) {
0082     case COLOR_DEPTH_666:
0083         denorm_mode = 1;
0084         break;
0085     case COLOR_DEPTH_888:
0086         denorm_mode = 2;
0087         break;
0088     case COLOR_DEPTH_999:
0089         denorm_mode = 3;
0090         break;
0091     case COLOR_DEPTH_101010:
0092         denorm_mode = 4;
0093         break;
0094     case COLOR_DEPTH_111111:
0095         denorm_mode = 5;
0096         break;
0097     case COLOR_DEPTH_121212:
0098         denorm_mode = 6;
0099         break;
0100     case COLOR_DEPTH_141414:
0101     case COLOR_DEPTH_161616:
0102     default:
0103         /* not valid used case! */
0104         break;
0105     }
0106 
0107     REG_UPDATE(DENORM_CONTROL[opp_id],
0108             MPC_OUT_DENORM_MODE, denorm_mode);
0109 }
0110 
0111 void mpc2_set_denorm_clamp(
0112         struct mpc *mpc,
0113         int opp_id,
0114         struct mpc_denorm_clamp denorm_clamp)
0115 {
0116     struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
0117 
0118     REG_UPDATE_2(DENORM_CONTROL[opp_id],
0119             MPC_OUT_DENORM_CLAMP_MAX_R_CR, denorm_clamp.clamp_max_r_cr,
0120             MPC_OUT_DENORM_CLAMP_MIN_R_CR, denorm_clamp.clamp_min_r_cr);
0121     REG_UPDATE_2(DENORM_CLAMP_G_Y[opp_id],
0122             MPC_OUT_DENORM_CLAMP_MAX_G_Y, denorm_clamp.clamp_max_g_y,
0123             MPC_OUT_DENORM_CLAMP_MIN_G_Y, denorm_clamp.clamp_min_g_y);
0124     REG_UPDATE_2(DENORM_CLAMP_B_CB[opp_id],
0125             MPC_OUT_DENORM_CLAMP_MAX_B_CB, denorm_clamp.clamp_max_b_cb,
0126             MPC_OUT_DENORM_CLAMP_MIN_B_CB, denorm_clamp.clamp_min_b_cb);
0127 }
0128 
0129 
0130 
0131 void mpc2_set_output_csc(
0132         struct mpc *mpc,
0133         int opp_id,
0134         const uint16_t *regval,
0135         enum mpc_output_csc_mode ocsc_mode)
0136 {
0137     uint32_t cur_mode;
0138     struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
0139     struct color_matrices_reg ocsc_regs;
0140 
0141     if (ocsc_mode == MPC_OUTPUT_CSC_DISABLE) {
0142         REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode);
0143         return;
0144     }
0145 
0146     if (regval == NULL) {
0147         BREAK_TO_DEBUGGER();
0148         return;
0149     }
0150 
0151     /* determine which CSC coefficients (A or B) we are using
0152      * currently.  select the alternate set to double buffer
0153      * the CSC update so CSC is updated on frame boundary
0154      */
0155     IX_REG_GET(MPC_OCSC_TEST_DEBUG_INDEX, MPC_OCSC_TEST_DEBUG_DATA,
0156                         MPC_OCSC_TEST_DEBUG_DATA_STATUS_IDX,
0157                         MPC_OCSC_TEST_DEBUG_DATA_OCSC_MODE, &cur_mode);
0158 
0159     if (cur_mode != MPC_OUTPUT_CSC_COEF_A)
0160         ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
0161     else
0162         ocsc_mode = MPC_OUTPUT_CSC_COEF_B;
0163 
0164     ocsc_regs.shifts.csc_c11 = mpc20->mpc_shift->MPC_OCSC_C11_A;
0165     ocsc_regs.masks.csc_c11  = mpc20->mpc_mask->MPC_OCSC_C11_A;
0166     ocsc_regs.shifts.csc_c12 = mpc20->mpc_shift->MPC_OCSC_C12_A;
0167     ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A;
0168 
0169     if (ocsc_mode == MPC_OUTPUT_CSC_COEF_A) {
0170         ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]);
0171         ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]);
0172     } else {
0173         ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_B[opp_id]);
0174         ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_B[opp_id]);
0175     }
0176 
0177     cm_helper_program_color_matrices(
0178             mpc20->base.ctx,
0179             regval,
0180             &ocsc_regs);
0181 
0182     REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode);
0183 }
0184 
0185 void mpc2_set_ocsc_default(
0186         struct mpc *mpc,
0187         int opp_id,
0188         enum dc_color_space color_space,
0189         enum mpc_output_csc_mode ocsc_mode)
0190 {
0191     uint32_t cur_mode;
0192     struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
0193     uint32_t arr_size;
0194     struct color_matrices_reg ocsc_regs;
0195     const uint16_t *regval = NULL;
0196 
0197     if (ocsc_mode == MPC_OUTPUT_CSC_DISABLE) {
0198         REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode);
0199         return;
0200     }
0201 
0202     regval = find_color_matrix(color_space, &arr_size);
0203 
0204     if (regval == NULL) {
0205         BREAK_TO_DEBUGGER();
0206         return;
0207     }
0208 
0209     /* determine which CSC coefficients (A or B) we are using
0210      * currently.  select the alternate set to double buffer
0211      * the CSC update so CSC is updated on frame boundary
0212      */
0213     IX_REG_GET(MPC_OCSC_TEST_DEBUG_INDEX, MPC_OCSC_TEST_DEBUG_DATA,
0214                         MPC_OCSC_TEST_DEBUG_DATA_STATUS_IDX,
0215                         MPC_OCSC_TEST_DEBUG_DATA_OCSC_MODE, &cur_mode);
0216 
0217     if (cur_mode != MPC_OUTPUT_CSC_COEF_A)
0218         ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
0219     else
0220         ocsc_mode = MPC_OUTPUT_CSC_COEF_B;
0221 
0222     ocsc_regs.shifts.csc_c11 = mpc20->mpc_shift->MPC_OCSC_C11_A;
0223     ocsc_regs.masks.csc_c11  = mpc20->mpc_mask->MPC_OCSC_C11_A;
0224     ocsc_regs.shifts.csc_c12 = mpc20->mpc_shift->MPC_OCSC_C12_A;
0225     ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A;
0226 
0227 
0228     if (ocsc_mode == MPC_OUTPUT_CSC_COEF_A) {
0229         ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]);
0230         ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]);
0231     } else {
0232         ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_B[opp_id]);
0233         ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_B[opp_id]);
0234     }
0235 
0236     cm_helper_program_color_matrices(
0237             mpc20->base.ctx,
0238             regval,
0239             &ocsc_regs);
0240 
0241     REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode);
0242 }
0243 
0244 static void mpc2_ogam_get_reg_field(
0245         struct mpc *mpc,
0246         struct xfer_func_reg *reg)
0247 {
0248     struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
0249 
0250     reg->shifts.exp_region0_lut_offset = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;
0251     reg->masks.exp_region0_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;
0252     reg->shifts.exp_region0_num_segments = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
0253     reg->masks.exp_region0_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
0254     reg->shifts.exp_region1_lut_offset = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;
0255     reg->masks.exp_region1_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;
0256     reg->shifts.exp_region1_num_segments = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
0257     reg->masks.exp_region1_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
0258     reg->shifts.field_region_end = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_B;
0259     reg->masks.field_region_end = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_B;
0260     reg->shifts.field_region_end_slope = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B;
0261     reg->masks.field_region_end_slope = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B;
0262     reg->shifts.field_region_end_base = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B;
0263     reg->masks.field_region_end_base = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B;
0264     reg->shifts.field_region_linear_slope = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B;
0265     reg->masks.field_region_linear_slope = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B;
0266     reg->shifts.exp_region_start = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_B;
0267     reg->masks.exp_region_start = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_B;
0268     reg->shifts.exp_resion_start_segment = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;
0269     reg->masks.exp_resion_start_segment = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;
0270 }
0271 
0272 void mpc20_power_on_ogam_lut(
0273         struct mpc *mpc, int mpcc_id,
0274         bool power_on)
0275 {
0276     struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
0277 
0278     REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0,
0279             MPCC_OGAM_MEM_PWR_DIS, power_on == true ? 1:0);
0280 
0281 }
0282 
0283 static void mpc20_configure_ogam_lut(
0284         struct mpc *mpc, int mpcc_id,
0285         bool is_ram_a)
0286 {
0287     struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
0288 
0289     REG_UPDATE_2(MPCC_OGAM_LUT_RAM_CONTROL[mpcc_id],
0290             MPCC_OGAM_LUT_WRITE_EN_MASK, 7,
0291             MPCC_OGAM_LUT_RAM_SEL, is_ram_a == true ? 0:1);
0292 
0293     REG_SET(MPCC_OGAM_LUT_INDEX[mpcc_id], 0, MPCC_OGAM_LUT_INDEX, 0);
0294 }
0295 
0296 static enum dc_lut_mode mpc20_get_ogam_current(struct mpc *mpc, int mpcc_id)
0297 {
0298     enum dc_lut_mode mode;
0299     uint32_t state_mode;
0300     struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
0301 
0302     REG_GET(MPCC_OGAM_LUT_RAM_CONTROL[mpcc_id], MPCC_OGAM_CONFIG_STATUS, &state_mode);
0303 
0304     switch (state_mode) {
0305     case 0:
0306         mode = LUT_BYPASS;
0307         break;
0308     case 1:
0309         mode = LUT_RAM_A;
0310         break;
0311     case 2:
0312         mode = LUT_RAM_B;
0313         break;
0314     default:
0315         mode = LUT_BYPASS;
0316         break;
0317     }
0318 
0319     return mode;
0320 }
0321 
0322 static void mpc2_program_lutb(struct mpc *mpc, int mpcc_id,
0323             const struct pwl_params *params)
0324 {
0325     struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
0326     struct xfer_func_reg gam_regs;
0327 
0328     mpc2_ogam_get_reg_field(mpc, &gam_regs);
0329 
0330     gam_regs.start_cntl_b = REG(MPCC_OGAM_RAMB_START_CNTL_B[mpcc_id]);
0331     gam_regs.start_cntl_g = REG(MPCC_OGAM_RAMB_START_CNTL_G[mpcc_id]);
0332     gam_regs.start_cntl_r = REG(MPCC_OGAM_RAMB_START_CNTL_R[mpcc_id]);
0333     gam_regs.start_slope_cntl_b = REG(MPCC_OGAM_RAMB_SLOPE_CNTL_B[mpcc_id]);
0334     gam_regs.start_slope_cntl_g = REG(MPCC_OGAM_RAMB_SLOPE_CNTL_G[mpcc_id]);
0335     gam_regs.start_slope_cntl_r = REG(MPCC_OGAM_RAMB_SLOPE_CNTL_R[mpcc_id]);
0336     gam_regs.start_end_cntl1_b = REG(MPCC_OGAM_RAMB_END_CNTL1_B[mpcc_id]);
0337     gam_regs.start_end_cntl2_b = REG(MPCC_OGAM_RAMB_END_CNTL2_B[mpcc_id]);
0338     gam_regs.start_end_cntl1_g = REG(MPCC_OGAM_RAMB_END_CNTL1_G[mpcc_id]);
0339     gam_regs.start_end_cntl2_g = REG(MPCC_OGAM_RAMB_END_CNTL2_G[mpcc_id]);
0340     gam_regs.start_end_cntl1_r = REG(MPCC_OGAM_RAMB_END_CNTL1_R[mpcc_id]);
0341     gam_regs.start_end_cntl2_r = REG(MPCC_OGAM_RAMB_END_CNTL2_R[mpcc_id]);
0342     gam_regs.region_start = REG(MPCC_OGAM_RAMB_REGION_0_1[mpcc_id]);
0343     gam_regs.region_end = REG(MPCC_OGAM_RAMB_REGION_32_33[mpcc_id]);
0344 
0345     cm_helper_program_xfer_func(mpc20->base.ctx, params, &gam_regs);
0346 
0347 }
0348 
0349 static void mpc2_program_luta(struct mpc *mpc, int mpcc_id,
0350         const struct pwl_params *params)
0351 {
0352     struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
0353     struct xfer_func_reg gam_regs;
0354 
0355     mpc2_ogam_get_reg_field(mpc, &gam_regs);
0356 
0357     gam_regs.start_cntl_b = REG(MPCC_OGAM_RAMA_START_CNTL_B[mpcc_id]);
0358     gam_regs.start_cntl_g = REG(MPCC_OGAM_RAMA_START_CNTL_G[mpcc_id]);
0359     gam_regs.start_cntl_r = REG(MPCC_OGAM_RAMA_START_CNTL_R[mpcc_id]);
0360     gam_regs.start_slope_cntl_b = REG(MPCC_OGAM_RAMA_SLOPE_CNTL_B[mpcc_id]);
0361     gam_regs.start_slope_cntl_g = REG(MPCC_OGAM_RAMA_SLOPE_CNTL_G[mpcc_id]);
0362     gam_regs.start_slope_cntl_r = REG(MPCC_OGAM_RAMA_SLOPE_CNTL_R[mpcc_id]);
0363     gam_regs.start_end_cntl1_b = REG(MPCC_OGAM_RAMA_END_CNTL1_B[mpcc_id]);
0364     gam_regs.start_end_cntl2_b = REG(MPCC_OGAM_RAMA_END_CNTL2_B[mpcc_id]);
0365     gam_regs.start_end_cntl1_g = REG(MPCC_OGAM_RAMA_END_CNTL1_G[mpcc_id]);
0366     gam_regs.start_end_cntl2_g = REG(MPCC_OGAM_RAMA_END_CNTL2_G[mpcc_id]);
0367     gam_regs.start_end_cntl1_r = REG(MPCC_OGAM_RAMA_END_CNTL1_R[mpcc_id]);
0368     gam_regs.start_end_cntl2_r = REG(MPCC_OGAM_RAMA_END_CNTL2_R[mpcc_id]);
0369     gam_regs.region_start = REG(MPCC_OGAM_RAMA_REGION_0_1[mpcc_id]);
0370     gam_regs.region_end = REG(MPCC_OGAM_RAMA_REGION_32_33[mpcc_id]);
0371 
0372     cm_helper_program_xfer_func(mpc20->base.ctx, params, &gam_regs);
0373 
0374 }
0375 
0376 static void mpc20_program_ogam_pwl(
0377         struct mpc *mpc, int mpcc_id,
0378         const struct pwl_result_data *rgb,
0379         uint32_t num)
0380 {
0381     uint32_t i;
0382     struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
0383 
0384     PERF_TRACE();
0385     REG_SEQ_START();
0386 
0387     for (i = 0 ; i < num; i++) {
0388         REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].red_reg);
0389         REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].green_reg);
0390         REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].blue_reg);
0391 
0392         REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0,
0393                 MPCC_OGAM_LUT_DATA, rgb[i].delta_red_reg);
0394         REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0,
0395                 MPCC_OGAM_LUT_DATA, rgb[i].delta_green_reg);
0396         REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0,
0397                 MPCC_OGAM_LUT_DATA, rgb[i].delta_blue_reg);
0398 
0399     }
0400 
0401 }
0402 
0403 static void apply_DEDCN20_305_wa(struct mpc *mpc, int mpcc_id,
0404                  enum dc_lut_mode current_mode,
0405                  enum dc_lut_mode next_mode)
0406 {
0407     struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
0408 
0409     if (mpc->ctx->dc->debug.cm_in_bypass) {
0410         REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0);
0411         return;
0412     }
0413 
0414     if (mpc->ctx->dc->work_arounds.dedcn20_305_wa == false) {
0415         /*hw fixed in new review*/
0416         return;
0417     }
0418     if (current_mode == LUT_BYPASS)
0419         /*this will only work if OTG is locked.
0420          *if we were to support OTG unlock case,
0421          *the workaround will be more complex
0422          */
0423         REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE,
0424             next_mode == LUT_RAM_A ? 1:2);
0425 }
0426 
0427 void mpc2_set_output_gamma(
0428         struct mpc *mpc,
0429         int mpcc_id,
0430         const struct pwl_params *params)
0431 {
0432     enum dc_lut_mode current_mode;
0433     enum dc_lut_mode next_mode;
0434     struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
0435 
0436     if (mpc->ctx->dc->debug.cm_in_bypass) {
0437         REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0);
0438         return;
0439     }
0440 
0441     if (params == NULL) {
0442         REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0);
0443         return;
0444     }
0445 
0446     current_mode = mpc20_get_ogam_current(mpc, mpcc_id);
0447     if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
0448         next_mode = LUT_RAM_B;
0449     else
0450         next_mode = LUT_RAM_A;
0451 
0452     mpc20_power_on_ogam_lut(mpc, mpcc_id, true);
0453     mpc20_configure_ogam_lut(mpc, mpcc_id, next_mode == LUT_RAM_A);
0454 
0455     if (next_mode == LUT_RAM_A)
0456         mpc2_program_luta(mpc, mpcc_id, params);
0457     else
0458         mpc2_program_lutb(mpc, mpcc_id, params);
0459 
0460     apply_DEDCN20_305_wa(mpc, mpcc_id, current_mode, next_mode);
0461 
0462     mpc20_program_ogam_pwl(
0463             mpc, mpcc_id, params->rgb_resulted, params->hw_points_num);
0464 
0465     REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE,
0466         next_mode == LUT_RAM_A ? 1:2);
0467 }
0468 void mpc2_assert_idle_mpcc(struct mpc *mpc, int id)
0469 {
0470     struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
0471     unsigned int mpc_disabled;
0472 
0473     ASSERT(!(mpc20->mpcc_in_use_mask & 1 << id));
0474     REG_GET(MPCC_STATUS[id], MPCC_DISABLED, &mpc_disabled);
0475     if (mpc_disabled)
0476         return;
0477 
0478     REG_WAIT(MPCC_STATUS[id],
0479             MPCC_IDLE, 1,
0480             1, 100000);
0481 }
0482 
0483 void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id)
0484 {
0485     struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
0486     unsigned int top_sel, mpc_busy, mpc_idle, mpc_disabled;
0487 
0488     REG_GET(MPCC_TOP_SEL[mpcc_id],
0489             MPCC_TOP_SEL, &top_sel);
0490 
0491     REG_GET_3(MPCC_STATUS[mpcc_id],
0492             MPCC_BUSY, &mpc_busy,
0493             MPCC_IDLE, &mpc_idle,
0494             MPCC_DISABLED, &mpc_disabled);
0495 
0496     if (top_sel == 0xf) {
0497         ASSERT(!mpc_busy);
0498         ASSERT(mpc_idle);
0499         ASSERT(mpc_disabled);
0500     } else {
0501         ASSERT(!mpc_disabled);
0502         ASSERT(!mpc_idle);
0503     }
0504 
0505     REG_SEQ_SUBMIT();
0506     PERF_TRACE();
0507     REG_SEQ_WAIT_DONE();
0508     PERF_TRACE();
0509 }
0510 
0511 static void mpc2_init_mpcc(struct mpcc *mpcc, int mpcc_inst)
0512 {
0513     mpcc->mpcc_id = mpcc_inst;
0514     mpcc->dpp_id = 0xf;
0515     mpcc->mpcc_bot = NULL;
0516     mpcc->blnd_cfg.overlap_only = false;
0517     mpcc->blnd_cfg.global_alpha = 0xff;
0518     mpcc->blnd_cfg.global_gain = 0xff;
0519     mpcc->blnd_cfg.background_color_bpc = 4;
0520     mpcc->blnd_cfg.bottom_gain_mode = 0;
0521     mpcc->blnd_cfg.top_gain = 0x1f000;
0522     mpcc->blnd_cfg.bottom_inside_gain = 0x1f000;
0523     mpcc->blnd_cfg.bottom_outside_gain = 0x1f000;
0524     mpcc->sm_cfg.enable = false;
0525 }
0526 
0527 static struct mpcc *mpc2_get_mpcc_for_dpp(struct mpc_tree *tree, int dpp_id)
0528 {
0529     struct mpcc *tmp_mpcc = tree->opp_list;
0530 
0531     while (tmp_mpcc != NULL) {
0532         if (tmp_mpcc->dpp_id == 0xf || tmp_mpcc->dpp_id == dpp_id)
0533             return tmp_mpcc;
0534 
0535         /* avoid circular linked list */
0536         ASSERT(tmp_mpcc != tmp_mpcc->mpcc_bot);
0537         if (tmp_mpcc == tmp_mpcc->mpcc_bot)
0538             break;
0539 
0540         tmp_mpcc = tmp_mpcc->mpcc_bot;
0541     }
0542     return NULL;
0543 }
0544 
0545 const struct mpc_funcs dcn20_mpc_funcs = {
0546     .read_mpcc_state = mpc1_read_mpcc_state,
0547     .insert_plane = mpc1_insert_plane,
0548     .remove_mpcc = mpc1_remove_mpcc,
0549     .mpc_init = mpc1_mpc_init,
0550     .mpc_init_single_inst = mpc1_mpc_init_single_inst,
0551     .update_blending = mpc2_update_blending,
0552     .cursor_lock = mpc1_cursor_lock,
0553     .get_mpcc_for_dpp = mpc2_get_mpcc_for_dpp,
0554     .wait_for_idle = mpc2_assert_idle_mpcc,
0555     .assert_mpcc_idle_before_connect = mpc2_assert_mpcc_idle_before_connect,
0556     .init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw,
0557     .set_denorm = mpc2_set_denorm,
0558     .set_denorm_clamp = mpc2_set_denorm_clamp,
0559     .set_output_csc = mpc2_set_output_csc,
0560     .set_ocsc_default = mpc2_set_ocsc_default,
0561     .set_output_gamma = mpc2_set_output_gamma,
0562     .power_on_mpc_mem_pwr = mpc20_power_on_ogam_lut,
0563     .get_mpc_out_mux = mpc1_get_mpc_out_mux,
0564     .set_bg_color = mpc1_set_bg_color,
0565 };
0566 
0567 void dcn20_mpc_construct(struct dcn20_mpc *mpc20,
0568     struct dc_context *ctx,
0569     const struct dcn20_mpc_registers *mpc_regs,
0570     const struct dcn20_mpc_shift *mpc_shift,
0571     const struct dcn20_mpc_mask *mpc_mask,
0572     int num_mpcc)
0573 {
0574     int i;
0575 
0576     mpc20->base.ctx = ctx;
0577 
0578     mpc20->base.funcs = &dcn20_mpc_funcs;
0579 
0580     mpc20->mpc_regs = mpc_regs;
0581     mpc20->mpc_shift = mpc_shift;
0582     mpc20->mpc_mask = mpc_mask;
0583 
0584     mpc20->mpcc_in_use_mask = 0;
0585     mpc20->num_mpcc = num_mpcc;
0586 
0587     for (i = 0; i < MAX_MPCC; i++)
0588         mpc2_init_mpcc(&mpc20->base.mpcc_array[i], i);
0589 }
0590
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