dc/dcn20/dcn20_mmhubbub.h

0001 /*
0002  * Copyright 2012-15 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef __DC_MCIF_WB_DCN20_H__
0027 #define __DC_MCIF_WB_DCN20_H__
0028
0029 #define TO_DCN20_MMHUBBUB(mcif_wb_base) \
0030     container_of(mcif_wb_base, struct dcn20_mmhubbub, base)
0031
0032 /* DCN */
0033 #define BASE_INNER(seg) \
0034     DCE_BASE__INST0_SEG ## seg
0035
0036 #define BASE(seg) \
0037     BASE_INNER(seg)
0038
0039 #define MCIF_WB_COMMON_REG_LIST_DCN2_0(inst) \
0040     SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
0041     SRI(MCIF_WB_BUFMGR_CUR_LINE_R, MCIF_WB, inst),\
0042     SRI(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst),\
0043     SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
0044     SRI(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst),\
0045     SRI(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst),\
0046     SRI(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst),\
0047     SRI(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst),\
0048     SRI(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst),\
0049     SRI(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst),\
0050     SRI(MCIF_WB_BUF_4_STATUS, MCIF_WB, inst),\
0051     SRI(MCIF_WB_BUF_4_STATUS2, MCIF_WB, inst),\
0052     SRI(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\
0053     SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\
0054     SRI(MCIF_WB_TEST_DEBUG_INDEX, MCIF_WB, inst),\
0055     SRI(MCIF_WB_TEST_DEBUG_DATA, MCIF_WB, inst),\
0056     SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\
0057     SRI(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB, inst),\
0058     SRI(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\
0059     SRI(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB, inst),\
0060     SRI(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\
0061     SRI(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB, inst),\
0062     SRI(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\
0063     SRI(MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB, inst),\
0064     SRI(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\
0065     SRI(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB, inst),\
0066     SRI(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\
0067     SRI(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB, inst),\
0068     SRI(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\
0069     SRI(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB, inst),\
0070     SRI(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\
0071     SRI(MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB, inst),\
0072     SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
0073     SRI(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MCIF_WB, inst),\
0074     SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\
0075     SRI(MCIF_WB_WATERMARK, MCIF_WB, inst),\
0076     SRI(MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB, inst),\
0077     SRI(MCIF_WB_WARM_UP_CNTL, MCIF_WB, inst),\
0078     SRI(MCIF_WB_SELF_REFRESH_CONTROL, MCIF_WB, inst),\
0079     SRI(MULTI_LEVEL_QOS_CTRL, MCIF_WB, inst),\
0080     SRI(MCIF_WB_SECURITY_LEVEL, MCIF_WB, inst),\
0081     SRI(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\
0082     SRI(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst),\
0083     SRI(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB, inst),\
0084     SRI(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB, inst),\
0085     SRI(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB, inst),\
0086     SRI(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB, inst),\
0087     SRI(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB, inst),\
0088     SRI(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB, inst),\
0089     SRI(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB, inst),\
0090     SRI(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB, inst),\
0091     SRI(MCIF_WB_BUF_1_RESOLUTION, MCIF_WB, inst),\
0092     SRI(MCIF_WB_BUF_2_RESOLUTION, MCIF_WB, inst),\
0093     SRI(MCIF_WB_BUF_3_RESOLUTION, MCIF_WB, inst),\
0094     SRI(MCIF_WB_BUF_4_RESOLUTION, MCIF_WB, inst),\
0095     SRI(SMU_WM_CONTROL, WBIF, inst)
0096
0097 #define MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(mask_sh) \
0098     SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
0099     SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
0100     SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
0101     SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
0102     SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
0103     SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
0104     SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\
0105     SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
0106     SF(MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R, MCIF_WB_BUFMGR_CUR_LINE_R, mask_sh),\
0107     SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_VCE_INT_STATUS, mask_sh),\
0108     SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_INT_STATUS, mask_sh),\
0109     SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS, mask_sh),\
0110     SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_CUR_BUF, mask_sh),\
0111     SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_BUFTAG, mask_sh),\
0112     SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_CUR_LINE_L, mask_sh),\
0113     SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_NEXT_BUF, mask_sh),\
0114     SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\
0115     SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_CHROMA_PITCH, mask_sh),\
0116     SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_ACTIVE, mask_sh),\
0117     SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_SW_LOCKED, mask_sh),\
0118     SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_VCE_LOCKED, mask_sh),\
0119     SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_OVERFLOW, mask_sh),\
0120     SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_DISABLE, mask_sh),\
0121     SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_MODE, mask_sh),\
0122     SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_BUFTAG, mask_sh),\
0123     SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_NXT_BUF, mask_sh),\
0124     SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_FIELD, mask_sh),\
0125     SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_CUR_LINE_L, mask_sh),\
0126     SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_LONG_LINE_ERROR, mask_sh),\
0127     SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_SHORT_LINE_ERROR, mask_sh),\
0128     SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_FRAME_LENGTH_ERROR, mask_sh),\
0129     SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_CUR_LINE_R, mask_sh),\
0130     SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_NEW_CONTENT, mask_sh),\
0131     SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_COLOR_DEPTH, mask_sh),\
0132     SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ_BLACK_PIXEL, mask_sh),\
0133     SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ, mask_sh),\
0134     SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_Y_OVERRUN, mask_sh),\
0135     SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_C_OVERRUN, mask_sh),\
0136     SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_ACTIVE, mask_sh),\
0137     SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_SW_LOCKED, mask_sh),\
0138     SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_VCE_LOCKED, mask_sh),\
0139     SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_OVERFLOW, mask_sh),\
0140     SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_DISABLE, mask_sh),\
0141     SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_MODE, mask_sh),\
0142     SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_BUFTAG, mask_sh),\
0143     SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_NXT_BUF, mask_sh),\
0144     SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_FIELD, mask_sh),\
0145     SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_CUR_LINE_L, mask_sh),\
0146     SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_LONG_LINE_ERROR, mask_sh),\
0147     SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_SHORT_LINE_ERROR, mask_sh),\
0148     SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_FRAME_LENGTH_ERROR, mask_sh),\
0149     SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_CUR_LINE_R, mask_sh),\
0150     SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_NEW_CONTENT, mask_sh),\
0151     SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_COLOR_DEPTH, mask_sh),\
0152     SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ_BLACK_PIXEL, mask_sh),\
0153     SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ, mask_sh),\
0154     SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_Y_OVERRUN, mask_sh),\
0155     SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_C_OVERRUN, mask_sh),\
0156     SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_ACTIVE, mask_sh),\
0157     SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_SW_LOCKED, mask_sh),\
0158     SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_VCE_LOCKED, mask_sh),\
0159     SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_OVERFLOW, mask_sh),\
0160     SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_DISABLE, mask_sh),\
0161     SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_MODE, mask_sh),\
0162     SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_BUFTAG, mask_sh),\
0163     SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_NXT_BUF, mask_sh),\
0164     SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_FIELD, mask_sh),\
0165     SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_CUR_LINE_L, mask_sh),\
0166     SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_LONG_LINE_ERROR, mask_sh),\
0167     SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_SHORT_LINE_ERROR, mask_sh),\
0168     SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_FRAME_LENGTH_ERROR, mask_sh),\
0169     SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_CUR_LINE_R, mask_sh),\
0170     SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_NEW_CONTENT, mask_sh),\
0171     SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_COLOR_DEPTH, mask_sh),\
0172     SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ_BLACK_PIXEL, mask_sh),\
0173     SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ, mask_sh),\
0174     SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_Y_OVERRUN, mask_sh),\
0175     SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_C_OVERRUN, mask_sh),\
0176     SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_ACTIVE, mask_sh),\
0177     SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_SW_LOCKED, mask_sh),\
0178     SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_VCE_LOCKED, mask_sh),\
0179     SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_OVERFLOW, mask_sh),\
0180     SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_DISABLE, mask_sh),\
0181     SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_MODE, mask_sh),\
0182     SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_BUFTAG, mask_sh),\
0183     SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_NXT_BUF, mask_sh),\
0184     SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_FIELD, mask_sh),\
0185     SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_CUR_LINE_L, mask_sh),\
0186     SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_LONG_LINE_ERROR, mask_sh),\
0187     SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_SHORT_LINE_ERROR, mask_sh),\
0188     SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_FRAME_LENGTH_ERROR, mask_sh),\
0189     SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_CUR_LINE_R, mask_sh),\
0190     SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_NEW_CONTENT, mask_sh),\
0191     SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_COLOR_DEPTH, mask_sh),\
0192     SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_TMZ_BLACK_PIXEL, mask_sh),\
0193     SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_TMZ, mask_sh),\
0194     SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_Y_OVERRUN, mask_sh),\
0195     SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_C_OVERRUN, mask_sh),\
0196     SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE, mask_sh),\
0197     SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, mask_sh),\
0198     SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, WM_CHANGE_ACK_FORCE_ON, mask_sh),\
0199     SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, mask_sh),\
0200     SF(MCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX, MCIF_WB_TEST_DEBUG_INDEX, mask_sh),\
0201     SF(MCIF_WB0_MCIF_WB_TEST_DEBUG_DATA, MCIF_WB_TEST_DEBUG_DATA, mask_sh),\
0202     SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, mask_sh),\
0203     SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB_BUF_1_ADDR_Y_OFFSET, mask_sh),\
0204     SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, mask_sh),\
0205     SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB_BUF_1_ADDR_C_OFFSET, mask_sh),\
0206     SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, mask_sh),\
0207     SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB_BUF_2_ADDR_Y_OFFSET, mask_sh),\
0208     SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, mask_sh),\
0209     SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB_BUF_2_ADDR_C_OFFSET, mask_sh),\
0210     SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, mask_sh),\
0211     SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB_BUF_3_ADDR_Y_OFFSET, mask_sh),\
0212     SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, mask_sh),\
0213     SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB_BUF_3_ADDR_C_OFFSET, mask_sh),\
0214     SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, mask_sh),\
0215     SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB_BUF_4_ADDR_Y_OFFSET, mask_sh),\
0216     SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, mask_sh),\
0217     SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB_BUF_4_ADDR_C_OFFSET, mask_sh),\
0218     SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK_IGNORE, mask_sh),\
0219     SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_EN, mask_sh),\
0220     SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_ACK, mask_sh),\
0221     SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN, mask_sh),\
0222     SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK, mask_sh),\
0223     SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, mask_sh),\
0224     SF(MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_REFRESH_WATERMARK, mask_sh),\
0225     SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\
0226     SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_FORCE_ON, mask_sh),\
0227     SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_ALLOW_FOR_URGENT, mask_sh),\
0228     SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
0229     SF(MCIF_WB0_MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, mask_sh),\
0230     SF(MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB_CLI_CLOCK_GATER_OVERRIDE, mask_sh),\
0231     SF(MCIF_WB0_MCIF_WB_WARM_UP_CNTL, MCIF_WB_PITCH_SIZE_WARMUP, mask_sh),\
0232     SF(MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL, DIS_REFRESH_UNDER_NBPREQ, mask_sh),\
0233     SF(MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL, PERFRAME_SELF_REFRESH, mask_sh),\
0234     SF(MCIF_WB0_MULTI_LEVEL_QOS_CTRL, MAX_SCALED_TIME_TO_URGENT, mask_sh),\
0235     SF(MCIF_WB0_MCIF_WB_SECURITY_LEVEL, MCIF_WB_SECURITY_LEVEL, mask_sh),\
0236     SF(MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, mask_sh),\
0237     SF(MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, mask_sh),\
0238     SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, mask_sh),\
0239     SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, mask_sh),\
0240     SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, mask_sh),\
0241     SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, mask_sh),\
0242     SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB_BUF_3_ADDR_Y_HIGH, mask_sh),\
0243     SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB_BUF_3_ADDR_C_HIGH, mask_sh),\
0244     SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB_BUF_4_ADDR_Y_HIGH, mask_sh),\
0245     SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB_BUF_4_ADDR_C_HIGH, mask_sh),\
0246     SF(MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION, MCIF_WB_BUF_1_RESOLUTION_WIDTH, mask_sh),\
0247     SF(MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION, MCIF_WB_BUF_1_RESOLUTION_HEIGHT, mask_sh),\
0248     SF(MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION, MCIF_WB_BUF_2_RESOLUTION_WIDTH, mask_sh),\
0249     SF(MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION, MCIF_WB_BUF_2_RESOLUTION_HEIGHT, mask_sh),\
0250     SF(MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION, MCIF_WB_BUF_3_RESOLUTION_WIDTH, mask_sh),\
0251     SF(MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION, MCIF_WB_BUF_3_RESOLUTION_HEIGHT, mask_sh),\
0252     SF(MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION, MCIF_WB_BUF_4_RESOLUTION_WIDTH, mask_sh),\
0253     SF(MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION, MCIF_WB_BUF_4_RESOLUTION_HEIGHT, mask_sh),\
0254     SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_SEL, mask_sh),\
0255     SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_REQ, mask_sh),\
0256     SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_ACK_INT_DIS, mask_sh),\
0257     SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_ACK_INT_STATUS, mask_sh)
0258
0259 #define MCIF_WB_REG_FIELD_LIST_DCN2_0(type) \
0260     type MCIF_WB_BUFMGR_ENABLE;\
0261     type MCIF_WB_BUFMGR_SW_INT_EN;\
0262     type MCIF_WB_BUFMGR_SW_INT_ACK;\
0263     type MCIF_WB_BUFMGR_SW_SLICE_INT_EN;\
0264     type MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN;\
0265     type MCIF_WB_BUFMGR_SW_LOCK;\
0266     type MCIF_WB_P_VMID;\
0267     type MCIF_WB_BUF_ADDR_FENCE_EN;\
0268     type MCIF_WB_BUFMGR_CUR_LINE_R;\
0269     type MCIF_WB_BUFMGR_VCE_INT_STATUS;\
0270     type MCIF_WB_BUFMGR_SW_INT_STATUS;\
0271     type MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS;\
0272     type MCIF_WB_BUFMGR_CUR_BUF;\
0273     type MCIF_WB_BUFMGR_BUFTAG;\
0274     type MCIF_WB_BUFMGR_CUR_LINE_L;\
0275     type MCIF_WB_BUFMGR_NEXT_BUF;\
0276     type MCIF_WB_BUF_LUMA_PITCH;\
0277     type MCIF_WB_BUF_CHROMA_PITCH;\
0278     type MCIF_WB_BUF_1_ACTIVE;\
0279     type MCIF_WB_BUF_1_SW_LOCKED;\
0280     type MCIF_WB_BUF_1_VCE_LOCKED;\
0281     type MCIF_WB_BUF_1_OVERFLOW;\
0282     type MCIF_WB_BUF_1_DISABLE;\
0283     type MCIF_WB_BUF_1_MODE;\
0284     type MCIF_WB_BUF_1_BUFTAG;\
0285     type MCIF_WB_BUF_1_NXT_BUF;\
0286     type MCIF_WB_BUF_1_FIELD;\
0287     type MCIF_WB_BUF_1_CUR_LINE_L;\
0288     type MCIF_WB_BUF_1_LONG_LINE_ERROR;\
0289     type MCIF_WB_BUF_1_SHORT_LINE_ERROR;\
0290     type MCIF_WB_BUF_1_FRAME_LENGTH_ERROR;\
0291     type MCIF_WB_BUF_1_CUR_LINE_R;\
0292     type MCIF_WB_BUF_1_NEW_CONTENT;\
0293     type MCIF_WB_BUF_1_COLOR_DEPTH;\
0294     type MCIF_WB_BUF_1_TMZ_BLACK_PIXEL;\
0295     type MCIF_WB_BUF_1_TMZ;\
0296     type MCIF_WB_BUF_1_Y_OVERRUN;\
0297     type MCIF_WB_BUF_1_C_OVERRUN;\
0298     type MCIF_WB_BUF_2_ACTIVE;\
0299     type MCIF_WB_BUF_2_SW_LOCKED;\
0300     type MCIF_WB_BUF_2_VCE_LOCKED;\
0301     type MCIF_WB_BUF_2_OVERFLOW;\
0302     type MCIF_WB_BUF_2_DISABLE;\
0303     type MCIF_WB_BUF_2_MODE;\
0304     type MCIF_WB_BUF_2_BUFTAG;\
0305     type MCIF_WB_BUF_2_NXT_BUF;\
0306     type MCIF_WB_BUF_2_FIELD;\
0307     type MCIF_WB_BUF_2_CUR_LINE_L;\
0308     type MCIF_WB_BUF_2_LONG_LINE_ERROR;\
0309     type MCIF_WB_BUF_2_SHORT_LINE_ERROR;\
0310     type MCIF_WB_BUF_2_FRAME_LENGTH_ERROR;\
0311     type MCIF_WB_BUF_2_CUR_LINE_R;\
0312     type MCIF_WB_BUF_2_NEW_CONTENT;\
0313     type MCIF_WB_BUF_2_COLOR_DEPTH;\
0314     type MCIF_WB_BUF_2_TMZ_BLACK_PIXEL;\
0315     type MCIF_WB_BUF_2_TMZ;\
0316     type MCIF_WB_BUF_2_Y_OVERRUN;\
0317     type MCIF_WB_BUF_2_C_OVERRUN;\
0318     type MCIF_WB_BUF_3_ACTIVE;\
0319     type MCIF_WB_BUF_3_SW_LOCKED;\
0320     type MCIF_WB_BUF_3_VCE_LOCKED;\
0321     type MCIF_WB_BUF_3_OVERFLOW;\
0322     type MCIF_WB_BUF_3_DISABLE;\
0323     type MCIF_WB_BUF_3_MODE;\
0324     type MCIF_WB_BUF_3_BUFTAG;\
0325     type MCIF_WB_BUF_3_NXT_BUF;\
0326     type MCIF_WB_BUF_3_FIELD;\
0327     type MCIF_WB_BUF_3_CUR_LINE_L;\
0328     type MCIF_WB_BUF_3_LONG_LINE_ERROR;\
0329     type MCIF_WB_BUF_3_SHORT_LINE_ERROR;\
0330     type MCIF_WB_BUF_3_FRAME_LENGTH_ERROR;\
0331     type MCIF_WB_BUF_3_CUR_LINE_R;\
0332     type MCIF_WB_BUF_3_NEW_CONTENT;\
0333     type MCIF_WB_BUF_3_COLOR_DEPTH;\
0334     type MCIF_WB_BUF_3_TMZ_BLACK_PIXEL;\
0335     type MCIF_WB_BUF_3_TMZ;\
0336     type MCIF_WB_BUF_3_Y_OVERRUN;\
0337     type MCIF_WB_BUF_3_C_OVERRUN;\
0338     type MCIF_WB_BUF_4_ACTIVE;\
0339     type MCIF_WB_BUF_4_SW_LOCKED;\
0340     type MCIF_WB_BUF_4_VCE_LOCKED;\
0341     type MCIF_WB_BUF_4_OVERFLOW;\
0342     type MCIF_WB_BUF_4_DISABLE;\
0343     type MCIF_WB_BUF_4_MODE;\
0344     type MCIF_WB_BUF_4_BUFTAG;\
0345     type MCIF_WB_BUF_4_NXT_BUF;\
0346     type MCIF_WB_BUF_4_FIELD;\
0347     type MCIF_WB_BUF_4_CUR_LINE_L;\
0348     type MCIF_WB_BUF_4_LONG_LINE_ERROR;\
0349     type MCIF_WB_BUF_4_SHORT_LINE_ERROR;\
0350     type MCIF_WB_BUF_4_FRAME_LENGTH_ERROR;\
0351     type MCIF_WB_BUF_4_CUR_LINE_R;\
0352     type MCIF_WB_BUF_4_NEW_CONTENT;\
0353     type MCIF_WB_BUF_4_COLOR_DEPTH;\
0354     type MCIF_WB_BUF_4_TMZ_BLACK_PIXEL;\
0355     type MCIF_WB_BUF_4_TMZ;\
0356     type MCIF_WB_BUF_4_Y_OVERRUN;\
0357     type MCIF_WB_BUF_4_C_OVERRUN;\
0358     type MCIF_WB_CLIENT_ARBITRATION_SLICE;\
0359     type MCIF_WB_TIME_PER_PIXEL;\
0360     type WM_CHANGE_ACK_FORCE_ON;\
0361     type MCIF_WB_CLI_WATERMARK_MASK;\
0362     type MCIF_WB_TEST_DEBUG_INDEX;\
0363     type MCIF_WB_TEST_DEBUG_DATA;\
0364     type MCIF_WB_BUF_1_ADDR_Y;\
0365     type MCIF_WB_BUF_1_ADDR_Y_OFFSET;\
0366     type MCIF_WB_BUF_1_ADDR_C;\
0367     type MCIF_WB_BUF_1_ADDR_C_OFFSET;\
0368     type MCIF_WB_BUF_2_ADDR_Y;\
0369     type MCIF_WB_BUF_2_ADDR_Y_OFFSET;\
0370     type MCIF_WB_BUF_2_ADDR_C;\
0371     type MCIF_WB_BUF_2_ADDR_C_OFFSET;\
0372     type MCIF_WB_BUF_3_ADDR_Y;\
0373     type MCIF_WB_BUF_3_ADDR_Y_OFFSET;\
0374     type MCIF_WB_BUF_3_ADDR_C;\
0375     type MCIF_WB_BUF_3_ADDR_C_OFFSET;\
0376     type MCIF_WB_BUF_4_ADDR_Y;\
0377     type MCIF_WB_BUF_4_ADDR_Y_OFFSET;\
0378     type MCIF_WB_BUF_4_ADDR_C;\
0379     type MCIF_WB_BUF_4_ADDR_C_OFFSET;\
0380     type MCIF_WB_BUFMGR_VCE_LOCK_IGNORE;\
0381     type MCIF_WB_BUFMGR_VCE_INT_EN;\
0382     type MCIF_WB_BUFMGR_VCE_INT_ACK;\
0383     type MCIF_WB_BUFMGR_VCE_SLICE_INT_EN;\
0384     type MCIF_WB_BUFMGR_VCE_LOCK;\
0385     type MCIF_WB_BUFMGR_SLICE_SIZE;\
0386     type NB_PSTATE_CHANGE_REFRESH_WATERMARK;\
0387     type NB_PSTATE_CHANGE_URGENT_DURING_REQUEST;\
0388     type NB_PSTATE_CHANGE_FORCE_ON;\
0389     type NB_PSTATE_ALLOW_FOR_URGENT;\
0390     type NB_PSTATE_CHANGE_WATERMARK_MASK;\
0391     type MCIF_WB_CLI_WATERMARK;\
0392     type MCIF_WB_CLI_CLOCK_GATER_OVERRIDE;\
0393     type MCIF_WB_PITCH_SIZE_WARMUP;\
0394     type DIS_REFRESH_UNDER_NBPREQ;\
0395     type PERFRAME_SELF_REFRESH;\
0396     type MAX_SCALED_TIME_TO_URGENT;\
0397     type MCIF_WB_SECURITY_LEVEL;\
0398     type MCIF_WB_BUF_LUMA_SIZE;\
0399     type MCIF_WB_BUF_CHROMA_SIZE;\
0400     type MCIF_WB_BUF_1_ADDR_Y_HIGH;\
0401     type MCIF_WB_BUF_1_ADDR_C_HIGH;\
0402     type MCIF_WB_BUF_2_ADDR_Y_HIGH;\
0403     type MCIF_WB_BUF_2_ADDR_C_HIGH;\
0404     type MCIF_WB_BUF_3_ADDR_Y_HIGH;\
0405     type MCIF_WB_BUF_3_ADDR_C_HIGH;\
0406     type MCIF_WB_BUF_4_ADDR_Y_HIGH;\
0407     type MCIF_WB_BUF_4_ADDR_C_HIGH;\
0408     type MCIF_WB_BUF_1_RESOLUTION_WIDTH;\
0409     type MCIF_WB_BUF_1_RESOLUTION_HEIGHT;\
0410     type MCIF_WB_BUF_2_RESOLUTION_WIDTH;\
0411     type MCIF_WB_BUF_2_RESOLUTION_HEIGHT;\
0412     type MCIF_WB_BUF_3_RESOLUTION_WIDTH;\
0413     type MCIF_WB_BUF_3_RESOLUTION_HEIGHT;\
0414     type MCIF_WB_BUF_4_RESOLUTION_WIDTH;\
0415     type MCIF_WB_BUF_4_RESOLUTION_HEIGHT;\
0416     type MCIF_WB0_WM_CHG_SEL;\
0417     type MCIF_WB0_WM_CHG_REQ;\
0418     type MCIF_WB0_WM_CHG_ACK_INT_DIS;\
0419     type MCIF_WB0_WM_CHG_ACK_INT_STATUS
0420
0421 #define MCIF_WB_REG_VARIABLE_LIST_DCN2_0 \
0422     uint32_t MCIF_WB_BUFMGR_SW_CONTROL;\
0423     uint32_t MCIF_WB_BUFMGR_CUR_LINE_R;\
0424     uint32_t MCIF_WB_BUFMGR_STATUS;\
0425     uint32_t MCIF_WB_BUF_PITCH;\
0426     uint32_t MCIF_WB_BUF_1_STATUS;\
0427     uint32_t MCIF_WB_BUF_1_STATUS2;\
0428     uint32_t MCIF_WB_BUF_2_STATUS;\
0429     uint32_t MCIF_WB_BUF_2_STATUS2;\
0430     uint32_t MCIF_WB_BUF_3_STATUS;\
0431     uint32_t MCIF_WB_BUF_3_STATUS2;\
0432     uint32_t MCIF_WB_BUF_4_STATUS;\
0433     uint32_t MCIF_WB_BUF_4_STATUS2;\
0434     uint32_t MCIF_WB_ARBITRATION_CONTROL;\
0435     uint32_t MCIF_WB_SCLK_CHANGE;\
0436     uint32_t MCIF_WB_TEST_DEBUG_INDEX;\
0437     uint32_t MCIF_WB_TEST_DEBUG_DATA;\
0438     uint32_t MCIF_WB_BUF_1_ADDR_Y;\
0439     uint32_t MCIF_WB_BUF_1_ADDR_Y_OFFSET;\
0440     uint32_t MCIF_WB_BUF_1_ADDR_C;\
0441     uint32_t MCIF_WB_BUF_1_ADDR_C_OFFSET;\
0442     uint32_t MCIF_WB_BUF_2_ADDR_Y;\
0443     uint32_t MCIF_WB_BUF_2_ADDR_Y_OFFSET;\
0444     uint32_t MCIF_WB_BUF_2_ADDR_C;\
0445     uint32_t MCIF_WB_BUF_2_ADDR_C_OFFSET;\
0446     uint32_t MCIF_WB_BUF_3_ADDR_Y;\
0447     uint32_t MCIF_WB_BUF_3_ADDR_Y_OFFSET;\
0448     uint32_t MCIF_WB_BUF_3_ADDR_C;\
0449     uint32_t MCIF_WB_BUF_3_ADDR_C_OFFSET;\
0450     uint32_t MCIF_WB_BUF_4_ADDR_Y;\
0451     uint32_t MCIF_WB_BUF_4_ADDR_Y_OFFSET;\
0452     uint32_t MCIF_WB_BUF_4_ADDR_C;\
0453     uint32_t MCIF_WB_BUF_4_ADDR_C_OFFSET;\
0454     uint32_t MCIF_WB_BUFMGR_VCE_CONTROL;\
0455     uint32_t MCIF_WB_NB_PSTATE_LATENCY_WATERMARK;\
0456     uint32_t MCIF_WB_NB_PSTATE_CONTROL;\
0457     uint32_t MCIF_WB_WATERMARK;\
0458     uint32_t MCIF_WB_CLOCK_GATER_CONTROL;\
0459     uint32_t MCIF_WB_WARM_UP_CNTL;\
0460     uint32_t MCIF_WB_SELF_REFRESH_CONTROL;\
0461     uint32_t MULTI_LEVEL_QOS_CTRL;\
0462     uint32_t MCIF_WB_SECURITY_LEVEL;\
0463     uint32_t MCIF_WB_BUF_LUMA_SIZE;\
0464     uint32_t MCIF_WB_BUF_CHROMA_SIZE;\
0465     uint32_t MCIF_WB_BUF_1_ADDR_Y_HIGH;\
0466     uint32_t MCIF_WB_BUF_1_ADDR_C_HIGH;\
0467     uint32_t MCIF_WB_BUF_2_ADDR_Y_HIGH;\
0468     uint32_t MCIF_WB_BUF_2_ADDR_C_HIGH;\
0469     uint32_t MCIF_WB_BUF_3_ADDR_Y_HIGH;\
0470     uint32_t MCIF_WB_BUF_3_ADDR_C_HIGH;\
0471     uint32_t MCIF_WB_BUF_4_ADDR_Y_HIGH;\
0472     uint32_t MCIF_WB_BUF_4_ADDR_C_HIGH;\
0473     uint32_t MCIF_WB_BUF_1_RESOLUTION;\
0474     uint32_t MCIF_WB_BUF_2_RESOLUTION;\
0475     uint32_t MCIF_WB_BUF_3_RESOLUTION;\
0476     uint32_t MCIF_WB_BUF_4_RESOLUTION;\
0477     uint32_t SMU_WM_CONTROL
0478
0479 struct dcn20_mmhubbub_registers {
0480     MCIF_WB_REG_VARIABLE_LIST_DCN2_0;
0481 };
0482
0483
0484 struct dcn20_mmhubbub_mask {
0485     MCIF_WB_REG_FIELD_LIST_DCN2_0(uint32_t);
0486 };
0487
0488 struct dcn20_mmhubbub_shift {
0489     MCIF_WB_REG_FIELD_LIST_DCN2_0(uint8_t);
0490 };
0491
0492 struct dcn20_mmhubbub {
0493     struct mcif_wb base;
0494     const struct dcn20_mmhubbub_registers *mcif_wb_regs;
0495     const struct dcn20_mmhubbub_shift *mcif_wb_shift;
0496     const struct dcn20_mmhubbub_mask *mcif_wb_mask;
0497 };
0498
0499 void mmhubbub2_config_mcif_irq(struct mcif_wb *mcif_wb,
0500     struct mcif_irq_params *params);
0501
0502 void mmhubbub2_enable_mcif(struct mcif_wb *mcif_wb);
0503
0504 void mmhubbub2_disable_mcif(struct mcif_wb *mcif_wb);
0505
0506 void mcifwb2_dump_frame(struct mcif_wb *mcif_wb,
0507     struct mcif_buf_params *mcif_params,
0508     enum dwb_scaler_mode out_format,
0509     unsigned int dest_width,
0510     unsigned int dest_height,
0511     struct mcif_wb_frame_dump_info *dump_info,
0512     unsigned char *luma_buffer,
0513     unsigned char *chroma_buffer,
0514     unsigned char *dest_luma_buffer,
0515     unsigned char *dest_chroma_buffer);
0516
0517 void dcn20_mmhubbub_construct(struct dcn20_mmhubbub *mcif_wb20,
0518     struct dc_context *ctx,
0519     const struct dcn20_mmhubbub_registers *mcif_wb_regs,
0520     const struct dcn20_mmhubbub_shift *mcif_wb_shift,
0521     const struct dcn20_mmhubbub_mask *mcif_wb_mask,
0522     int inst);
0523
0524 #endif