dc/dcn20/dcn20_mmhubbub.c

0001 /*
0002  * Copyright 2012-15 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026
0027 #include "reg_helper.h"
0028 #include "resource.h"
0029 #include "mcif_wb.h"
0030 #include "dcn20_mmhubbub.h"
0031
0032
0033 #define REG(reg)\
0034     mcif_wb20->mcif_wb_regs->reg
0035
0036 #define CTX \
0037     mcif_wb20->base.ctx
0038
0039 #undef FN
0040 #define FN(reg_name, field_name) \
0041     mcif_wb20->mcif_wb_shift->field_name, mcif_wb20->mcif_wb_mask->field_name
0042
0043 #define MCIF_ADDR(addr) (((unsigned long long)addr & 0xffffffffff) + 0xFE) >> 8
0044 #define MCIF_ADDR_HIGH(addr) (unsigned long long)addr >> 40
0045
0046 /* wbif programming guide:
0047  * 1. set up wbif parameter:
0048  *    unsigned long long   luma_address[4];       //4 frame buffer
0049  *    unsigned long long   chroma_address[4];
0050  *    unsigned int     luma_pitch;
0051  *    unsigned int     chroma_pitch;
0052  *    unsigned int         warmup_pitch=0x10;     //256B align, the page size is 4KB when it is 0x10
0053  *    unsigned int     slice_lines;           //slice size
0054  *    unsigned int         time_per_pixel;        // time per pixel, in ns
0055  *    unsigned int         arbitration_slice;     // 0: 512 bytes 1: 1024 bytes 2: 2048 Bytes
0056  *    unsigned int         max_scaled_time;       // used for QOS generation
0057  *    unsigned int         swlock=0x0;
0058  *    unsigned int         cli_watermark[4];      //4 group urgent watermark
0059  *    unsigned int         pstate_watermark[4];   //4 group pstate watermark
0060  *    unsigned int         sw_int_en;             // Software interrupt enable, frame end and overflow
0061  *    unsigned int         sw_slice_int_en;       // slice end interrupt enable
0062  *    unsigned int         sw_overrun_int_en;     // overrun error interrupt enable
0063  *    unsigned int         vce_int_en;            // VCE interrupt enable, frame end and overflow
0064  *    unsigned int         vce_slice_int_en;      // VCE slice end interrupt enable, frame end and overflow
0065  *
0066  * 2. configure wbif register
0067  *    a. call mmhubbub_config_wbif()
0068  *
0069  * 3. Enable wbif
0070  *    call set_wbif_bufmgr_enable();
0071  *
0072  * 4. wbif_dump_status(), option, for debug purpose
0073  *    the bufmgr status can show the progress of write back, can be used for debug purpose
0074  */
0075
0076 static void mmhubbub2_config_mcif_buf(struct mcif_wb *mcif_wb,
0077         struct mcif_buf_params *params,
0078         unsigned int dest_height)
0079 {
0080     struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb);
0081
0082     /* sw lock buffer0~buffer3, default is 0 */
0083     REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, params->swlock);
0084
0085     /* buffer address for packing mode or Luma in planar mode */
0086     REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, MCIF_ADDR(params->luma_address[0]));
0087     REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[0]));
0088     /* right eye sub-buffer address offset for packing mode or Luma in planar mode */
0089     REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB_BUF_1_ADDR_Y_OFFSET, 0);
0090
0091     /* buffer address for Chroma in planar mode (unused in packing mode) */
0092     REG_UPDATE(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, MCIF_ADDR(params->chroma_address[0]));
0093     REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[0]));
0094     /* right eye offset for packing mode or Luma in planar mode */
0095     REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB_BUF_1_ADDR_C_OFFSET, 0);
0096
0097     /* buffer address for packing mode or Luma in planar mode */
0098     REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, MCIF_ADDR(params->luma_address[1]));
0099     REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[1]));
0100     /* right eye sub-buffer address offset for packing mode or Luma in planar mode */
0101     REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB_BUF_2_ADDR_Y_OFFSET, 0);
0102
0103     /* buffer address for Chroma in planar mode (unused in packing mode) */
0104     REG_UPDATE(MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, MCIF_ADDR(params->chroma_address[1]));
0105     REG_UPDATE(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[1]));
0106     /* right eye offset for packing mode or Luma in planar mode */
0107     REG_UPDATE(MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB_BUF_2_ADDR_C_OFFSET, 0);
0108
0109     /* buffer address for packing mode or Luma in planar mode */
0110     REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, MCIF_ADDR(params->luma_address[2]));
0111     REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[2]));
0112     /* right eye sub-buffer address offset for packing mode or Luma in planar mode */
0113     REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB_BUF_3_ADDR_Y_OFFSET, 0);
0114
0115     /* buffer address for Chroma in planar mode (unused in packing mode) */
0116     REG_UPDATE(MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, MCIF_ADDR(params->chroma_address[2]));
0117     REG_UPDATE(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[2]));
0118     /* right eye offset for packing mode or Luma in planar mode */
0119     REG_UPDATE(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB_BUF_3_ADDR_C_OFFSET, 0);
0120
0121     /* buffer address for packing mode or Luma in planar mode */
0122     REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, MCIF_ADDR(params->luma_address[3]));
0123     REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[3]));
0124     /* right eye sub-buffer address offset for packing mode or Luma in planar mode */
0125     REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB_BUF_4_ADDR_Y_OFFSET, 0);
0126
0127     /* buffer address for Chroma in planar mode (unused in packing mode) */
0128     REG_UPDATE(MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, MCIF_ADDR(params->chroma_address[3]));
0129     REG_UPDATE(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[3]));
0130     /* right eye offset for packing mode or Luma in planar mode */
0131     REG_UPDATE(MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB_BUF_4_ADDR_C_OFFSET, 0);
0132
0133     /* setup luma & chroma size
0134      * should be enough to contain a whole frame Luma data,
0135      * the programmed value is frame buffer size [27:8], 256-byte aligned
0136      */
0137     REG_UPDATE(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, (params->luma_pitch>>8) * dest_height);
0138     REG_UPDATE(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, (params->chroma_pitch>>8) * dest_height);
0139
0140     /* enable address fence */
0141     REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, 1);
0142
0143     /* setup pitch, the programmed value is [15:8], 256B align */
0144     REG_UPDATE_2(MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, params->luma_pitch >> 8,
0145             MCIF_WB_BUF_CHROMA_PITCH, params->chroma_pitch >> 8);
0146
0147     /* Set pitch for MC cache warm up mode */
0148     /* Pitch is 256 bytes aligned. The default pitch is 4K */
0149     /* default is 0x10 */
0150     REG_UPDATE(MCIF_WB_WARM_UP_CNTL, MCIF_WB_PITCH_SIZE_WARMUP, params->warmup_pitch);
0151 }
0152
0153 static void mmhubbub2_config_mcif_arb(struct mcif_wb *mcif_wb,
0154         struct mcif_arb_params *params)
0155 {
0156     struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb);
0157
0158     /* Programmed by the video driver based on the CRTC timing (for DWB) */
0159     REG_UPDATE(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, params->time_per_pixel);
0160
0161     /* Programming dwb watermark */
0162     /* Watermark to generate urgent in MCIF_WB_CLI, value is determined by MCIF_WB_CLI_WATERMARK_MASK. */
0163     /* Program in ns. A formula will be provided in the pseudo code to calculate the value. */
0164     REG_UPDATE(MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, 0x0);
0165     /* urgent_watermarkA */
0166     REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK,  params->cli_watermark[0]);
0167     REG_UPDATE(MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, 0x1);
0168     /* urgent_watermarkB */
0169     REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK,  params->cli_watermark[1]);
0170     REG_UPDATE(MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, 0x2);
0171     /* urgent_watermarkC */
0172     REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK,  params->cli_watermark[2]);
0173     REG_UPDATE(MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, 0x3);
0174     /* urgent_watermarkD */
0175     REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK,  params->cli_watermark[3]);
0176
0177     /* Programming nb pstate watermark */
0178     /* nbp_state_change_watermarkA */
0179     REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x0);
0180     REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,
0181             NB_PSTATE_CHANGE_REFRESH_WATERMARK, params->pstate_watermark[0]);
0182     /* nbp_state_change_watermarkB */
0183     REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x1);
0184     REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,
0185             NB_PSTATE_CHANGE_REFRESH_WATERMARK, params->pstate_watermark[1]);
0186     /* nbp_state_change_watermarkC */
0187     REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x2);
0188     REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,
0189             NB_PSTATE_CHANGE_REFRESH_WATERMARK, params->pstate_watermark[2]);
0190     /* nbp_state_change_watermarkD */
0191     REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x3);
0192     REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,
0193             NB_PSTATE_CHANGE_REFRESH_WATERMARK, params->pstate_watermark[3]);
0194
0195     /* max_scaled_time */
0196     REG_UPDATE(MULTI_LEVEL_QOS_CTRL, MAX_SCALED_TIME_TO_URGENT, params->max_scaled_time);
0197
0198     /* slice_lines */
0199     REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, params->slice_lines-1);
0200
0201     /* Set arbitration unit for Luma/Chroma */
0202     /* arb_unit=2 should be chosen for more efficiency */
0203     /* Arbitration size, 0: 512 bytes 1: 1024 bytes 2: 2048 Bytes */
0204     REG_UPDATE(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE,  params->arbitration_slice);
0205 }
0206
0207 void mmhubbub2_config_mcif_irq(struct mcif_wb *mcif_wb,
0208         struct mcif_irq_params *params)
0209 {
0210     struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb);
0211
0212     /* Set interrupt mask */
0213     REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, params->sw_int_en);
0214     REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, params->sw_slice_int_en);
0215     REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN,  params->sw_overrun_int_en);
0216
0217     REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_EN,  params->vce_int_en);
0218     REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN,  params->vce_slice_int_en);
0219 }
0220
0221 void mmhubbub2_enable_mcif(struct mcif_wb *mcif_wb)
0222 {
0223     struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb);
0224
0225     /* Enable Mcifwb */
0226     REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, 1);
0227 }
0228
0229 void mmhubbub2_disable_mcif(struct mcif_wb *mcif_wb)
0230 {
0231     struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb);
0232
0233     /* disable buffer manager */
0234     REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, 0);
0235 }
0236
0237 /* set which group of pstate watermark to use and set wbif watermark change request */
0238 /*
0239 static void mmhubbub2_wbif_watermark_change_req(struct mcif_wb *mcif_wb, unsigned int wm_set)
0240 {
0241     struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb);
0242     uint32_t change_req;
0243
0244     REG_GET(SMU_WM_CONTROL, MCIF_WB0_WM_CHG_REQ, &change_req);
0245     change_req = (change_req == 0) ? 1 : 0;
0246     REG_UPDATE(SMU_WM_CONTROL, MCIF_WB0_WM_CHG_SEL, wm_set);
0247     REG_UPDATE(SMU_WM_CONTROL, MCIF_WB0_WM_CHG_REQ, change_req);
0248 }
0249 */
0250 /* Set watermark change interrupt disable bit */
0251 /*
0252 static void mmhubbub2_set_wbif_watermark_change_int_disable(struct mcif_wb *mcif_wb, unsigned int ack_int_dis)
0253 {
0254     struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb);
0255
0256     REG_UPDATE(SMU_WM_CONTROL, MCIF_WB0_WM_CHG_ACK_INT_DIS, ack_int_dis);
0257 }
0258 */
0259 /* Read watermark change interrupt status */
0260 /*
0261 unsigned int mmhubbub2_get_wbif_watermark_change_int_status(struct mcif_wb *mcif_wb)
0262 {
0263     struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb);
0264     uint32_t irq_status;
0265
0266     REG_GET(SMU_WM_CONTROL, MCIF_WB0_WM_CHG_ACK_INT_STATUS, &irq_status);
0267     return irq_status;
0268 }
0269 */
0270
0271 void mcifwb2_dump_frame(struct mcif_wb *mcif_wb,
0272         struct mcif_buf_params *mcif_params,
0273         enum dwb_scaler_mode out_format,
0274         unsigned int dest_width,
0275         unsigned int dest_height,
0276         struct mcif_wb_frame_dump_info *dump_info,
0277         unsigned char *luma_buffer,
0278         unsigned char *chroma_buffer,
0279         unsigned char *dest_luma_buffer,
0280         unsigned char *dest_chroma_buffer)
0281 {
0282     struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb);
0283
0284     REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, 0xf);
0285
0286     memcpy(dest_luma_buffer,   luma_buffer,   mcif_params->luma_pitch * dest_height);
0287     memcpy(dest_chroma_buffer, chroma_buffer, mcif_params->chroma_pitch * dest_height / 2);
0288
0289     REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, 0x0);
0290
0291     dump_info->format   = out_format;
0292     dump_info->width    = dest_width;
0293     dump_info->height   = dest_height;
0294     dump_info->luma_pitch   = mcif_params->luma_pitch;
0295     dump_info->chroma_pitch = mcif_params->chroma_pitch;
0296     dump_info->size     = dest_height * (mcif_params->luma_pitch + mcif_params->chroma_pitch);
0297 }
0298
0299 const struct mcif_wb_funcs dcn20_mmhubbub_funcs = {
0300     .enable_mcif        = mmhubbub2_enable_mcif,
0301     .disable_mcif       = mmhubbub2_disable_mcif,
0302     .config_mcif_buf    = mmhubbub2_config_mcif_buf,
0303     .config_mcif_arb    = mmhubbub2_config_mcif_arb,
0304     .config_mcif_irq    = mmhubbub2_config_mcif_irq,
0305     .dump_frame     = mcifwb2_dump_frame,
0306 };
0307
0308 void dcn20_mmhubbub_construct(struct dcn20_mmhubbub *mcif_wb20,
0309         struct dc_context *ctx,
0310         const struct dcn20_mmhubbub_registers *mcif_wb_regs,
0311         const struct dcn20_mmhubbub_shift *mcif_wb_shift,
0312         const struct dcn20_mmhubbub_mask *mcif_wb_mask,
0313         int inst)
0314 {
0315     mcif_wb20->base.ctx = ctx;
0316
0317     mcif_wb20->base.inst = inst;
0318     mcif_wb20->base.funcs = &dcn20_mmhubbub_funcs;
0319
0320     mcif_wb20->mcif_wb_regs = mcif_wb_regs;
0321     mcif_wb20->mcif_wb_shift = mcif_wb_shift;
0322     mcif_wb20->mcif_wb_mask = mcif_wb_mask;
0323 }