dc/dcn20/dcn20_link_encoder.h

0001 /*
0002  * Copyright 2012-15 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  *  and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef __DC_LINK_ENCODER__DCN20_H__
0027 #define __DC_LINK_ENCODER__DCN20_H__
0028
0029 #include "dcn10/dcn10_link_encoder.h"
0030
0031 #define DCN2_AUX_REG_LIST(id)\
0032     AUX_REG_LIST(id), \
0033     SRI(AUX_DPHY_TX_CONTROL, DP_AUX, id)
0034
0035 #define UNIPHY_MASK_SH_LIST(mask_sh)\
0036     LE_SF(SYMCLKA_CLOCK_ENABLE, SYMCLKA_CLOCK_ENABLE, mask_sh),\
0037     LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_LINK_ENABLE, mask_sh),\
0038     LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL0_XBAR_SOURCE, mask_sh),\
0039     LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL1_XBAR_SOURCE, mask_sh),\
0040     LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL2_XBAR_SOURCE, mask_sh),\
0041     LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL3_XBAR_SOURCE, mask_sh)
0042
0043 #define DPCS_MASK_SH_LIST(mask_sh)\
0044     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_CLK_RDY, mask_sh),\
0045     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_DATA_EN, mask_sh),\
0046     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_CLK_RDY, mask_sh),\
0047     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_DATA_EN, mask_sh),\
0048     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_CLK_RDY, mask_sh),\
0049     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_DATA_EN, mask_sh),\
0050     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_CLK_RDY, mask_sh),\
0051     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_DATA_EN, mask_sh),\
0052     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX0_TERM_CTRL, mask_sh),\
0053     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX1_TERM_CTRL, mask_sh),\
0054     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX2_TERM_CTRL, mask_sh),\
0055     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX3_TERM_CTRL, mask_sh),\
0056     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_DP_MPLLB_MULTIPLIER, mask_sh),\
0057     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX0_WIDTH, mask_sh),\
0058     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX0_RATE, mask_sh),\
0059     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX1_WIDTH, mask_sh),\
0060     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX1_RATE, mask_sh),\
0061     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX2_PSTATE, mask_sh),\
0062     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX3_PSTATE, mask_sh),\
0063     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX2_MPLL_EN, mask_sh),\
0064     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX3_MPLL_EN, mask_sh),\
0065     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL7, RDPCS_PHY_DP_MPLLB_FRACN_QUOT, mask_sh),\
0066     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL7, RDPCS_PHY_DP_MPLLB_FRACN_DEN, mask_sh),\
0067     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL8, RDPCS_PHY_DP_MPLLB_SSC_PEAK, mask_sh),\
0068     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL9, RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD, mask_sh),\
0069     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL9, RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE, mask_sh),\
0070     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL10, RDPCS_PHY_DP_MPLLB_FRACN_REM, mask_sh),\
0071     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_DP_REF_CLK_MPLLB_DIV, mask_sh),\
0072     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_HDMI_MPLLB_HDMI_DIV, mask_sh),\
0073     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_SSC_EN, mask_sh),\
0074     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN, mask_sh),\
0075     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_TX_CLK_DIV, mask_sh),\
0076     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN, mask_sh),\
0077     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_STATE, mask_sh),\
0078     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL13, RDPCS_PHY_DP_MPLLB_DIV_CLK_EN, mask_sh),\
0079     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL13, RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER, mask_sh),\
0080     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL14, RDPCS_PHY_DP_MPLLB_FRACN_EN, mask_sh),\
0081     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL14, RDPCS_PHY_DP_MPLLB_PMIX_EN, mask_sh),\
0082     LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE0_EN, mask_sh),\
0083     LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE1_EN, mask_sh),\
0084     LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE2_EN, mask_sh),\
0085     LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE3_EN, mask_sh),\
0086     LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_EN, mask_sh),\
0087     LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_RD_START_DELAY, mask_sh),\
0088     LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_EXT_REFCLK_EN, mask_sh),\
0089     LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_BYPASS, mask_sh),\
0090     LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_EN, mask_sh),\
0091     LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_CLOCK_ON, mask_sh),\
0092     LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_CLOCK_ON, mask_sh),\
0093     LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_GATE_DIS, mask_sh),\
0094     LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_EN, mask_sh),\
0095     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_DISABLE, mask_sh),\
0096     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_DISABLE, mask_sh),\
0097     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_DISABLE, mask_sh),\
0098     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_DISABLE, mask_sh),\
0099     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_REQ, mask_sh),\
0100     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_REQ, mask_sh),\
0101     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_REQ, mask_sh),\
0102     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_REQ, mask_sh),\
0103     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_ACK, mask_sh),\
0104     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_ACK, mask_sh),\
0105     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_ACK, mask_sh),\
0106     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_ACK, mask_sh),\
0107     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_RESET, mask_sh),\
0108     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_RESET, mask_sh),\
0109     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_RESET, mask_sh),\
0110     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_RESET, mask_sh),\
0111     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_RESET, mask_sh),\
0112     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_CR_MUX_SEL, mask_sh),\
0113     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_REF_RANGE, mask_sh),\
0114     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_BYPASS, mask_sh),\
0115     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_EXT_LD_DONE, mask_sh),\
0116     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_HDMIMODE_ENABLE, mask_sh),\
0117     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_INIT_DONE, mask_sh),\
0118     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL2, RDPCS_PHY_DP4_POR, mask_sh),\
0119     LE_SF(RDPCSTX0_RDPCSTX_PLL_UPDATE_DATA, RDPCS_PLL_UPDATE_DATA, mask_sh),\
0120     LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_REG_FIFO_ERROR_MASK, mask_sh),\
0121     LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_TX_FIFO_ERROR_MASK, mask_sh),\
0122     LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_DPALT_DISABLE_TOGGLE_MASK, mask_sh),\
0123     LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_DPALT_4LANE_TOGGLE_MASK, mask_sh),\
0124     LE_SF(RDPCSTX0_RDPCS_TX_CR_ADDR, RDPCS_TX_CR_ADDR, mask_sh),\
0125     LE_SF(RDPCSTX0_RDPCS_TX_CR_DATA, RDPCS_TX_CR_DATA, mask_sh),\
0126     LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_MPLLB_V2I, mask_sh),\
0127     LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_MAIN, mask_sh),\
0128     LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_PRE, mask_sh),\
0129     LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_POST, mask_sh),\
0130     LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_MPLLB_FREQ_VCO, mask_sh),\
0131     LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_MPLLB_CP_INT, mask_sh),\
0132     LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_MPLLB_CP_PROP, mask_sh),\
0133     LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_MAIN, mask_sh),\
0134     LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_PRE, mask_sh),\
0135     LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_POST, mask_sh),\
0136     LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_MAIN, mask_sh),\
0137     LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_PRE, mask_sh),\
0138     LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_POST, mask_sh),\
0139     LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_MAIN, mask_sh),\
0140     LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DCO_FINETUNE, mask_sh),\
0141     LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DCO_RANGE, mask_sh),\
0142     LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_PRE, mask_sh),\
0143     LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_POST, mask_sh),\
0144     LE_SF(DPCSTX0_DPCSTX_TX_CLOCK_CNTL, DPCS_SYMCLK_CLOCK_ON, mask_sh),\
0145     LE_SF(DPCSTX0_DPCSTX_TX_CLOCK_CNTL, DPCS_SYMCLK_GATE_DIS, mask_sh),\
0146     LE_SF(DPCSTX0_DPCSTX_TX_CLOCK_CNTL, DPCS_SYMCLK_EN, mask_sh),\
0147     LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_DATA_SWAP, mask_sh),\
0148     LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_DATA_ORDER_INVERT, mask_sh),\
0149     LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_FIFO_EN, mask_sh),\
0150     LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_FIFO_RD_START_DELAY, mask_sh)
0151
0152 #define DPCS_DCN2_MASK_SH_LIST(mask_sh)\
0153     DPCS_MASK_SH_LIST(mask_sh),\
0154     LE_SF(RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL, RDPCS_PHY_RX_REF_LD_VAL, mask_sh),\
0155     LE_SF(RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL, RDPCS_PHY_RX_VCO_LD_VAL, mask_sh),\
0156     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE_ACK, mask_sh),\
0157     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX0_PSTATE, mask_sh),\
0158     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX1_PSTATE, mask_sh),\
0159     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX0_MPLL_EN, mask_sh),\
0160     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX1_MPLL_EN, mask_sh),\
0161     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_REF_CLK_EN, mask_sh),\
0162     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX2_WIDTH, mask_sh),\
0163     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX2_RATE, mask_sh),\
0164     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX3_WIDTH, mask_sh),\
0165     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX3_RATE, mask_sh),\
0166     LE_SF(DCIO_SOFT_RESET, UNIPHYA_SOFT_RESET, mask_sh),\
0167     LE_SF(DCIO_SOFT_RESET, UNIPHYB_SOFT_RESET, mask_sh),\
0168     LE_SF(DCIO_SOFT_RESET, UNIPHYC_SOFT_RESET, mask_sh),\
0169     LE_SF(DCIO_SOFT_RESET, UNIPHYD_SOFT_RESET, mask_sh),\
0170     LE_SF(DCIO_SOFT_RESET, UNIPHYE_SOFT_RESET, mask_sh),\
0171     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, mask_sh),\
0172     LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, mask_sh)
0173
0174 #define LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh)\
0175     LINK_ENCODER_MASK_SH_LIST_DCN10(mask_sh),\
0176     LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_EN, mask_sh),\
0177     LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, mask_sh),\
0178     LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, mask_sh),\
0179     LE_SF(DIG0_DIG_LANE_ENABLE, DIG_LANE0EN, mask_sh),\
0180     LE_SF(DIG0_DIG_LANE_ENABLE, DIG_LANE1EN, mask_sh),\
0181     LE_SF(DIG0_DIG_LANE_ENABLE, DIG_LANE2EN, mask_sh),\
0182     LE_SF(DIG0_DIG_LANE_ENABLE, DIG_LANE3EN, mask_sh),\
0183     LE_SF(DIG0_DIG_LANE_ENABLE, DIG_CLK_EN, mask_sh),\
0184     LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
0185     UNIPHY_MASK_SH_LIST(mask_sh),\
0186     LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_START_WINDOW, mask_sh),\
0187     LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_HALF_SYM_DETECT_LEN, mask_sh),\
0188     LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_TRANSITION_FILTER_EN, mask_sh),\
0189     LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT, mask_sh),\
0190     LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_START, mask_sh),\
0191     LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_STOP, mask_sh),\
0192     LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_PHASE_DETECT_LEN, mask_sh),\
0193     LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_DETECTION_THRESHOLD, mask_sh), \
0194     LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_LEN, mask_sh),\
0195     LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_SYMBOLS, mask_sh),\
0196     LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_MODE_DET_CHECK_DELAY, mask_sh),\
0197     LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_PRECHARGE_SKIP, mask_sh),\
0198     LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, mask_sh),\
0199     LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN_MUL, mask_sh)
0200
0201 #define UNIPHY_DCN2_REG_LIST(id) \
0202     SRI(CLOCK_ENABLE, SYMCLK, id), \
0203     SRI(CHANNEL_XBAR_CNTL, UNIPHY, id)
0204
0205 #define DPCS_DCN2_CMN_REG_LIST(id) \
0206     SRI(DIG_LANE_ENABLE, DIG, id), \
0207     SRI(TMDS_CTL_BITS, DIG, id), \
0208     SRI(RDPCSTX_PHY_CNTL3, RDPCSTX, id), \
0209     SRI(RDPCSTX_PHY_CNTL4, RDPCSTX, id), \
0210     SRI(RDPCSTX_PHY_CNTL5, RDPCSTX, id), \
0211     SRI(RDPCSTX_PHY_CNTL6, RDPCSTX, id), \
0212     SRI(RDPCSTX_PHY_CNTL7, RDPCSTX, id), \
0213     SRI(RDPCSTX_PHY_CNTL8, RDPCSTX, id), \
0214     SRI(RDPCSTX_PHY_CNTL9, RDPCSTX, id), \
0215     SRI(RDPCSTX_PHY_CNTL10, RDPCSTX, id), \
0216     SRI(RDPCSTX_PHY_CNTL11, RDPCSTX, id), \
0217     SRI(RDPCSTX_PHY_CNTL12, RDPCSTX, id), \
0218     SRI(RDPCSTX_PHY_CNTL13, RDPCSTX, id), \
0219     SRI(RDPCSTX_PHY_CNTL14, RDPCSTX, id), \
0220     SRI(RDPCSTX_CNTL, RDPCSTX, id), \
0221     SRI(RDPCSTX_CLOCK_CNTL, RDPCSTX, id), \
0222     SRI(RDPCSTX_INTERRUPT_CONTROL, RDPCSTX, id), \
0223     SRI(RDPCSTX_PHY_CNTL0, RDPCSTX, id), \
0224     SRI(RDPCSTX_PHY_CNTL2, RDPCSTX, id), \
0225     SRI(RDPCSTX_PLL_UPDATE_DATA, RDPCSTX, id), \
0226     SRI(RDPCS_TX_CR_ADDR, RDPCSTX, id), \
0227     SRI(RDPCS_TX_CR_DATA, RDPCSTX, id), \
0228     SRI(RDPCSTX_PHY_FUSE0, RDPCSTX, id), \
0229     SRI(RDPCSTX_PHY_FUSE1, RDPCSTX, id), \
0230     SRI(RDPCSTX_PHY_FUSE2, RDPCSTX, id), \
0231     SRI(RDPCSTX_PHY_FUSE3, RDPCSTX, id), \
0232     SRI(DPCSTX_TX_CLOCK_CNTL, DPCSTX, id), \
0233     SRI(DPCSTX_TX_CNTL, DPCSTX, id), \
0234     SR(RDPCSTX0_RDPCSTX_SCRATCH)
0235
0236
0237 #define DPCS_DCN2_REG_LIST(id) \
0238     DPCS_DCN2_CMN_REG_LIST(id), \
0239     SRI(RDPCSTX_PHY_RX_LD_VAL, RDPCSTX, id),\
0240     SRI(RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG, RDPCSTX, id)
0241
0242 #define LE_DCN2_REG_LIST(id) \
0243         LE_DCN10_REG_LIST(id), \
0244         SR(DCIO_SOFT_RESET)
0245
0246 struct mpll_cfg {
0247     uint32_t mpllb_ana_v2i;
0248     uint32_t mpllb_ana_freq_vco;
0249     uint32_t mpllb_ana_cp_int;
0250     uint32_t mpllb_ana_cp_prop;
0251     uint32_t mpllb_multiplier;
0252     uint32_t ref_clk_mpllb_div;
0253     bool mpllb_word_div2_en;
0254     bool mpllb_ssc_en;
0255     bool mpllb_div5_clk_en;
0256     bool mpllb_div_clk_en;
0257     bool mpllb_fracn_en;
0258     bool mpllb_pmix_en;
0259     uint32_t mpllb_div_multiplier;
0260     uint32_t mpllb_tx_clk_div;
0261     uint32_t mpllb_fracn_quot;
0262     uint32_t mpllb_fracn_den;
0263     uint32_t mpllb_ssc_peak;
0264     uint32_t mpllb_ssc_stepsize;
0265     uint32_t mpllb_ssc_up_spread;
0266     uint32_t mpllb_fracn_rem;
0267     uint32_t mpllb_hdmi_div;
0268     // TODO: May not mpll params, need to figure out.
0269     uint32_t tx_vboost_lvl;
0270     uint32_t hdmi_pixel_clk_div;
0271     uint32_t ref_range;
0272     uint32_t ref_clk;
0273     bool hdmimode_enable;
0274     bool sup_pre_hp;
0275     bool dp_tx0_vergdrv_byp;
0276     bool dp_tx1_vergdrv_byp;
0277     bool dp_tx2_vergdrv_byp;
0278     bool dp_tx3_vergdrv_byp;
0279     uint32_t tx_peaking_lvl;
0280     uint32_t ctr_reqs_pll;
0281
0282
0283 };
0284
0285 struct dpcssys_phy_seq_cfg {
0286     bool program_fuse;
0287     bool bypass_sram;
0288     bool lane_en[4];
0289     bool use_calibration_setting;
0290     struct mpll_cfg mpll_cfg;
0291     bool load_sram_fw;
0292 #if 0
0293
0294     bool hdmimode_enable;
0295     bool silver2;
0296     bool ext_refclk_en;
0297     uint32_t dp_tx0_term_ctrl;
0298     uint32_t dp_tx1_term_ctrl;
0299     uint32_t dp_tx2_term_ctrl;
0300     uint32_t dp_tx3_term_ctrl;
0301     uint32_t fw_data[0x1000];
0302     uint32_t dp_tx0_width;
0303     uint32_t dp_tx1_width;
0304     uint32_t dp_tx2_width;
0305     uint32_t dp_tx3_width;
0306     uint32_t dp_tx0_rate;
0307     uint32_t dp_tx1_rate;
0308     uint32_t dp_tx2_rate;
0309     uint32_t dp_tx3_rate;
0310     uint32_t dp_tx0_eq_main;
0311     uint32_t dp_tx0_eq_pre;
0312     uint32_t dp_tx0_eq_post;
0313     uint32_t dp_tx1_eq_main;
0314     uint32_t dp_tx1_eq_pre;
0315     uint32_t dp_tx1_eq_post;
0316     uint32_t dp_tx2_eq_main;
0317     uint32_t dp_tx2_eq_pre;
0318     uint32_t dp_tx2_eq_post;
0319     uint32_t dp_tx3_eq_main;
0320     uint32_t dp_tx3_eq_pre;
0321     uint32_t dp_tx3_eq_post;
0322     bool data_swap_en;
0323     bool data_order_invert_en;
0324     uint32_t ldpcs_fifo_start_delay;
0325     uint32_t rdpcs_fifo_start_delay;
0326     bool rdpcs_reg_fifo_error_mask;
0327     bool rdpcs_tx_fifo_error_mask;
0328     bool rdpcs_dpalt_disable_mask;
0329     bool rdpcs_dpalt_4lane_mask;
0330 #endif
0331 };
0332
0333 struct dcn20_link_encoder {
0334     struct dcn10_link_encoder enc10;
0335     struct dpcssys_phy_seq_cfg phy_seq_cfg;
0336 };
0337
0338 void enc2_fec_set_enable(struct link_encoder *enc, bool enable);
0339 void enc2_fec_set_ready(struct link_encoder *enc, bool ready);
0340 bool enc2_fec_is_active(struct link_encoder *enc);
0341 void enc2_hw_init(struct link_encoder *enc);
0342
0343 void link_enc2_read_state(struct link_encoder *enc, struct link_enc_state *s);
0344
0345 void dcn20_link_encoder_enable_dp_output(
0346     struct link_encoder *enc,
0347     const struct dc_link_settings *link_settings,
0348     enum clock_source_id clock_source);
0349
0350 bool dcn20_link_encoder_is_in_alt_mode(struct link_encoder *enc);
0351 void dcn20_link_encoder_get_max_link_cap(struct link_encoder *enc,
0352     struct dc_link_settings *link_settings);
0353
0354 void dcn20_link_encoder_construct(
0355     struct dcn20_link_encoder *enc20,
0356     const struct encoder_init_data *init_data,
0357     const struct encoder_feature_support *enc_features,
0358     const struct dcn10_link_enc_registers *link_regs,
0359     const struct dcn10_link_enc_aux_registers *aux_regs,
0360     const struct dcn10_link_enc_hpd_registers *hpd_regs,
0361     const struct dcn10_link_enc_shift *link_shift,
0362     const struct dcn10_link_enc_mask *link_mask);
0363
0364 #endif /* __DC_LINK_ENCODER__DCN20_H__ */