dc/dcn20/dcn20_link_encoder.c

0001 /*
0002  * Copyright 2012-15 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include "reg_helper.h"
0027
0028 #include "core_types.h"
0029 #include "link_encoder.h"
0030 #include "dcn20_link_encoder.h"
0031 #include "stream_encoder.h"
0032 #include "i2caux_interface.h"
0033 #include "dc_bios_types.h"
0034
0035 #include "gpio_service_interface.h"
0036
0037 #define CTX \
0038     enc10->base.ctx
0039 #define DC_LOGGER \
0040     enc10->base.ctx->logger
0041
0042 #define REG(reg)\
0043     (enc10->link_regs->reg)
0044
0045 #undef FN
0046 #define FN(reg_name, field_name) \
0047     enc10->link_shift->field_name, enc10->link_mask->field_name
0048
0049 #define IND_REG(index) \
0050     (enc10->link_regs->index)
0051
0052 #ifndef MAX
0053 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
0054 #endif
0055 #ifndef MIN
0056 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
0057 #endif
0058
0059 static struct mpll_cfg dcn2_mpll_cfg[] = {
0060     // RBR
0061     {
0062         .hdmimode_enable = 1,
0063         .ref_range = 3,
0064         .ref_clk_mpllb_div = 2,
0065         .mpllb_ssc_en = 1,
0066         .mpllb_div5_clk_en = 1,
0067         .mpllb_multiplier = 226,
0068         .mpllb_fracn_en = 1,
0069         .mpllb_fracn_quot = 39321,
0070         .mpllb_fracn_rem = 3,
0071         .mpllb_fracn_den = 5,
0072         .mpllb_ssc_up_spread = 0,
0073         .mpllb_ssc_peak = 38221,
0074         .mpllb_ssc_stepsize = 49314,
0075         .mpllb_div_clk_en = 0,
0076         .mpllb_div_multiplier = 0,
0077         .mpllb_hdmi_div = 0,
0078         .mpllb_tx_clk_div = 2,
0079         .tx_vboost_lvl = 4,
0080         .mpllb_pmix_en = 1,
0081         .mpllb_word_div2_en = 0,
0082         .mpllb_ana_v2i = 2,
0083         .mpllb_ana_freq_vco = 2,
0084         .mpllb_ana_cp_int = 7,
0085         .mpllb_ana_cp_prop = 18,
0086         .hdmi_pixel_clk_div = 0,
0087     },
0088     // HBR
0089     {
0090         .hdmimode_enable = 1,
0091         .ref_range = 3,
0092         .ref_clk_mpllb_div = 2,
0093         .mpllb_ssc_en = 1,
0094         .mpllb_div5_clk_en = 1,
0095         .mpllb_multiplier = 184,
0096         .mpllb_fracn_en = 0,
0097         .mpllb_fracn_quot = 0,
0098         .mpllb_fracn_rem = 0,
0099         .mpllb_fracn_den = 1,
0100         .mpllb_ssc_up_spread = 0,
0101         .mpllb_ssc_peak = 31850,
0102         .mpllb_ssc_stepsize = 41095,
0103         .mpllb_div_clk_en = 0,
0104         .mpllb_div_multiplier = 0,
0105         .mpllb_hdmi_div = 0,
0106         .mpllb_tx_clk_div = 1,
0107         .tx_vboost_lvl = 4,
0108         .mpllb_pmix_en = 1,
0109         .mpllb_word_div2_en = 0,
0110         .mpllb_ana_v2i = 2,
0111         .mpllb_ana_freq_vco = 3,
0112         .mpllb_ana_cp_int = 7,
0113         .mpllb_ana_cp_prop = 18,
0114         .hdmi_pixel_clk_div = 0,
0115     },
0116     //HBR2
0117     {
0118         .hdmimode_enable = 1,
0119         .ref_range = 3,
0120         .ref_clk_mpllb_div = 2,
0121         .mpllb_ssc_en = 1,
0122         .mpllb_div5_clk_en = 1,
0123         .mpllb_multiplier = 184,
0124         .mpllb_fracn_en = 0,
0125         .mpllb_fracn_quot = 0,
0126         .mpllb_fracn_rem = 0,
0127         .mpllb_fracn_den = 1,
0128         .mpllb_ssc_up_spread = 0,
0129         .mpllb_ssc_peak = 31850,
0130         .mpllb_ssc_stepsize = 41095,
0131         .mpllb_div_clk_en = 0,
0132         .mpllb_div_multiplier = 0,
0133         .mpllb_hdmi_div = 0,
0134         .mpllb_tx_clk_div = 0,
0135         .tx_vboost_lvl = 4,
0136         .mpllb_pmix_en = 1,
0137         .mpllb_word_div2_en = 0,
0138         .mpllb_ana_v2i = 2,
0139         .mpllb_ana_freq_vco = 3,
0140         .mpllb_ana_cp_int = 7,
0141         .mpllb_ana_cp_prop = 18,
0142         .hdmi_pixel_clk_div = 0,
0143     },
0144     //HBR3
0145     {
0146         .hdmimode_enable = 1,
0147         .ref_range = 3,
0148         .ref_clk_mpllb_div = 2,
0149         .mpllb_ssc_en = 1,
0150         .mpllb_div5_clk_en = 1,
0151         .mpllb_multiplier = 292,
0152         .mpllb_fracn_en = 0,
0153         .mpllb_fracn_quot = 0,
0154         .mpllb_fracn_rem = 0,
0155         .mpllb_fracn_den = 1,
0156         .mpllb_ssc_up_spread = 0,
0157         .mpllb_ssc_peak = 47776,
0158         .mpllb_ssc_stepsize = 61642,
0159         .mpllb_div_clk_en = 0,
0160         .mpllb_div_multiplier = 0,
0161         .mpllb_hdmi_div = 0,
0162         .mpllb_tx_clk_div = 0,
0163         .tx_vboost_lvl = 4,
0164         .mpllb_pmix_en = 1,
0165         .mpllb_word_div2_en = 0,
0166         .mpllb_ana_v2i = 2,
0167         .mpllb_ana_freq_vco = 0,
0168         .mpllb_ana_cp_int = 7,
0169         .mpllb_ana_cp_prop = 18,
0170         .hdmi_pixel_clk_div = 0,
0171     },
0172 };
0173
0174 void enc2_fec_set_enable(struct link_encoder *enc, bool enable)
0175 {
0176     struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
0177     DC_LOG_DSC("%s FEC at link encoder inst %d",
0178             enable ? "Enabling" : "Disabling", enc->id.enum_id);
0179     REG_UPDATE(DP_DPHY_CNTL, DPHY_FEC_EN, enable);
0180 }
0181
0182 void enc2_fec_set_ready(struct link_encoder *enc, bool ready)
0183 {
0184     struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
0185
0186     REG_UPDATE(DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, ready);
0187 }
0188
0189 bool enc2_fec_is_active(struct link_encoder *enc)
0190 {
0191     uint32_t active = 0;
0192     struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
0193
0194     REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &active);
0195
0196     return (active != 0);
0197 }
0198
0199 /* this function reads dsc related register fields to be logged later in dcn10_log_hw_state
0200  * into a dcn_dsc_state struct.
0201  */
0202 void link_enc2_read_state(struct link_encoder *enc, struct link_enc_state *s)
0203 {
0204     struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
0205
0206     REG_GET(DP_DPHY_CNTL, DPHY_FEC_EN, &s->dphy_fec_en);
0207     REG_GET(DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, &s->dphy_fec_ready_shadow);
0208     REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &s->dphy_fec_active_status);
0209     REG_GET(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, &s->dp_link_training_complete);
0210 }
0211
0212 static bool update_cfg_data(
0213         struct dcn10_link_encoder *enc10,
0214         const struct dc_link_settings *link_settings,
0215         struct dpcssys_phy_seq_cfg *cfg)
0216 {
0217     int i;
0218
0219     cfg->load_sram_fw = false;
0220
0221     for (i = 0; i < link_settings->lane_count; i++)
0222         cfg->lane_en[i] = true;
0223
0224     switch (link_settings->link_rate) {
0225     case LINK_RATE_LOW:
0226         cfg->mpll_cfg = dcn2_mpll_cfg[0];
0227         break;
0228     case LINK_RATE_HIGH:
0229         cfg->mpll_cfg = dcn2_mpll_cfg[1];
0230         break;
0231     case LINK_RATE_HIGH2:
0232         cfg->mpll_cfg = dcn2_mpll_cfg[2];
0233         break;
0234     case LINK_RATE_HIGH3:
0235         cfg->mpll_cfg = dcn2_mpll_cfg[3];
0236         break;
0237     default:
0238         DC_LOG_ERROR("%s: No supported link rate found %X!\n",
0239                 __func__, link_settings->link_rate);
0240         return false;
0241     }
0242
0243     return true;
0244 }
0245
0246 void dcn20_link_encoder_enable_dp_output(
0247     struct link_encoder *enc,
0248     const struct dc_link_settings *link_settings,
0249     enum clock_source_id clock_source)
0250 {
0251     struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
0252     struct dcn20_link_encoder *enc20 = (struct dcn20_link_encoder *) enc10;
0253     struct dpcssys_phy_seq_cfg *cfg = &enc20->phy_seq_cfg;
0254
0255     if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
0256         dcn10_link_encoder_enable_dp_output(enc, link_settings, clock_source);
0257         return;
0258     }
0259
0260     if (!update_cfg_data(enc10, link_settings, cfg))
0261         return;
0262
0263     enc1_configure_encoder(enc10, link_settings);
0264
0265     dcn10_link_encoder_setup(enc, SIGNAL_TYPE_DISPLAY_PORT);
0266
0267 }
0268
0269 void dcn20_link_encoder_get_max_link_cap(struct link_encoder *enc,
0270     struct dc_link_settings *link_settings)
0271 {
0272     struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
0273     uint32_t is_in_usb_c_dp4_mode = 0;
0274
0275     dcn10_link_encoder_get_max_link_cap(enc, link_settings);
0276
0277     /* in usb c dp2 mode, max lane count is 2 */
0278     if (enc->funcs->is_in_alt_mode && enc->funcs->is_in_alt_mode(enc)) {
0279         REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode);
0280         if (!is_in_usb_c_dp4_mode)
0281             link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count);
0282     }
0283
0284 }
0285
0286 bool dcn20_link_encoder_is_in_alt_mode(struct link_encoder *enc)
0287 {
0288     struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
0289     uint32_t dp_alt_mode_disable = 0;
0290     bool is_usb_c_alt_mode = false;
0291
0292     if (enc->features.flags.bits.DP_IS_USB_C) {
0293         /* if value == 1 alt mode is disabled, otherwise it is enabled */
0294         REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable);
0295         is_usb_c_alt_mode = (dp_alt_mode_disable == 0);
0296     }
0297
0298     return is_usb_c_alt_mode;
0299 }
0300
0301 #define AUX_REG(reg)\
0302     (enc10->aux_regs->reg)
0303
0304 #define AUX_REG_READ(reg_name) \
0305         dm_read_reg(CTX, AUX_REG(reg_name))
0306
0307 #define AUX_REG_WRITE(reg_name, val) \
0308             dm_write_reg(CTX, AUX_REG(reg_name), val)
0309 void enc2_hw_init(struct link_encoder *enc)
0310 {
0311     struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
0312 /*
0313     00 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 : 1/2
0314     01 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 : 3/4
0315     02 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 : 7/8
0316     03 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 : 15/16
0317     04 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 : 31/32
0318     05 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 : 63/64
0319     06 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 : 127/128
0320     07 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 : 255/256
0321 */
0322
0323 /*
0324     AUX_REG_UPDATE_5(AUX_DPHY_RX_CONTROL0,
0325     AUX_RX_START_WINDOW = 1 [6:4]
0326     AUX_RX_RECEIVE_WINDOW = 1 default is 2 [10:8]
0327     AUX_RX_HALF_SYM_DETECT_LEN  = 1 [13:12] default is 1
0328     AUX_RX_TRANSITION_FILTER_EN = 1 [16] default is 1
0329     AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT [17] is 0  default is 0
0330     AUX_RX_ALLOW_BELOW_THRESHOLD_START [18] is 1  default is 1
0331     AUX_RX_ALLOW_BELOW_THRESHOLD_STOP [19] is 1  default is 1
0332     AUX_RX_PHASE_DETECT_LEN,  [21,20] = 0x3 default is 3
0333     AUX_RX_DETECTION_THRESHOLD [30:28] = 1
0334 */
0335     if (enc->ctx->dc_bios->golden_table.dc_golden_table_ver > 0) {
0336         AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, enc->ctx->dc_bios->golden_table.aux_dphy_rx_control0_val);
0337
0338         AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, enc->ctx->dc_bios->golden_table.aux_dphy_tx_control_val);
0339
0340         AUX_REG_WRITE(AUX_DPHY_RX_CONTROL1, enc->ctx->dc_bios->golden_table.aux_dphy_rx_control1_val);
0341     } else {
0342         AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110);
0343
0344         AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a);
0345     }
0346
0347     //AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32;
0348     // Set AUX_TX_REF_DIV Divider to generate 2 MHz reference from refclk
0349     // 27MHz -> 0xd
0350     // 100MHz -> 0x32
0351     // 48MHz -> 0x18
0352
0353     // Set TMDS_CTL0 to 1.  This is a legacy setting.
0354     REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1);
0355
0356     dcn10_aux_initialize(enc10);
0357 }
0358
0359 static const struct link_encoder_funcs dcn20_link_enc_funcs = {
0360     .read_state = link_enc2_read_state,
0361     .validate_output_with_stream =
0362         dcn10_link_encoder_validate_output_with_stream,
0363     .hw_init = enc2_hw_init,
0364     .setup = dcn10_link_encoder_setup,
0365     .enable_tmds_output = dcn10_link_encoder_enable_tmds_output_with_clk_pattern_wa,
0366     .enable_dp_output = dcn20_link_encoder_enable_dp_output,
0367     .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
0368     .disable_output = dcn10_link_encoder_disable_output,
0369     .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
0370     .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
0371     .update_mst_stream_allocation_table =
0372         dcn10_link_encoder_update_mst_stream_allocation_table,
0373     .psr_program_dp_dphy_fast_training =
0374             dcn10_psr_program_dp_dphy_fast_training,
0375     .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
0376     .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
0377     .enable_hpd = dcn10_link_encoder_enable_hpd,
0378     .disable_hpd = dcn10_link_encoder_disable_hpd,
0379     .is_dig_enabled = dcn10_is_dig_enabled,
0380     .destroy = dcn10_link_encoder_destroy,
0381     .fec_set_enable = enc2_fec_set_enable,
0382     .fec_set_ready = enc2_fec_set_ready,
0383     .fec_is_active = enc2_fec_is_active,
0384     .get_dig_mode = dcn10_get_dig_mode,
0385     .get_dig_frontend = dcn10_get_dig_frontend,
0386     .is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode,
0387     .get_max_link_cap = dcn20_link_encoder_get_max_link_cap,
0388 };
0389
0390 void dcn20_link_encoder_construct(
0391     struct dcn20_link_encoder *enc20,
0392     const struct encoder_init_data *init_data,
0393     const struct encoder_feature_support *enc_features,
0394     const struct dcn10_link_enc_registers *link_regs,
0395     const struct dcn10_link_enc_aux_registers *aux_regs,
0396     const struct dcn10_link_enc_hpd_registers *hpd_regs,
0397     const struct dcn10_link_enc_shift *link_shift,
0398     const struct dcn10_link_enc_mask *link_mask)
0399 {
0400     struct bp_encoder_cap_info bp_cap_info = {0};
0401     const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
0402     enum bp_result result = BP_RESULT_OK;
0403     struct dcn10_link_encoder *enc10 = &enc20->enc10;
0404
0405     enc10->base.funcs = &dcn20_link_enc_funcs;
0406     enc10->base.ctx = init_data->ctx;
0407     enc10->base.id = init_data->encoder;
0408
0409     enc10->base.hpd_source = init_data->hpd_source;
0410     enc10->base.connector = init_data->connector;
0411
0412     enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
0413
0414     enc10->base.features = *enc_features;
0415
0416     enc10->base.transmitter = init_data->transmitter;
0417
0418     /* set the flag to indicate whether driver poll the I2C data pin
0419      * while doing the DP sink detect
0420      */
0421
0422 /*  if (dal_adapter_service_is_feature_supported(as,
0423         FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
0424         enc10->base.features.flags.bits.
0425             DP_SINK_DETECT_POLL_DATA_PIN = true;*/
0426
0427     enc10->base.output_signals =
0428         SIGNAL_TYPE_DVI_SINGLE_LINK |
0429         SIGNAL_TYPE_DVI_DUAL_LINK |
0430         SIGNAL_TYPE_LVDS |
0431         SIGNAL_TYPE_DISPLAY_PORT |
0432         SIGNAL_TYPE_DISPLAY_PORT_MST |
0433         SIGNAL_TYPE_EDP |
0434         SIGNAL_TYPE_HDMI_TYPE_A;
0435
0436     /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
0437      * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
0438      * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
0439      * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
0440      * Prefer DIG assignment is decided by board design.
0441      * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
0442      * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
0443      * By this, adding DIGG should not hurt DCE 8.0.
0444      * This will let DCE 8.1 share DCE 8.0 as much as possible
0445      */
0446
0447     enc10->link_regs = link_regs;
0448     enc10->aux_regs = aux_regs;
0449     enc10->hpd_regs = hpd_regs;
0450     enc10->link_shift = link_shift;
0451     enc10->link_mask = link_mask;
0452
0453     switch (enc10->base.transmitter) {
0454     case TRANSMITTER_UNIPHY_A:
0455         enc10->base.preferred_engine = ENGINE_ID_DIGA;
0456     break;
0457     case TRANSMITTER_UNIPHY_B:
0458         enc10->base.preferred_engine = ENGINE_ID_DIGB;
0459     break;
0460     case TRANSMITTER_UNIPHY_C:
0461         enc10->base.preferred_engine = ENGINE_ID_DIGC;
0462     break;
0463     case TRANSMITTER_UNIPHY_D:
0464         enc10->base.preferred_engine = ENGINE_ID_DIGD;
0465     break;
0466     case TRANSMITTER_UNIPHY_E:
0467         enc10->base.preferred_engine = ENGINE_ID_DIGE;
0468     break;
0469     case TRANSMITTER_UNIPHY_F:
0470         enc10->base.preferred_engine = ENGINE_ID_DIGF;
0471     break;
0472     case TRANSMITTER_UNIPHY_G:
0473         enc10->base.preferred_engine = ENGINE_ID_DIGG;
0474     break;
0475     default:
0476         ASSERT_CRITICAL(false);
0477         enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
0478     }
0479
0480     /* default to one to mirror Windows behavior */
0481     enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
0482
0483     result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
0484                         enc10->base.id, &bp_cap_info);
0485
0486     /* Override features with DCE-specific values */
0487     if (result == BP_RESULT_OK) {
0488         enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
0489                 bp_cap_info.DP_HBR2_EN;
0490         enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
0491                 bp_cap_info.DP_HBR3_EN;
0492         enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
0493         enc10->base.features.flags.bits.DP_IS_USB_C =
0494                 bp_cap_info.DP_IS_USB_C;
0495     } else {
0496         DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
0497                 __func__,
0498                 result);
0499     }
0500     if (enc10->base.ctx->dc->debug.hdmi20_disable) {
0501         enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
0502     }
0503 }