dc/dcn20/dcn20_hwseq.h

0001 /*
0002 * Copyright 2016 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef __DC_HWSS_DCN20_H__
0027 #define __DC_HWSS_DCN20_H__
0028
0029 #include "hw_sequencer_private.h"
0030
0031 bool dcn20_set_blend_lut(
0032     struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
0033 bool dcn20_set_shaper_3dlut(
0034     struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
0035 void dcn20_program_front_end_for_ctx(
0036         struct dc *dc,
0037         struct dc_state *context);
0038 void dcn20_post_unlock_program_front_end(
0039         struct dc *dc,
0040         struct dc_state *context);
0041 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
0042 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
0043 bool dcn20_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
0044             const struct dc_plane_state *plane_state);
0045 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
0046             const struct dc_stream_state *stream);
0047 void dcn20_program_output_csc(struct dc *dc,
0048         struct pipe_ctx *pipe_ctx,
0049         enum dc_color_space colorspace,
0050         uint16_t *matrix,
0051         int opp_id);
0052 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx);
0053 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
0054         struct dc_link_settings *link_settings);
0055 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx);
0056 void dcn20_disable_pixel_data(
0057         struct dc *dc,
0058         struct pipe_ctx *pipe_ctx,
0059         bool blank);
0060 void dcn20_blank_pixel_data(
0061         struct dc *dc,
0062         struct pipe_ctx *pipe_ctx,
0063         bool blank);
0064 void dcn20_pipe_control_lock(
0065     struct dc *dc,
0066     struct pipe_ctx *pipe,
0067     bool lock);
0068 void dcn20_prepare_bandwidth(
0069         struct dc *dc,
0070         struct dc_state *context);
0071 void dcn20_optimize_bandwidth(
0072         struct dc *dc,
0073         struct dc_state *context);
0074 bool dcn20_update_bandwidth(
0075         struct dc *dc,
0076         struct dc_state *context);
0077 void dcn20_reset_hw_ctx_wrap(
0078         struct dc *dc,
0079         struct dc_state *context);
0080 enum dc_status dcn20_enable_stream_timing(
0081         struct pipe_ctx *pipe_ctx,
0082         struct dc_state *context,
0083         struct dc *dc);
0084 void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx);
0085 void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx);
0086 void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);
0087 void dcn20_init_blank(
0088         struct dc *dc,
0089         struct timing_generator *tg);
0090 void dcn20_disable_vga(
0091     struct dce_hwseq *hws);
0092 void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);
0093 void dcn20_enable_power_gating_plane(
0094     struct dce_hwseq *hws,
0095     bool enable);
0096 void dcn20_dpp_pg_control(
0097         struct dce_hwseq *hws,
0098         unsigned int dpp_inst,
0099         bool power_on);
0100 void dcn20_hubp_pg_control(
0101         struct dce_hwseq *hws,
0102         unsigned int hubp_inst,
0103         bool power_on);
0104 void dcn20_program_triple_buffer(
0105     const struct dc *dc,
0106     struct pipe_ctx *pipe_ctx,
0107     bool enable_triple_buffer);
0108 void dcn20_enable_writeback(
0109         struct dc *dc,
0110         struct dc_writeback_info *wb_info,
0111         struct dc_state *context);
0112 void dcn20_disable_writeback(
0113         struct dc *dc,
0114         unsigned int dwb_pipe_inst);
0115 void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
0116 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx);
0117 void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx);
0118 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx);
0119 void dcn20_init_vm_ctx(
0120         struct dce_hwseq *hws,
0121         struct dc *dc,
0122         struct dc_virtual_addr_space_config *va_config,
0123         int vmid);
0124 void dcn20_set_flip_control_gsl(
0125         struct pipe_ctx *pipe_ctx,
0126         bool flip_immediate);
0127 void dcn20_dsc_pg_control(
0128         struct dce_hwseq *hws,
0129         unsigned int dsc_inst,
0130         bool power_on);
0131 void dcn20_fpga_init_hw(struct dc *dc);
0132 bool dcn20_wait_for_blank_complete(
0133         struct output_pixel_processor *opp);
0134 void dcn20_dccg_init(struct dce_hwseq *hws);
0135 int dcn20_init_sys_ctx(struct dce_hwseq *hws,
0136         struct dc *dc,
0137         struct dc_phy_addr_space_config *pa_config);
0138
0139 #ifndef TRIM_FSFT
0140 bool dcn20_optimize_timing_for_fsft(struct dc *dc,
0141         struct dc_crtc_timing *timing,
0142         unsigned int max_input_rate_in_khz);
0143 #endif
0144
0145 void dcn20_set_disp_pattern_generator(const struct dc *dc,
0146         struct pipe_ctx *pipe_ctx,
0147         enum controller_dp_test_pattern test_pattern,
0148         enum controller_dp_color_space color_space,
0149         enum dc_color_depth color_depth,
0150         const struct tg_color *solid_color,
0151         int width, int height, int offset);
0152
0153 void dcn20_update_visual_confirm_color(struct dc *dc,
0154         struct pipe_ctx *pipe_ctx,
0155         struct tg_color *color,
0156         int mpcc_id);
0157
0158 #endif /* __DC_HWSS_DCN20_H__ */
0159